Build a co-processor in UDB with Verilog in PSOC 5LP?

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cross mob
Anonymous
Not applicable

Hi, 

   

I am looking for example designs which uses the UDB in 5LP to work closely with the CPU. 

   

I need to write 32b data to UDB and read from result from the UDB. My verilog in UDB will do some custom computation. The closest I saw on the Cypress is the fan control but it uses functions like FanController_GetActualSpeed, is that an API or do I have access to the source codes? 

   

Are there any ref designs which uses the registers in UDB like memory mapped registers? 

   

Thank you! 

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1 Solution
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Welcome in the forum.

   

Start here for an example and do not forget to look into Brad's blog.

   

There are no memory-mapped registers in the UDBs but you can address the (few) registers in an UDB-based component directly.

   

 

   

Bob

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2 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Welcome in the forum.

   

Start here for an example and do not forget to look into Brad's blog.

   

There are no memory-mapped registers in the UDBs but you can address the (few) registers in an UDB-based component directly.

   

 

   

Bob

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Anonymous
Not applicable

That's cool Bob. Thank you. 

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