Hello,
I think that (maybe) there is a bug in the subtraction verilog implementation of 2 variables :
The following module is a saw generator with an incremented offset. If you change the "+ offset" in "- offset", the result is completely false (uncomment the next line). If you convert “-x“ in “~x + 1” the result is correct. To visualize the result, simply connect the DA to the outp, and clock the module with a 100kHz, for example…
Jean-Louis
`include "cypress.v"//`#end` -- edit above this line, do not edit this line// Generated on 05/26/2010 at 12:40
// Component: bugtest
module bugtest (
outp,
clk
);
output [7:0] outp;
input clk;
//`#start body` -- edit after this line, do not edit this line
reg [7:0] outp;
reg [15:0] offset;
reg [4:0] saw;
always @(posedge clk)
begin
// saw generator
saw <= saw + 1;
// offset
offset <= offset + 1;
// add is OK
outp <= {3'b0, saw} + offset[15:8];
// BUG if sub
// outp <= {3'b0, saw} - offset[15:8];
// corrected sub is OK
// outp <= {3'b0, saw} + ~offset[15:8] + 1;
end
//`#end` -- edit above this line, do not edit this line
endmodule
