PSOC3,5 FIFO capture fails with external clock signal

[VlYe_281166]

Trying to build fine frequency meter I discover that capture function fail to work in case of external measuring signal used.

   

I use sequential capturing on terminal count of Counter_1. Then I calculate difference between two neighbor FIFO values. 

   

 See attached setup.

   

If I use as test signal internally generated Clock2 everything works fine.

   

But in any case of using external signal from the port pin(doesn't matter as digital input or analog with comparator) lead to zeroes in FIFO status bits.

   

This is absolutely the same for PSOC3 and PSOC5. Tests were done on CY8KIT-003 and CY8KIT-014.  

[VlYe_281166]

 Solved in collaboration with Jibin Thomas (many thanks!).

   

    This bug exists in version 1.50 of Counter and will be fixed in v2.0. Till this use v1.20.