Why the length of WR_FIFO is longer than what I want?

[Anonymous]

I use the 68013A, GPIF mode, the FIFO write, found that each write of n data , the length of WR_FIFO signal is longer than n datas' length, the result is that n+1 datas wrote into the FIFO. why ?

[Anonymous]

Hi,

   

Please check whether you have a state after the WR_FIFO signal assertion which deasserts this signal and jump to the idele state after that stste.

   

Also if you can attach the firmware and gpif waveform I will be able to help you more on this.

   

-Shubham