SAR ADC Clock Frequency issues

[Anonymous]

Hi.. I'm facing a couple of funny problems...

   

I want to run my PSoC 5 as fast as possible, so I set the IMO to 48MHz and the PLL to 76MHz (the fastest it'll go with the error limits not exceeding 80MHz). The UART complains that the error in clock is too much. So I pulled down the IMO slower; the only possible setting is the slowest, i.e. 3MHz. so the first Q is

   

1. Is it ok to run the PLL this way? (3M input and 76M output?)

   

Then I added a pair of SAR ADCs, which now complain that the internal clock frequency is too high and can at most be 18MHz. I have selected external clocking and am providing 18M to it. (See attached). Now the only way to fix that is to slow my PLL down or use only IMO directly; thereby slowing the entire chip to a crawl.

   

2. What is the workaround?

       

Thanks in advance,

   

Abhijit K

[Anonymous]

Just debugged this myself.  The code is not very shrewd about idenitfying the clock.  It expects the name of the clock (as appearing in the list of clocks) to be $INSTANCE_NAME_theACLK.  This is the easiest workaround.

   

The hard way around that is to modify the code for the SAR to not do the check or to use a different naming convention.  The appropriate file to look at is: Program Files\Cypress\PSoC Creator\1.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\ADC_SAR_v1_50\Custom\cyadcsarcustomizer.cs.   Look at the function VerifyClock() at line 85.  I also modified the error reporting on line 103 to report the actual frequency in addition to the range it should be in.  The error string is located in cyadcsarcontrol.resx.

   

Unfortunately, since the instance name is part of the expected clock name, you must have two external clock source if you use two SARs.

   

At some point, Cypress needs to fix this.  In addition, they need to expose the hardware control of the SAR input mux.