Single Write Transfer S0 lasts for several clocks!!!!!!!!

[Anonymous]

I writing a basic GPIF master firmware that will use EP2 as out bulk 512.

   

My waveform is just the one for single write in the gpif primer, but when I run it I see in my logic analyzer that state S0 stays for a lot of clocks. Obvioulsy this keeps my WEN low for several clocks writing more than one.

   

Can anyone help me out?

       

This is an image of my logic analyzer for you to see the S0 (00) lasting a lot of clocks.

[Anonymous]

Please post your .gpf file here, it would help us have an idea of what you're trying to achieve.

   

Looking at your .png file I assume you've taken the capture of WEN staying low and then making a transition, the bus state with no value mentioned is the data you're clocking in. Please confirm.

   

Regards,

   

Anand