J-link (JTAG) schematics

[Anonymous]

Hi,

   

In DVK schematics, pin 15 (N_SRST) is not connected to any pins of FX3.0. However, in the J-Link datasheet, this pin (RESET) is defined to be connected to target CPU reset signal. Is it ok to leave this pin unconnected?

   

Thanks,

   

Nazila

[Anonymous]

FX3 JTAG controller has a power on reset mechanism, but we recommend hooking up TRST to your JTAG Master.

   

if you do not intend to use JTAG Interface then it can be left floating.

                   

  “What should the connection be on JTAG interface if we don’t use it?”

      It is a No Connect if it is not used

[Anonymous]

Thanks! But I am not asking about (N_TRST: pin 3). I am asking about pin 15 which is N_SRST! which in schematics is not connected to any pin on Cypress FX3

[Anonymous]

 Hi,

   

This is intentional. We've a separate circuitry to handle the Reset of FX3 so we're not connecting N_SRST to the reset of FX3.

   

Regards,

   

Anand