Driving multiple Seven Segment Displays - The PSoC Way!

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Anonymous
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Driving six 7-segment displays using PSoC to display numbers was a requirement which I came across.

   

This function was a jsut small portion of several other tasks which PSoC was performing. So, it was important to reduce the onus on the CPU from this task.

   

The programmable hardware available in PSoC can be put to best use in such a scenario.

   

The solution was to build a custom component to do the house keeping task of refreshing the 7-segment displays.

   

The schematic of the custom component is shown below:

   

 

   

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Bob_Marlowe
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Hi,

   

I expanded my 7-Seg-display implementation with two more logical inputs

   

1: Display Test (Outputs all segments "On")

   

2: Display Blank (Outputs all segments "Off, can be used with a PRISM-Module to control the intensity)

   

Regards, Bob

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Anonymous
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From the snap-shot of the schematic attached, it can be seen that implementation of this fuctionality requires Control Registers, Look Up Tables and Digital Muxes.

   

1) 6 Control Registers which are 4-bit wide each contain the lower nibble value of the decimal number to be displayed (In this case, the upper nibble has no significance as it would be '3' in ASCII number representation).

   

2) 4 Digital Muxes are used of width 8-bits.The lower 6-bits are utilized but the upper two are not.

   

3) LUT_1 generates an 8-bit output depending upon the input from Mux. This is connected to the segments of the display units.

   

4) LUT_2 is a Modulo-6 sequential counter which counts from 0 through 5 upon every Clock.

   

5) LUT_3’s output determines the display unit which has to display by generating a corresponding ‘High’ depending upon the value from LUT_2. At any given point of time, only 1 bit will remain high out of the 6 output bits available. (Assuming it's a Common Anode Configuration).

   

Working: LUT_2 is a modulo 6 counter which counts from 0 through 5 upon clock input. The 3 bit output which is generated is used as select lines for the Digital Mux and also as input to LUT_3.
When LUT_2 output is 0, the bits from Control_Reg_0 is passed to LUT_1 via Mux, and an eight bit output drives the corresponding segments of the display. Meanwhile LUT_3 gives a high on Selection0 which chooses the first 7-Segment display unit.
Similarly upon subsequent increment of the LUT_2 value on clock input, the next Control Register value is used and corresponding Common Anode terminal is made high.

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Anonymous
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The snap-shot of the symbol for the component is attached.

   

The symbol has the following terminals:

   

1) A Clock Input

   

2) Segment Output Terminals [7:0] (output)

   

3) Selection Terminals [5:0] to the six 7-segment units (output)

   

 

   

The Clock input is selected such that there is no flickering in the display. Segment terminals is to drive the Segments of the display units and Selection terminal is to select a given display unit at a given point of time.

   

The custom component is implemented completely in hardware. None of the component used inside requires any API to start it, but API.h and API.c files should be created to write the values to be displayed to the control registers.

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Anonymous
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Anonymous
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I was unable to paste the snap-shot with the post, hence attaching it with this comment.

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Bob_Marlowe
Level 10
Level 10
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Hi,

   

I expanded my 7-Seg-display implementation with two more logical inputs

   

1: Display Test (Outputs all segments "On")

   

2: Display Blank (Outputs all segments "Off, can be used with a PRISM-Module to control the intensity)

   

Regards, Bob

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Anonymous
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An interesting approach! Nice work.

   

We normally add a little bit of dead time ie turning the segments all off before switching the common. Addin this little dead time, could reduce chances of "LEAKAGE" or "GHOST image" across digits. May be it is easy to do in hardware as well...

Anonymous
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Hi Bob Marlowe,

   

 

   

That's a useful additional feature to have in the component !

   

The LUT can have upto 5 inputs, so it's a good idea to have the test option.

   

Use of PrISM to drive the LEDs sounds fun. I haven't intergated it though. The frequency of the operation of PrISM should be greater than the refresh rate of the 7-segments LEDs.

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Anonymous
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Hi lleung,

   

 

   

Thank you for the advice. Cross talk between the two 7-segment displays can be avoided by providing the dead band.

   

I guess the cross talk gets more pronounced if the refresh rate goes higher. It is possible to eliminate the cross-talk in hardware by using an "OFF" command (by switching off all the LEDs) on every display of the 7-segment unit.

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Anonymous
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How about doing in the PSoC way, ie by using the hardware blocks

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Anonymous
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Yes lleung, definitely possible.

   

Another 4 input 8 output registered LUT Component which updates on the falling edge of the clock can be used to update the value of 0x00 to turn off the 7-segment for the second half period. This will eliminate the cross-talk between two adjacent 7-segment units. An extra NOT Gate will be required to invert the clock input of the LUT Component.

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Bob_Marlowe
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Oh, yes,

   

just another difference to my approach (which is not a module):

   

I used a PWM to generate the clocks and while increasing the digit-counter, I switched off the display via my "BlankDisplay" input to the LUT

   

Regards, Bob

Anonymous
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 Yes,

   

Use the PWM with the output as clock to the counter, and with PWM to gate the output of segment

   

1. brightness control by control the pwm duty cycle

   

2. as long as the duty cycle is not 100 %, the dead time is achieved automatically

   

Killing two birds with 1 stone

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Bob_Marlowe
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Hi Community,

   

here is my approach to seven-segment-displays

   

Happy coding

   

Bob

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