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Hello All,
I noticed that the latest ADC requires external bypassing on pin 0[4] or 0[2] to reach its full speed of 700 KSPS (dropped from the earlier advertised 1MSPS?) However, on the -050 DVK, the hardware schematics depict the connection of the decoupling capacitors at pin 0[3] or 3[2]. Cypress support, are you aware of this?
Alex
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PSoC 5LP
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Based on what I see from the PSoC 3 DVK and architecture, it looks like the DVK was designed with the PSoC 3's decoupling structure in mind. I think this will probably need a PCB revision from Cypress to fix for PSoC 5.
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I think the capacitors you mean are for the external reference. (At least when I'm looking at page 38, in the box called 'voltage reference') So you would need to add the ADC decoupling condensators on your own.
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Based on what I see from the PSoC 3 DVK and architecture, it looks like the DVK was designed with the PSoC 3's decoupling structure in mind. I think this will probably need a PCB revision from Cypress to fix for PSoC 5.
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On the kits like Kit-050 a user could easily solder the refernce capacitor on the protoarea. I believe both the reference pins for the SAR ADC are brought out in to the proto space.
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Hi,
You can use pins P0[2] and P0[4] to which the capacitor is to be connected when internal bypass with capacitor mode is selected.