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I use 'slave-fifo' and 'bulkout-auto' mode to transfer data between pc and FPGA.
This is the final problem, i find it during a painful debugging:
1、I send a 512bytes bulk to 68013
2、68013 get this bulk, then the EP2PF=1, FLAGB=1
3、FPGA let the FIFOADR=10,
4、After 2 period, SLOE=1,ready to read data from 68013
5、After a period,SLRD=1,read data
6、read 512bytes,SLOE\SLED=0,stop reading
It shoud work properly,but sometimes one or two bytes are losing like this:
A right transmission is:
0x00 0x01 0x02 0x03 0x04 0x05......................0xff --ep2empty=1
fpga recieved 512 bytes
but sometimes it likes this:
0x00 0x01 0x03 0x04 0x05 0x06........................0xff --ep2empty=1
fpga recived 511 bytes
I have changed three chips, the problem has always been...
Regards,
Sky.
Solved! Go to Solution.
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Hi
As you have mentioned that only 511 bytes will be read and empty flag will be set, could you please take a trace and check whether it is sending 512 bytes or not.Could you please share the entire project?
Regards,
Vikas
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Hi
As you have mentioned that only 511 bytes will be read and empty flag will be set, could you please take a trace and check whether it is sending 512 bytes or not.Could you please share the entire project?
Regards,
Vikas
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HI.
VAVC.
Thanks for your reply.
I used the EP2PF and set the EP2FIFOPFX value to the FLAGB will be set when a 512bytes bulk has been ready to commit.
So, i think the data that PC to 68013 is right.
My codes associated PC to 68013 to fpga is as follows:
68013 init:
void TD_Init( void )
{ // Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
PINFLAGSAB = 0x4A; // FLAGB - EP2PF ,FLAGA - EP6EF
SYNCDELAY;
PINFLAGSCD = 0x08; // FLAGC - EP2EF
SYNCDELAY;
PORTACFG |= 0x80;
SYNCDELAY;
IFCONFIG = 0x03; // for async? for sync?
SYNCDELAY;
FIFOPINPOLAR |= 0x3F;
SYNCDELAY;
CPUCS |= 0x02;
SYNCDELAY;
REVCTL = 0x01;
SYNCDELAY;
EP4CFG = 0x01; //clear valid bit
SYNCDELAY;
EP8CFG = 0x01; //clear valid bit
SYNCDELAY;
EP2CFG = 0xA0; //out 512 bytes, 4x, bulk
SYNCDELAY;
EP6CFG = 0xE0; // in 512 bytes, 4x, bulk
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
EP2FIFOCFG = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
SYNCDELAY;
EP6FIFOCFG = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x09; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
SYNCDELAY;
EP6AUTOINLENH = 0x02;
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
EP2FIFOPFH = 0x88;
SYNCDELAY;
EP2FIFOPFL = 0x00;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
}
68013 reset(called when error,a EP0 vendor):
BOOL RstAll(void)
{
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0X02;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x10; //8bits
SYNCDELAY;
EP6FIFOCFG = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x09
;
SYNCDELAY;
EP6AUTOINLENH = 0x02;
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
INPKTEND = 0x84;
SYNCDELAY;
return( TRUE );
}
FPGA, read from 68013:
-----------FULL------------
when full =>
case con_full is
when 0 =>
usb_data_en<='0';
fifo_utr_write<='0';
sloe<='0';
slrd<='0';
fifoadr<="00";
if usb_full='1' then
con_full:=con_full+1;
else
con_full:=0;
end if;
when 1 =>
sloe<='1';
con_full:=con_full+1;
when 2 =>
con_full:=con_full+1;
when 3 =>
slrd<='1';
fifo_utr_write<='1';
con_full:=con_full+1;
when others =>
case fifo_utr_num_w_buffer is
when "000111111101" =>
con_full:=0;
when "001111111101" =>
con_full:=0;
when "010111111101" =>
con_full:=0;
when "011111111101" =>
usb_check(15 downto 8)<=usb_data_in(7 downto 0);
when "011111111110" =>
usb_check(7 downto 0)<=usb_data_in(7 downto 0);
sloe<='0';
slrd<='0';
fifo_utr_write<='0';
when "100000000000" =>
usb_state<=judge;
con_full:=0;
when others =>
fifo_utr_write<=fifo_utr_write;
end case;
end case;
Regards,
Vikas
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Hi.
After trial, I find that the losing bytes always behind lost of 0x00 like this:
Regards,
Sky