Learning Verilog

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HuEl_264296
Level 5
Level 5
First like given 25 sign-ins First solution authored

Now that I'm going to be using the PSoC 5 as my microcontroller of choice, I would like to learn Verilog so I can create my own peripherals for it.

   

I have spent some time searching the web for Verilog learning resources (especially ASIC World), and I feel I've learned quite a few things about it, however, I also feel that there's a big hole in my understanding. This is because there is something that none of the resources seem to teach.

   

Once I know the syntax, how do I go about designing a Verilog peripheral?

   

What I mean is, I'm still baffled by the designs people create in Verilog. E.G. Why did they do it that way, not the obviously much simpler way? For example, I came across this code:

   
task add;      // task definition  input a, b;   // two input argument ports  output c;     // one output argument port  reg R;        // register declaration  begin    R = 1;    if (a == b)      c = 1 & R;    else      c = 0;  end endtask 
   

There must be a good reason for the design, but it seems bizarre to me. I get the syntax, I see what it does, but I don't understnd why. Is there some resource for learning to think in Verilog?

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2 Replies
Anonymous
Not applicable

Hi Rocketmagnet,

   

 

   

The Component Author Guide will show you how to create components using Verilog. This also speaks about the use of Datapath tool for component creation.

   

If you want to get started quickly, you can watch component creation using Verilog training video which can be downloaded from here http://www.cypress.com/?rID=40330

   

 

   

The code which you have posted in your previous comment is that of a task which acts as an XNOR Gate. The output "c" is high when the inputs, "a" and "b" are same. Else, the output is low.

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HuEl_264296
Level 5
Level 5
First like given 25 sign-ins First solution authored

Thanks for the reply.

   

 

   

I can see what that Verilog example does, but what I don't understand is why they wrote it that way. Why didn't they do this instead?

   

 

   

 task add; // task definition

   

input a, b; // two input argument ports

   

output c; // one output argument port

   

begin

   

  if (a == b)

   

    c = 1;

   

  else

   

    c = 0;

   

  end

   

endtask 

   

 

   

And, lastly. Is there some teaching resource which explains these kinds of design decisions.

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