Question about Slave FIFO

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Anonymous
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Hi, in my design the FIFO is synchronously filled at aobut 6MBs, with streaming data coming from and ADC, with some glue logic in between (it's and SDR application). If I use isochronous endpoint with 1024 size packet and 1 packet per microframe, the bandwidth is roughly 8MBs. Since the USB side is faster than the FIFO side, it means (if I understood correctly, i'm new to USB) that some IN tokens will arrive when no data has been committed yet. What happens in this case? The host will wait or a zero packet length will be sent? 

   

I could shorten the isochronous packet length to match the bandwidths, 750 size packet gives 6MBs, but my understanding is that it is better to have a faster USB side, in order to avoid full FIFO event and loss of data (there is no other buffer in between). Am I correct?

   

One last question: when the FIFO goes from full to empty and the flag is de-asserted, is this flag change synchronous with IFCLK or it can happen asynchronously?

   

Thanks

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1 Reply
Anonymous
Not applicable

  Hi,

   

       See this http://www.cypress.com/?docID=20041      

 

   

       Flag change is synchronous; see timing diagrams in AC Electrical Characteristics section of Datasheet.

   

Thanks

   

Prajith

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