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1. Re: A few quick questions about cyfxslfifosync SDK Example:
userc_43736 Apr 19, 2012 7:56 PM (in response to userc_43736)Just to clarify Question #2, I see FLAGA and FLAGB go high when the address pins = 00, and I see them go low when the address pins = 01.
I need to know what those pins are configured for in the cyfxslfifosync example so I can make sense of how to program the external processor on the other end of the Slave FIFO interface! What hardware threads are they tied to, which one is for read, which one is for write, etc.,
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2. Re: A few quick questions about cyfxslfifosync SDK Example:
userc_43736 Apr 20, 2012 12:41 PM (in response to userc_43736)Anyone?