9 Replies Latest reply on May 3, 2012 5:00 AM by zhli_282171

    Missing data during FX3 sending data packets to PC

      I am using 32bits slave FIFO sychronous mode. I need to send 8KB data to PC, and I divided them into 16 packets, each packet is 128*32bits (512B), at the end of each packet, there is a packet_end signal. The endpoint buffer size was set to 1024B and I keep monitoring the full flag to make sure there is no overflow. However, I can not receive the whole 8KB data in the USB control center. Instead I only got 2342~2396B, each time different. Can anybody tell me what may be the proper problem? I am sure FPGA has write the data into CYUSB3014, and there is no overflow.