5 Replies Latest reply on Jun 11, 2012 9:14 PM by userc_39074

    Synch Slave Fifo



      I need some help. I am running the sync slave fifo example from AN65974. When I send data to the FX3 using the Control Center, it receives the bytes. I can verify this by setting a breakpoint in the U to P call back. But, when the FPGA sends data back to the FX3, it never arrives, or at least the P to U call back is not called. I see where others are using the slave fifo example and it is working, so I know it works, I just can't seem to make it work for me. I have attached  a logic analyzer screen showing my signals. Can someone tell me why this isn't working, or tell me how to get a simple example to work?


      The PCLK in the picute is running at 3.125MHz.



            Since U to P is working, but P to U is not, I think I must have a control signal wrong, but they look right to me. Any help would be very appreciated.     

        • 1. Re: Synch Slave Fifo

          Run the GPIF II Designer and select sync_slave_fifo_2bit from the Cypress Supplied Interfaces.  Verify that your connections match the I/O Matrix.


          I'm assuming you designed your interface around the slave FIFO interface described in the CYUSB3014.pdf datasheet.

          • 2. Re: Synch Slave Fifo

            Yes, I am using the 2 bit address slave fifo sync file in the GPIF II examples. The hardware is wired according to the data sheet.  I will verify the I/O matrix connections.



            • 3. Re: Synch Slave Fifo

              I checked my connections against the I/O Martix Configuration for sync_slave_fifo_2bit.cydsn and they are correct.


              I am using the FX3 DVK, rev 3 PCB. I have an interconnect PCB that I use to connect J77 on the DVK to an FPGA development kit. The FPGA is suppying the control signals as the master. The signal are as shown in the attached picture. Flag A is dedicated to thread 3. When I send bytes from the USB Control Center, I see Flag A go high as expected. The FPAG responds to this as expected and does a read, then a write. But, no words are received by the FX3. So, half of it work, that is the PC to FX3 to FPGA. The FPGA to FX3 to PC part is not working.


              Is there a minimum clock speed for the GPIF II interface?


              Has anyone made this example (AN65974) work?



              • 4. Re: Synch Slave Fifo

                Did you write enough data to the GPIF to reach the packet size or did you set the packet end signal? Unless you do at least on of this, you will not get any data from P-PORT....

                • 5. Re: Synch Slave Fifo

                  Hi Chris,


                  Yes, I am asserting PKEND in sync with the last SLWR as required from the FX3 data sheet. This can be seen in the image I attached.


                  At this point, all I really want to know is has anyone used the example code from AN65974 and made it work. If you have, what device did you use on the P port?

                  • 6. Re: Synch Slave Fifo

                     I have used the example code from AN65974 and made it work.


                    But my set up is FX3 back to back. I have made this path working FX3 master --> FX3 Slave --> PC. Master writes data to slave FX3 and then it can be read from PC.