About slave fifo clk

[Anonymous]

 Hi, 

   

In Slave firo sync operation, while the SLWR is asserted, data will be written into the FIFO, on every rising edge of the CLK and the FIFO pointer is incremented. 

   

Here my question is that, is there any option to sample the data from data bus on the falling edge of the CLK.

   

Thanks,

   

Subbarao.

[Anonymous]

 Have you tried changing the "Active clock edge" to "Negative" in the "Interface Definition" page of the GPIF II designer project.

   

Regards,

   

sai krishna.