Anonymous
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Jul 11, 2012
02:46 AM
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Jul 11, 2012
02:46 AM
Hi,
In Slave firo sync operation, while the SLWR is asserted, data will be written into the FIFO, on every rising edge of the CLK and the FIFO pointer is incremented.
Here my question is that, is there any option to sample the data from data bus on the falling edge of the CLK.
Thanks,
Subbarao.
1 Reply
Anonymous
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Jul 11, 2012
06:42 AM
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Jul 11, 2012
06:42 AM
Have you tried changing the "Active clock edge" to "Negative" in the "Interface Definition" page of the GPIF II designer project.
Regards,
sai krishna.