Analog analyser window in creator

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ShBa_282106
Level 3
Level 3
25 replies posted 10 replies posted 5 replies posted

Hi!

   

can anyone tell how to view analog analyser window in a creator project?

   

thnx in advance..

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HeLi_263931
Level 8
Level 8
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ShBa_282106
Level 3
Level 3
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Hi hli!

   

it shows error in renaming .exe file.

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Anonymous
Not applicable

logic analyser are used in digital circuit to compare logic high and low values.

   

anybody tell whats the use and what is analog logic analyser?

   

is analog logic analyser is equivalent to digital storage oscillioscope(DSO/CRO)?

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Bob_Marlowe
Level 10
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The analog analyzer is a part of the Creator 2.0 software and shows the routing of the analog resources performed for your chip-desing. Since some of the routes are including resistors you can get the information to alter the way the fitter assigns resources and routes.

   

Sadly this is not a logic analyzer

   

 

   

Bob

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HeLi_263931
Level 8
Level 8
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Actually, it is called "analog design viewer", and this name makes clear what it is.

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HeLi_263931
Level 8
Level 8
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@neha: you should not rename the exe file. You need to modify the shortcut calling the creator .exe (maybe you need to copy it beforehand to your shorthand), adding the parameter /adv (IIRC ).

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ShBa_282106
Level 3
Level 3
25 replies posted 10 replies posted 5 replies posted

Thnx All!

   

wish thr ws a logic analyser as well...

   

Regards,

   

Neha

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ETRO_SSN583
Level 9
Level 9
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Here is an open source design using PSOC 5 -

   

 

   

      http://beaversource.oregonstate.edu/projects/44x201107/wiki/WikiStart

   

 

   

Regards, Dana.

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Bob_Marlowe
Level 10
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... and hli built one based on PSoC5 too! Have a look at this thread http://www.cypress.com/?app=forum&id=2232&rID=65870 

   

 

   

Bob

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ETRO_SSN583
Level 9
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Analyzers also typically these days are accompanied by stimulus generators.

   

 

   

PSOC DMA = Pattern generator, ability to program digital I/O logic levels, timer/counter implementation of N

   

burst of N pulses generator, duty cycle, all easily achived by PSOC 3/5. Even the ability to verify PHY

   

characterisitcs of a digital interface.

   

 

   

A significant part of this can be implemented in Verilog to optimize speed. and simplicity of design.

   

 

   

Regards, Dana.

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