Can DMA write ?

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Anonymous
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Hello ALL

   

Can we write the data from the DMA to any register? For example we can write data from DMA to VDAC register similarly can i write data to any communication peripheral register or FIFO

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Anonymous
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Hi microHari,

   

 

   

It is possible to write data to a register via DMA if the Software access has Write ability.

   

 

   

It is possible to write into the FIFO register. Similarly, look into the Register Map to see if the communication peripheral register is software write capable to be written via DMA.

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Anonymous
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As an example, consider a FIFO register as shown below:

   

 

   

   

 

   

This FIFO has both Read / Write ability via software. DMA or CPU can access this FIFO register.

   

In general, the Status Registers will be Read Only. So, you can use DMA to read from those, but cannot be written.

   

 

   

 

   

Regards,

   

Gautam

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Anonymous
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 You mentioned about writing data into FIFO .. say supposingly i get data from ADC and try to output data from UART.

   

How do i configure? I will set UART as only RX and want to send data to hyperterminal. Will just write to FIFO from DMA send data or should i do something?

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Anonymous
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 And can you also tell me what is the Rx fifo register so that i acn write the data directly without CPU intervention......

   

And where do i find these registers....

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Bob_Marlowe
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Every  component using an UDB can have a FiFo integrated, UART, ADC, DAC, Timer etc. Whether the usermodule presents that FiFo to the user or not you'll find in the datasheet (search for FIFO).

   

There are some videos concerning "Datapath" which is a part of the UDB that can give you an insight into some internals of PSoC - chip design although I'm sure you'll have a bunch of new questions then 🙂

   

 

   

Bob 

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Bob_Marlowe
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Have a look at the DMA example-projects for PSoC3 or 5, they can show you how to use DMA (stay to 8-bit devices at first)

   

Bob

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Anonymous
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Gautam or others: what does the B0 of the identifier B0_UDB09_F0 mean? Does this mean Bank 0? My guess is that we're looking at the Fifo 0 of UDB09 (10th UDB) for the 0 bank. Is this correct?

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Anonymous
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Gautam or others: I also cannot find ANYWHERE in the registers document where there are static registers associated with the DMAC. There are registers assigned to USB an the DFB concerning masking of events associated with DMA calls, but I see absolutely nothing for the DMA controller itself. Are these instantiated in SRAM at runtime?

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Bob_Marlowe
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Yep, you (or rather the software) needs an algorithm to address the correct registers for the configuration. Keep in mind, that every connection made, every property of a component and the component istself is created by setting bits in "registers". The fitter-part of Creator contains an auto-router and an auto-placer to select the needed elements (have a look at the .rpt-file which elements there are) for your project and program the needed interconnections.

   

 

   

Bob

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Anonymous
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Bob: I'm well aware that Cyfitter does automatic routing and element selection (and not being able to control the latter means you cannot apriori use an absolute address, so all the register datasheet info is essentially an academic exercise). But it does not make any sense for the DMAC to have to go all the way out to SRAM to retrieve an address each and every time it's called. On the other hand, there is no evidence to suggest this is done otherwise...can someone PLEASE tell me the fine details here? WIthout truly understanding the architecture, I cannot say I really have an understanding.

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Bob_Marlowe
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Oh, sorry I thought you knew that DMA and Controller are part of the processor core. It is a quite usual way to just tell the DMAC the address of a TD and the DMAC works on that (it has of course some CPU-capabilities, internal ALU to calculate addresses, swapping bytes to change endianess etc. The DMAC accesses in parallel to the CPU memory to get its parameters and do the byte transfer. When you look at wikipedia for ARM and browse on the ARM website for details (registration might be needed) you'll get some informations about that. But I sweart, you'll get drowned in information so that it will turn out to get difficult to separate the important from the rest of the world. It is a challenge, but you are trying to understand 41 years of microprocessor evolution.

   

 

   

Bob

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Anonymous
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Bob: no, I did not know the DMA controller was integrated "inside the wall" with the ARM stuff, I would have thought those would be separate, but whatever. Nonetheless, there should be static registers associated with the DMA controller - it makes no sense to waste SRAM and bus bandwidth instantiating these into RAM. With the HC11, Z80, PIC32,etc., finding the info on all the DMA control registers (or anything else for that matter) requires 20 seconds of searching the datasheet. I just do not understand why everyone is acting like I'm crazy to want to know the fine grained details here - and apparently Microhari has the same questions that I do. I don't want spoon-fed templates, I want understanding and discussion.  I appreciate your time and Dana's time (you both have really been great at responding) but I'm puzzled why a Cypress employee can't just put some of my questions to rest...after all, the answer to my question just enables everyone who views the response to get their designs done better and faster! The DMA is a lynch-pin to interfacing the digital to the analog realm...the details MATTER!

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Bob_Marlowe
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Have a look at (if you hadn't before) at the PSoC5 TRM here     http://www.cypress.com/?docID=36586       and search for DMAC..

   
   

There is a brief description of the capabilities and principles of operation of the DMAC. together with the PHUB There are register names given, but I didn't search within the Cypress generated C-files for their occurences.

   
   

Knowing how DMA usually does work I take the DMAC as a black-box  and uses it that way. Since it is a fixed part within the system (Yes, I know you may give the DMAC some instructions to work on...) I rely on the (obviously working) implementation of the Cypress's programmers. So no need for me to change anything and I admitt also few interest in it because it is not changeable.

   
   

What I've read out of the above TRM:

   
   

The DMAC manages the 24 DMA-channels and the 128 TDs which indeed implies that the DMAC has internal memory apart from normal SRAM which it uses. The DMAC is an "internal peripheral" a stand-allone CPU bound by the PHUB to the system bus, even able to run its own program(s).

   
   

 

   
   

Bob

   
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Anonymous
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In the DMA project of transmitting data from ADC to VDAC , the whole operation goes witout knowing which register in the VDAC is written the value to generate the necessary output. Similarly if I were to writ the data from ADC to DMA and to say UART fifo (UART is configured for RX only) does the UART transmit data ??

   

or should i trigger an interrupt saying FIFO not empty and then transmit the data... i dont know hoew much of time is taken for entering the interrupt and transmitting data.

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Bob_Marlowe
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As I understand the internals of PSoC and DMA it works as:

   

The interfaces capable of DMA are using an internal "DataPath" component that is part of every UDB (make a Keyword Search for "DataPath" to get more information / videos about that). Part of the DataPath are two 4-stage deep FIFOs one used for input, one used for ouput. Signals for the state of the FIFO are generated internally and can be brought out to be controlled / read by other PSoC internal hardware. Due to the asynchroneous nature of these (ie. communication) devices DMA is always connected to the FIFOs and reads/writes from/to them. DataPaths may be connected to each other to form 16, 24 or 32 bit wide devices and so FIFOs with the appropiate width as well.

   

Another part beside the FIFO of the DataPath is an ALU (Arithmetic and Logical Unit) that can be microprogrammed (Yes, even by us!) to define what the ALU should calculate and do (reaf input FIFO, write output FIFO, test or set status bits...)

   

The DMA component is told from which register to read and that is (as I understand) always the FIFO which is presented under a readable name by a #define in the fitter.

   

If you are an applied masochist, you may search your entire project for the occurences of the register-name shown by the DMA-Wzard, and then using the found #define to go deeper and deeper until you really find the number of the UDB containing your DataPath.

   

 

   

Happy searching

   

Bob

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