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Hi,
Anyone have any ideas of what I should check, regarding why my first address always contains 0000h upon power-up restore, even though the rest of the locations appear to contain what was stored using autostore. All of my SRAM writes and reads are correct it is only upon restore that the first address read is incorrect and all zeros.
Thanks,
Rad
Solved! Go to Solution.
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Hi
We have a KB article which describes why this situation may occur.
http://www.cypress.com/?id=4&rID=39853.
If the solution of having a pull up on WE# does not work, this could be because the host controller is driving the WE# line low during bootup.
Details - http://www.cypress.com/?id=4&rID=57733
Regards
Ajay
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Does it happend when using software restore?
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Hi
We have a KB article which describes why this situation may occur.
http://www.cypress.com/?id=4&rID=39853.
If the solution of having a pull up on WE# does not work, this could be because the host controller is driving the WE# line low during bootup.
Details - http://www.cypress.com/?id=4&rID=57733
Regards
Ajay
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You can always learn something new
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Thanks for the replys!
lleung, I have not attempted a software restore yet. I will attempt this.
ajai, I already have a 10k pullup on the WEn line. I will add a 10k pullup to the CEn and try again.
Thanks,
Rad
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Hi Rad,
Having a pull up on CE# also may not help. Please check for the waveform on the WE# line, I suspect that the controller/FPGA which is interfaced to the memory is driving a strong low during its boot up .
The nvSRAM will be ready after 20ms on power on, the FPGA's and controllers typically take a longer time to boot. During this time, the I/O's of the controllers may be forced a strong low. If this happens, the pull up may not help. Is it possible to check with the controller if it can tri-state the lines/make the lines high during power up?
Regards,
Ajay
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Hi,
I wanted to let you know that my first address was being written due to my power down sequence. I was shutting down and grounding the inputs to the NVRAM before removing the power to the device. This in effect was setting all inputs to '0' and causing the write cycle.
Thanks,
Rad
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Hi Rad,
Yes, that can be a situation if the FPGA/microcontroller is powered down before the memory and memory sees zero on CE and WE line.
However, when the Vcc of the nvSRAM goes below Vswitch, all Address/data and control lines are tri-stated.
Regards,
Ajay