USB clock-locking

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Anonymous
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 The Registers TRM makes mention of USB clock-locking, but does not specify the location of the USB_LOCK bit. Is there clock-locking in the PSoC 5 architecture? It's not mentioned in the Architecture TRM, but then that wouldn't be the first omission there. 🙂

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Anonymous
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  In PSoC5 TRM -> section 16.4.2 USB Clock -> USB Mode Operation, there is an explanation given about USB clock locking to get 0.25% accurate clock for meeting Full Speed specs.

   

 

   

You can do it in the Clock configuration wizard of .cydwr file by using a 24MHz external crystal and enabling the clock double of USB block in it as shown in the attached image file.

   

 

   

Regards,

   

Kishore.

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Anonymous
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  In PSoC5 TRM -> section 16.4.2 USB Clock -> USB Mode Operation, there is an explanation given about USB clock locking to get 0.25% accurate clock for meeting Full Speed specs.

   

 

   

You can do it in the Clock configuration wizard of .cydwr file by using a 24MHz external crystal and enabling the clock double of USB block in it as shown in the attached image file.

   

 

   

Regards,

   

Kishore.

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Anonymous
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 If you are looking for enabling the USB lock bit in firmware, then you can refer to the PSoC5 Registers TRM -> 1.3.31 FASTCLK_IMO_CR -> Bit 6 corresponds to "usbclk_on".

   

 

   

Regards,

   

Kishore.

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Anonymous
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 Ah, thanks for the Arch TRM reference. Must have missed it earlier. Turns out USB_LOCK is probably enable_lock (USB_CR1[1]).

   

Thanks everyone!

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