Cache wait states

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Anonymous
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As the opearting frequency of CPU goes higher or BUS clock goes higher the no. of wait states also go higher. Is there a particular reason why the wait states are to be set for recommended values mentioned in the TRM or "0 " wait state will work.

   

and secondly

   

On a software reset does the Cache gets cleared?

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Anonymous
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Wait states are common in any Pipelined architecture. Instruction & data fetch happens from the same Flash. That is why we have Cache memory but only for intsruction data. So, some wait states are required to avoid any data clashes happening in the architecture.

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Anonymous
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I think Cache memory will be cleared by all types of resets...

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Bob_Marlowe
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The number of waitstates needed is automatically calculated at boot from the selected bus-clock speed. Only when changing the clock programatically an adjusting is required. Cache invalidation is mandantory for resets.

   

 

   

Bob

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ETRO_SSN583
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Wait state table from TRM, attached.

   

 

   

Regards, Dana.

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Anonymous
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We have an option to select no. of wait states basd on thre frequency of operation. So setting different wait states affect the functionality ???

   

And also what is the size of Cache in PSoC3 and PSoC5?

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ETRO_SSN583
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From the TRM -

   

 

   

5.1 Features
■ Instruction cache
■ Direct mapped
■ 128 bytes total cache memory
■ Registers to measure cache hit/miss ratios

   

 

   

Regards, Dana.

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ETRO_SSN583
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Based on TRM -

   

 

   

5.5 Wait States when Reading from Flash

   


The wait states refer to the number of bus clocks for which
cache must wait before data is available from flash. It varies
with the bus clock frequency.

   

 

   

I would interpret this to mean if you have too few wait states then

   

the cache miss/refill operation may get invalid data ?

   

 

   

Regards, Dana.

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ETRO_SSN583
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For the PSOC 3, from the TRM -

   

 

   

5.1 Features
■ Single Port Cache RAM (CRAM) – either one read or one write
■ Instruction cache
■ Fully associative
■ 512 bytes total cache memory in PSoC 3
■ Control to enable and disable cache
■ Designed to put flash into sleep automatically to save power

   

 

   

Regards, Dana.

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