Design 2 Code

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cross mob
Anonymous
Not applicable

 `include "cypress.v"

   

 

   

module Count4Bit_v1_0(

   

Clock,

   

Load,

   

Roll_enable,

   

Load_val,

   

Reset,

   

   

Count_out,

   

Min,

   

Max

   

);

   

 

   

parameter CountUp = 1;

   

 

   

input Clock;

   

input Load;

   

// input Up_down;

   

input Roll_enable;

   

input Load_val;

   

input Reset;

   

   

output Count_out;

   

output Min;

   

output Max;

   

   

// reg [3:0]Load_Reg;

   

reg [3:0]Count_out;

   

reg Load_Flag;

   

wire [3:0]Load_val;

   

   

//`#start body` -- edit after this line, do not edit this line

   

 

   

assign Min = (Count_out == 4'h0);

   

assign Max = (Count_out == 4'hf);

   

   

/* */

   

always @(posedge Clock or posedge Load)

   

if(Load)

   

begin

   

Load_Flag <= 1'b1;

   

end

   

else begin

   

Load_Flag <= 1'b0;

   

end

   

/* */

   

always @(posedge Clock or negedge Reset)

   

if (~Reset)

   

begin

   

Count_out <= 0;

   

end

   

else begin

   

if(Load_Flag)

   

begin

   

Count_out <= Load_val;

   

end

   

else

   

begin

   

Count_out <= CountUp?(Count_out[3:0]+{0,0,0,Roll_enable | ~Max}):(Count_out[3:0]-{0,0,0,Roll_enable | ~Min});

   

end

   

end

   

   

//`#end` -- edit above this line, do not edit this line

   

endmodule

   

//`#start footer` -- edit after this line, do not edit this line

   

//`#end` -- edit above this line, do not edit this line

   
        
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