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1)Hardware enviroment
Our board use CY7C68013A as synchronouse slave fifo, and a fpga as master.
CY7C68013A's CLKOUT at 12MHz, and FPGA's PLL use as input, output 40Mhz as CY7C68013A's IFCLK.
EEPROM is blank.
2)firmware and modification
use Cypress Suite USB 3.4.7\Firmware\Bulkloop example, and only modify BulkLoop.c as follow:
// CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
// CPUCS = (CPUCS & ~bmCLKSPD) |bmCLKSPD0; //24MHz
CPUCS = CPUCS & ~bmCLKSPD ; //12MHz CLKOUT
// set the slave FIFO interface to 48MHz
//IFCONFIG |= 0x40;
IFCONFIG = 0x03; //slave fifo, sync, external
3)host pc
windows 7 32bit.
Cypress Suite USB 3.4.7
CY3684_EZ-USB_FX2LP_DVK
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sorry, system tell me posted fail, but appear in the forum.
please delete the first 3 topics.
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The BulkLoop project attached.
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