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hi developers,
I would like to know about the input protection capabilities for PSoC I/O pins. specifically are there any protection diodes on I/O pins of any PSoC IC.if so how much power they can handle.?
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PSoC 1
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Most IC now have ESD protection on the pins, but I would use external clamping diodes in all IO's. For those IO's goes outside the board, and have chances of having some kinds of ESD, I would all TRANSORB type device as well.
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Most IC now have ESD protection on the pins, but I would use external clamping diodes in all IO's. For those IO's goes outside the board, and have chances of having some kinds of ESD, I would all TRANSORB type device as well.
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thanks lleung for the reply. i have some more doubts. this is regarding some fundamentals. would'nt the transient in the input lines if shorted to a supply rail through a protection diode, cause the whole of supply rail to increase its level and affect circuits connected to the same rail.?
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If the sourse of transient is more powerful in compare with rail voltage sourse, then the transient current can to change the rail voltage. Proportionally the difference between the sourses. In the case you should take care for transient current attenuating before it comes to input line.
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In CMOS there is a parasitic SCR if triggered will short the Vdd to Vss rail inside
the part and typically blows open the chip bond wire for Vdd rail. It is current sensitive,
and of course SCRs have a senstivity to dV/dT on the gate as well. The 29466 has a
latchup current rating of -25 & + 50 mA into any pin, above this SCR can potentially get
triggered. The part also has an actual latchup current rating of < 200 mA, so in this case
bond wire will remain intact.
If the SCR does not get triggered the input protection diodes will turn on and dump
charge into the substrate potentially causing logic and other circuits to potentially fault.
So use external clamps, preferably schottky diodes to make sure they tunr on before
internal protection diodes.
Some reference material http://www.ti.com/lit/an/sdya009c/sdya009c.pdf
Regards, Dana.
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In PSoC 1 device, you should not exceed 0.5V above Vdd and go 0.5V below Vss at any IO. This is the specification for continuous drive. As far as ESD is concerned, IOs can handle 2000V. For higher ESD handling capability, it is recommended to use transient suppressors like TPD1E10B09 at the ESD susceptible port pins.
If you are worried about transients of much longer duration (not ESD), you can zener diodes at the pins.
-Rajiv Badiger
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Zeners have very fast avalanche switching, so in the right application they can be
very beneficial. But their Vz >> Vdiodesilicon >> Vdiodeschottky. So if you are trying
to clamp I/O on transients, you need to use the lowest threshold device you can get
your hands on. For clamps on Vdd zener most appropriate.
Another approach to think about - http://www.digikey.com/Web%20Export/Supplier%20Content/AdvancedLinearDevices_1014/pdf/ald-tech-volta...
Regards, Dana.
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A couple more references -
http://www.fairchildsemi.com/an/AN/AN-600.pdf
http://www.zarlink.com/zarlink/msan107-appnote.pdf
Regards, Dana.