slaveFIFO2b_fpga_top Project Status
Project File: slavefifo2b_vhdl_feb20.xise Parser Errors: No Errors
Module Name: slaveFIFO2b_fpga_top Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
9 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 288 18,224 1%  
    Number used as Flip Flops 288      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 312 9,112 3%  
    Number used as logic 312 9,112 3%  
        Number using O6 output only 262      
        Number using O5 output only 3      
        Number using O5 and O6 47      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
Number of occupied Slices 117 2,278 5%  
Number of MUXCYs used 120 4,556 2%  
Number of LUT Flip Flop pairs used 343      
    Number with an unused Flip Flop 70 343 20%  
    Number with an unused LUT 31 343 9%  
    Number of fully used LUT-FF pairs 242 343 70%  
    Number of unique control sets 9      
    Number of slice register sites lost
        to control set restrictions
24 18,224 1%  
Number of bonded IOBs 52 232 22%  
    Number of LOCed IOBs 52 52 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 1 248 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.27      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Apr 8 15:42:04 201304 Warnings (0 new)7 Infos (0 new)
Translation ReportCurrentMon Apr 8 15:42:14 2013001 Info (0 new)
Map ReportCurrentMon Apr 8 15:42:30 201301 Warning (0 new)7 Infos (0 new)
Place and Route ReportCurrentMon Apr 8 15:42:46 2013002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Apr 8 15:42:56 201303 Warnings (0 new)4 Infos (0 new)
Bitgen ReportCurrentMon Apr 8 15:43:10 201301 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateMon Apr 8 15:43:10 2013
WebTalk Log FileOut of DateMon Apr 8 15:43:26 2013

Date Generated: 11/19/2013 - 18:38:52