clk_wiz_v3_6_2 Project Status (02/20/2013 - 14:45:58) | |||
Project File: | slavefifo2b_vhdl_feb20.xise | Parser Errors: | No Errors |
Module Name: | clk_wiz_v3_6_2 | Implementation State: | Programming File Not Generated |
Target Device: | xc6slx16-3csg324 |
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Product Version: | ISE 14.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Wed Feb 20 14:45:57 2013 | |
WebTalk Log File | Out of Date | Wed Feb 20 14:45:58 2013 |