Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (WebPack) - P.49d Target Family: Spartan6
OS Platform: NT Target Device: xc6slx16
Project ID (random number) e333ae5154d542c9a02c9b4e98c23735.89D869E116554898A2FD4B8E769E3913.8 Target Package: csg324
Registration ID __0_0_0 Target Speed: -3
Date Generated 2013-04-08T15:43:09 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz CPU Speed 2194 MHz
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz CPU Speed 2194 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=4
  • 8-bit up loadable accumulator=2
  • 9-bit updown loadable accumulator=2
Adders/Subtractors=3
  • 8-bit adder=1
  • 9-bit addsub=2
Comparators=4
  • 2-bit comparator greater=4
Counters=10
  • 2-bit down counter=4
  • 32-bit up counter=3
  • 4-bit up counter=3
FSMs=6 Multiplexers=29
  • 1-bit 2-to-1 multiplexer=13
  • 1-bit 7-to-1 multiplexer=1
  • 32-bit 2-to-1 multiplexer=4
  • 32-bit 7-to-1 multiplexer=1
  • 8-bit 2-to-1 multiplexer=2
  • 9-bit 2-to-1 multiplexer=8
RAMs=1
  • 256x32-bit dual-port block RAM=1
Registers=84
  • Flip-Flops=84
MiscellaneousStatistics
  • AGG_BONDED_IO=52
  • AGG_IO=52
  • AGG_LOCED_IO=52
  • AGG_SLICE=117
  • NUM_BONDED_IOB=52
  • NUM_BSFULL=242
  • NUM_BSLUTONLY=70
  • NUM_BSREGONLY=31
  • NUM_BSUSED=343
  • NUM_BUFG=2
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_IOB_FF=1
  • NUM_LOCED_IOB=52
  • NUM_LOGIC_O5ANDO6=47
  • NUM_LOGIC_O5ONLY=3
  • NUM_LOGIC_O6ONLY=262
  • NUM_LUT_RT_O5=3
  • NUM_LUT_RT_O6=3
  • NUM_OLOGIC2=1
  • NUM_PLL_ADV=1
  • NUM_RAMB8BWER=1
  • NUM_SLICEL=35
  • NUM_SLICEX=82
  • NUM_SLICE_CARRY4=30
  • NUM_SLICE_CONTROLSET=9
  • NUM_SLICE_CYINIT=365
  • NUM_SLICE_F7MUX=5
  • NUM_SLICE_FF=288
  • NUM_SLICE_UNUSEDCTRL=24
  • NUM_UNUSABLE_FF_BELS=24
NetStatistics
  • NumNets_Active=589
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=15
  • NumNodesOfType_Active_BOUNCEIN=71
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=8
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=97
  • NumNodesOfType_Active_CLKPINFEED=14
  • NumNodesOfType_Active_CNTRLPIN=123
  • NumNodesOfType_Active_DOUBLE=745
  • NumNodesOfType_Active_GENERIC=159
  • NumNodesOfType_Active_GLOBAL=53
  • NumNodesOfType_Active_INPUT=81
  • NumNodesOfType_Active_IOBIN2OUT=113
  • NumNodesOfType_Active_IOBOUTPUT=114
  • NumNodesOfType_Active_LUTINPUT=1642
  • NumNodesOfType_Active_OUTBOUND=581
  • NumNodesOfType_Active_OUTPUT=513
  • NumNodesOfType_Active_PADINPUT=72
  • NumNodesOfType_Active_PADOUTPUT=41
  • NumNodesOfType_Active_PINBOUNCE=322
  • NumNodesOfType_Active_PINFEED=1953
  • NumNodesOfType_Active_PINFEED1=1
  • NumNodesOfType_Active_PINFEED2=3
  • NumNodesOfType_Active_QUAD=960
  • NumNodesOfType_Active_REGINPUT=90
  • NumNodesOfType_Active_SINGLE=975
  • NumNodesOfType_Gnd_BOUNCEIN=50
  • NumNodesOfType_Gnd_CNTRLPIN=1
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_HGNDOUT=26
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_IOBINPUT=1
  • NumNodesOfType_Gnd_OUTBOUND=1
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PINBOUNCE=90
  • NumNodesOfType_Gnd_PINFEED=3
  • NumNodesOfType_Gnd_REGINPUT=90
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_GENERIC=3
  • NumNodesOfType_Vcc_HVCCOUT=38
  • NumNodesOfType_Vcc_INPUT=4
  • NumNodesOfType_Vcc_IOBIN2OUT=4
  • NumNodesOfType_Vcc_IOBOUTPUT=3
  • NumNodesOfType_Vcc_KVCCOUT=2
  • NumNodesOfType_Vcc_LUTINPUT=53
  • NumNodesOfType_Vcc_PADINPUT=3
  • NumNodesOfType_Vcc_PINFEED=62
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=27
  • IOB-IOBS=25
  • SLICEL-SLICEM=31
  • SLICEX-SLICEL=17
  • SLICEX-SLICEM=18
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • CARRY4=30
  • FF_SR=16
  • IOB=52
  • IOB_IMUX=41
  • IOB_INBUF=41
  • IOB_OUTBUF=43
  • LUT5=53
  • LUT6=312
  • OLOGIC2=1
  • OLOGIC2_OUTFF=1
  • PAD=52
  • PLL_ADV=1
  • PLL_ADV_PLL_ADV=1
  • RAMB8BWER=1
  • RAMB8BWER_RAMB8BWER=1
  • REG_SR=272
  • SELMUX2_1=5
  • SLICEL=35
  • SLICEX=82
 
Configuration Data
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
FF_SR
  • CK=[CK:16] [CK_INV:0]
  • SRINIT=[SRINIT0:14] [SRINIT1:2]
  • SYNC_ATTR=[ASYNC:16]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:43]
  • SLEW=[SLOW:43]
  • SUSPEND=[3STATE:43]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:1]
  • CLK1=[CLK1:0] [CLK1_INV:1]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:1]
  • CK1=[CK1_INV:1] [CK1:0]
  • DDR_ALIGNMENT=[NONE:1]
  • OUTFFTYPE=[DDR:1]
  • SRINIT_OQ=[0:1]
  • SRTYPE_OQ=[SYNC:1]
PLL_ADV
  • RST=[RST:0] [RST_INV:1]
PLL_ADV_PLL_ADV
  • BANDWIDTH=[OPTIMIZED:1]
  • CLK_FEEDBACK=[CLKFBOUT:1]
  • COMPENSATION=[SYSTEM_SYNCHRONOUS:1]
  • PLL_ADD_LEAKAGE=[2:1]
  • PLL_AVDD_COMP_SET=[2:1]
  • PLL_CLAMP_BYPASS=[FALSE:1]
  • PLL_CLAMP_REF_SEL=[1:1]
  • PLL_CLK0MX=[0:1]
  • PLL_CLK1MX=[0:1]
  • PLL_CLK2MX=[0:1]
  • PLL_CLK3MX=[0:1]
  • PLL_CLK4MX=[0:1]
  • PLL_CLK5MX=[0:1]
  • PLL_CLKBURST_CNT=[0:1]
  • PLL_CLKBURST_ENABLE=[TRUE:1]
  • PLL_CLKCNTRL=[0:1]
  • PLL_CLKFBMX=[0:1]
  • PLL_CLKFBOUT2_EDGE=[TRUE:1]
  • PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKFBOUT_EDGE=[TRUE:1]
  • PLL_CLKFBOUT_EN=[FALSE:1]
  • PLL_CLKFBOUT_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT0_EDGE=[TRUE:1]
  • PLL_CLKOUT0_EN=[FALSE:1]
  • PLL_CLKOUT0_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT1_EDGE=[TRUE:1]
  • PLL_CLKOUT1_EN=[FALSE:1]
  • PLL_CLKOUT1_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT2_EDGE=[TRUE:1]
  • PLL_CLKOUT2_EN=[FALSE:1]
  • PLL_CLKOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT3_EDGE=[TRUE:1]
  • PLL_CLKOUT3_EN=[FALSE:1]
  • PLL_CLKOUT3_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT4_EDGE=[TRUE:1]
  • PLL_CLKOUT4_EN=[FALSE:1]
  • PLL_CLKOUT4_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT5_EDGE=[TRUE:1]
  • PLL_CLKOUT5_EN=[FALSE:1]
  • PLL_CLKOUT5_NOCOUNT=[TRUE:1]
  • PLL_CLK_LOST_DETECT=[FALSE:1]
  • PLL_CP=[1:1]
  • PLL_CP_BIAS_TRIP_SHIFT=[TRUE:1]
  • PLL_CP_REPL=[1:1]
  • PLL_CP_RES=[0:1]
  • PLL_DIRECT_PATH_CNTRL=[TRUE:1]
  • PLL_DIVCLK_EDGE=[TRUE:1]
  • PLL_DIVCLK_NOCOUNT=[TRUE:1]
  • PLL_DVDD_COMP_SET=[2:1]
  • PLL_EN=[FALSE:1]
  • PLL_EN_DLY=[TRUE:1]
  • PLL_EN_LEAKAGE=[2:1]
  • PLL_EN_TCLK0=[TRUE:1]
  • PLL_EN_TCLK1=[TRUE:1]
  • PLL_EN_TCLK2=[TRUE:1]
  • PLL_EN_TCLK3=[TRUE:1]
  • PLL_EN_VCO0=[FALSE:1]
  • PLL_EN_VCO1=[FALSE:1]
  • PLL_EN_VCO2=[FALSE:1]
  • PLL_EN_VCO3=[FALSE:1]
  • PLL_EN_VCO4=[FALSE:1]
  • PLL_EN_VCO5=[FALSE:1]
  • PLL_EN_VCO6=[FALSE:1]
  • PLL_EN_VCO7=[FALSE:1]
  • PLL_EN_VCO_DIV1=[FALSE:1]
  • PLL_EN_VCO_DIV6=[TRUE:1]
  • PLL_INTFB=[0:1]
  • PLL_IO_CLKSRC=[0:1]
  • PLL_LFHF=[3:1]
  • PLL_LOCK_FB_DLY=[3:1]
  • PLL_LOCK_REF_DLY=[5:1]
  • PLL_MAN_LF_EN=[TRUE:1]
  • PLL_NBTI_EN=[TRUE:1]
  • PLL_PFD_CNTRL=[8:1]
  • PLL_PFD_DLY=[1:1]
  • PLL_PWRD_CFG=[FALSE:1]
  • PLL_REG_INPUT=[TRUE:1]
  • PLL_RES=[1:1]
  • PLL_SEL_SLIPD=[FALSE:1]
  • PLL_SKEW_CNTRL=[0:1]
  • PLL_TEST_IN_WINDOW=[FALSE:1]
  • PLL_VDD_SEL=[0:1]
  • PLL_VLFHIGH_DIS=[TRUE:1]
  • RST=[RST:0] [RST_INV:1]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[36:1]
  • DATA_WIDTH_B=[36:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[TRUE:1]
  • EN_RSTRAM_B=[TRUE:1]
  • RAM_MODE=[SDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[READ_FIRST:1]
  • WRITE_MODE_B=[READ_FIRST:1]
REG_SR
  • CK=[CK:272] [CK_INV:0]
  • LATCH_OR_FF=[FF:272]
  • SRINIT=[SRINIT0:265] [SRINIT1:7]
  • SYNC_ATTR=[ASYNC:272]
SLICEL
  • CLK=[CLK:33] [CLK_INV:0]
SLICEX
  • CLK=[CLK:60] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
CARRY4
  • CIN=25
  • CO3=25
  • CYINIT=5
  • DI0=28
  • DI1=28
  • DI2=28
  • DI3=25
  • O0=30
  • O1=28
  • O2=28
  • O3=28
  • S0=30
  • S1=28
  • S2=28
  • S3=28
FF_SR
  • CE=5
  • CK=16
  • D=16
  • Q=16
  • SR=16
IOB
  • I=41
  • O=43
  • PAD=52
  • T=32
IOB_IMUX
  • I=41
  • OUT=41
IOB_INBUF
  • OUT=41
  • PAD=41
IOB_OUTBUF
  • IN=43
  • OUT=43
  • TRI=32
LUT5
  • A1=29
  • A2=32
  • A3=24
  • A4=23
  • A5=43
  • O5=53
LUT6
  • A1=192
  • A2=250
  • A3=283
  • A4=295
  • A5=311
  • A6=312
  • O6=312
OLOGIC2
  • CLK0=1
  • CLK1=1
  • D1=1
  • D2=1
  • OCE=1
  • OQ=1
  • SR=1
OLOGIC2_OUTFF
  • CE=1
  • CK0=1
  • CK1=1
  • D1=1
  • D2=1
  • Q=1
  • SR=1
PAD
  • PAD=52
PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT0=1
  • LOCKED=1
  • RST=1
PLL_ADV_PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT0=1
  • LOCKED=1
  • RST=1
RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DOADO0=1
  • DOADO1=1
  • DOADO10=1
  • DOADO11=1
  • DOADO12=1
  • DOADO13=1
  • DOADO14=1
  • DOADO15=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • DOADO8=1
  • DOADO9=1
  • DOBDO0=1
  • DOBDO1=1
  • DOBDO10=1
  • DOBDO11=1
  • DOBDO12=1
  • DOBDO13=1
  • DOBDO14=1
  • DOBDO15=1
  • DOBDO2=1
  • DOBDO3=1
  • DOBDO4=1
  • DOBDO5=1
  • DOBDO6=1
  • DOBDO7=1
  • DOBDO8=1
  • DOBDO9=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DOADO0=1
  • DOADO1=1
  • DOADO10=1
  • DOADO11=1
  • DOADO12=1
  • DOADO13=1
  • DOADO14=1
  • DOADO15=1
  • DOADO2=1
  • DOADO3=1
  • DOADO4=1
  • DOADO5=1
  • DOADO6=1
  • DOADO7=1
  • DOADO8=1
  • DOADO9=1
  • DOBDO0=1
  • DOBDO1=1
  • DOBDO10=1
  • DOBDO11=1
  • DOBDO12=1
  • DOBDO13=1
  • DOBDO14=1
  • DOBDO15=1
  • DOBDO2=1
  • DOBDO3=1
  • DOBDO4=1
  • DOBDO5=1
  • DOBDO6=1
  • DOBDO7=1
  • DOBDO8=1
  • DOBDO9=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
REG_SR
  • CE=107
  • CK=272
  • D=272
  • Q=272
  • SR=272
SELMUX2_1
  • 0=5
  • 1=5
  • OUT=5
  • S0=5
SLICEL
  • A=1
  • A1=25
  • A2=25
  • A3=29
  • A4=30
  • A5=33
  • A6=33
  • AQ=32
  • AX=27
  • B=2
  • B1=28
  • B2=29
  • B3=31
  • B4=31
  • B5=31
  • B6=31
  • BMUX=1
  • BQ=29
  • BX=26
  • C1=30
  • C2=31
  • C3=33
  • C4=33
  • C5=33
  • C6=33
  • CE=24
  • CIN=25
  • CLK=33
  • CMUX=2
  • COUT=25
  • CQ=31
  • CX=31
  • D1=30
  • D2=30
  • D3=32
  • D4=32
  • D5=33
  • D6=33
  • DQ=28
  • DX=23
  • SR=33
SLICEX
  • A=35
  • A1=25
  • A2=39
  • A3=42
  • A4=43
  • A5=51
  • A6=51
  • AMUX=8
  • AQ=40
  • AX=22
  • B=22
  • B1=30
  • B2=41
  • B3=44
  • B4=46
  • B5=46
  • B6=46
  • BMUX=6
  • BQ=49
  • BX=20
  • C=23
  • C1=29
  • C2=41
  • C3=43
  • C4=43
  • C5=44
  • C6=45
  • CE=5
  • CLK=60
  • CMUX=9
  • CQ=42
  • CX=18
  • D=33
  • D1=20
  • D2=35
  • D3=35
  • D4=37
  • D5=40
  • D6=40
  • DMUX=17
  • DQ=21
  • DX=13
  • SR=60
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 6 5 0 0 0 0 0
bitgen 155 154 0 0 0 0 0
cse_server 80 80 0 0 0 0 0
map 158 156 0 0 0 0 0
ngcbuild 34 34 0 0 0 0 0
ngdbuild 170 170 0 0 0 0 0
par 156 155 0 0 0 0 0
trce 154 154 0 0 0 0 0
xst 308 304 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_VHDLSourceAnalysisStandard=VHDL-200X
PROP_intProjectCreationTimestamp=2013-02-20T11:35:01 PROP_intWbtProjectID=89D869E116554898A2FD4B8E769E3913
PROP_intWbtProjectIteration=8 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=8
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=37.037 clkin2_period=37.037 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=1 primtype_sel=PLL_BASE
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=true use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1 XST_NUM_ODDR2=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=167 NGDBUILD_NUM_FDCE=112 NGDBUILD_NUM_FDP=9
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=8 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3
NGDBUILD_NUM_IOBUF=32 NGDBUILD_NUM_LUT2=33 NGDBUILD_NUM_LUT3=55 NGDBUILD_NUM_LUT4=20
NGDBUILD_NUM_LUT5=59 NGDBUILD_NUM_LUT6=188 NGDBUILD_NUM_MUXCY=109 NGDBUILD_NUM_MUXF7=5
NGDBUILD_NUM_OBUF=11 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=114
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=167 NGDBUILD_NUM_FDCE=112 NGDBUILD_NUM_FDP=9
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=40 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3
NGDBUILD_NUM_LUT2=33 NGDBUILD_NUM_LUT3=55 NGDBUILD_NUM_LUT4=20 NGDBUILD_NUM_LUT5=59
NGDBUILD_NUM_LUT6=188 NGDBUILD_NUM_MUXCY=109 NGDBUILD_NUM_MUXF7=5 NGDBUILD_NUM_OBUF=11
NGDBUILD_NUM_OBUFT=32 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_PLL_ADV=1 NGDBUILD_NUM_RAMB8BWER=1
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=114
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5