clk_wiz_v3_6_2 Project Status (02/20/2013 - 14:45:58)
Project File: slavefifo2b_vhdl_feb20.xise Parser Errors: No Errors
Module Name: clk_wiz_v3_6_2 Implementation State: Programming File Not Generated
Target Device: xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 14.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateWed Feb 20 14:45:57 2013
WebTalk Log FileOut of DateWed Feb 20 14:45:58 2013

Date Generated: 02/20/2013 - 15:31:29