Static Timing Analysis

Project : PWMExample01
Build Time : 10/05/18 10:22:57
Device : CYBLE-212006-01
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(FFB) Clock_1(FFB) 12.000 MHz 12.000 MHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyHFCLK 12.000 MHz 12.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Clock To Output Section
+ Clock_1(FFB)
Source Destination Delay (ns)
\PWM:cy_m0s8_tcpwm_1\/line LED_GREEN(0)_PAD 15.616
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,3) 1 \PWM:cy_m0s8_tcpwm_1\ \PWM:cy_m0s8_tcpwm_1\/clock \PWM:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_207 \PWM:cy_m0s8_tcpwm_1\/line LED_GREEN(0)/pin_input 1.000
iocell1 P3[6] 1 LED_GREEN(0) LED_GREEN(0)/pin_input LED_GREEN(0)/pad_out 14.616
Route 1 LED_GREEN(0)_PAD LED_GREEN(0)/pad_out LED_GREEN(0)_PAD 0.000
Clock Clock path delay 0.000