Static Timing Analysis

Project : SGPIO_Target
Build Time : 08/12/13 15:57:37
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_intClock(FFB) ADC_intClock(FFB) 12.000 MHz 12.000 MHz N/A
Clock_1(FFB) Clock_1(FFB) 12.000 kHz 12.000 kHz N/A
Clock_3(FFB) Clock_3(FFB) 100.000 kHz 100.000 kHz N/A
Clock_4(FFB) Clock_4(FFB) 12.000 kHz 12.000 kHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 73.697 MHz
ADC_intClock CyHFCLK 12.000 MHz 12.000 MHz N/A
I2C_SCBCLK CyHFCLK 1.600 MHz 1.600 MHz N/A
Clock_2 CyHFCLK 1.000 MHz 1.000 MHz 45.880 MHz
Clock_3 CyHFCLK 100.000 kHz 100.000 kHz N/A
Clock_1 CyHFCLK 12.000 kHz 12.000 kHz N/A
Clock_4 CyHFCLK 12.000 kHz 12.000 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
I2C_SCBCLK(FFB) I2C_SCBCLK(FFB) 1.600 MHz 1.600 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SGPIO_Target:TargetBitCounter\/tc \SGPIO_Target:TargetShiftReg:u0\/cs_addr_0 45.880 MHz 21.796 978.204
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SGPIO_Target:TargetBitCounter\ \SGPIO_Target:TargetBitCounter\/clock \SGPIO_Target:TargetBitCounter\/tc 2.580
Route 1 \SGPIO_Target:tc\ \SGPIO_Target:TargetBitCounter\/tc \SGPIO_Target:cs_addr_0\/main_0 2.710
macrocell11 U(0,0) 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/main_0 \SGPIO_Target:cs_addr_0\/q 3.350
Route 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_0 5.986
datapathcell1 U(1,0) 1 \SGPIO_Target:TargetShiftReg:u0\ SETUP 7.170
Clock Skew 0.000
\SGPIO_Target:TargetBitCounter\/tc \SGPIO_Target:TargetShiftReg:u1\/cs_addr_0 45.886 MHz 21.793 978.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SGPIO_Target:TargetBitCounter\ \SGPIO_Target:TargetBitCounter\/clock \SGPIO_Target:TargetBitCounter\/tc 2.580
Route 1 \SGPIO_Target:tc\ \SGPIO_Target:TargetBitCounter\/tc \SGPIO_Target:cs_addr_0\/main_0 2.710
macrocell11 U(0,0) 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/main_0 \SGPIO_Target:cs_addr_0\/q 3.350
Route 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_0 5.983
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ SETUP 7.170
Clock Skew 0.000
\SGPIO_Target:sync_sm_1\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_0 50.015 MHz 19.994 980.006
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/clock_0 \SGPIO_Target:sync_sm_1\/q 1.250
Route 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/q \SGPIO_Target:cs_addr_0\/main_1 2.238
macrocell11 U(0,0) 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/main_1 \SGPIO_Target:cs_addr_0\/q 3.350
Route 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_0 5.986
datapathcell1 U(1,0) 1 \SGPIO_Target:TargetShiftReg:u0\ SETUP 7.170
Clock Skew 0.000
\SGPIO_Target:sync_sm_1\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_0 50.023 MHz 19.991 980.009
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/clock_0 \SGPIO_Target:sync_sm_1\/q 1.250
Route 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/q \SGPIO_Target:cs_addr_0\/main_1 2.238
macrocell11 U(0,0) 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/main_1 \SGPIO_Target:cs_addr_0\/q 3.350
Route 1 \SGPIO_Target:cs_addr_0\ \SGPIO_Target:cs_addr_0\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_0 5.983
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ SETUP 7.170
Clock Skew 0.000
\SGPIO_Target:falling_sclock\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_2 83.215 MHz 12.017 987.983
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \SGPIO_Target:falling_sclock\ \SGPIO_Target:falling_sclock\/clock_0 \SGPIO_Target:falling_sclock\/q 1.250
Route 1 \SGPIO_Target:falling_sclock\ \SGPIO_Target:falling_sclock\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_2 3.597
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ SETUP 7.170
Clock Skew 0.000
\SGPIO_Target:falling_sclock\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_2 83.431 MHz 11.986 988.014
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \SGPIO_Target:falling_sclock\ \SGPIO_Target:falling_sclock\/clock_0 \SGPIO_Target:falling_sclock\/q 1.250
Route 1 \SGPIO_Target:falling_sclock\ \SGPIO_Target:falling_sclock\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_2 3.566
datapathcell1 U(1,0) 1 \SGPIO_Target:TargetShiftReg:u0\ SETUP 7.170
Clock Skew 0.000
\SGPIO_Target:TargetShiftReg:u1\/ce1_comb \SGPIO_Target:TargetBitCounter\/load 83.829 MHz 11.929 988.071
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ \SGPIO_Target:TargetShiftReg:u1\/clock \SGPIO_Target:TargetShiftReg:u1\/ce1_comb 5.030
Route 1 \SGPIO_Target:sync_dp\ \SGPIO_Target:TargetShiftReg:u1\/ce1_comb \SGPIO_Target:TargetBitCounter\/load 2.679
count7cell U(0,0) 1 \SGPIO_Target:TargetBitCounter\ SETUP 4.220
Clock Skew 0.000
\SGPIO_Target:TargetShiftReg:u1\/ce1_comb \SGPIO_Target:status_0\/main_1 89.087 MHz 11.225 988.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ \SGPIO_Target:TargetShiftReg:u1\/clock \SGPIO_Target:TargetShiftReg:u1\/ce1_comb 5.030
Route 1 \SGPIO_Target:sync_dp\ \SGPIO_Target:TargetShiftReg:u1\/ce1_comb \SGPIO_Target:status_0\/main_1 2.685
macrocell18 U(0,0) 1 \SGPIO_Target:status_0\ SETUP 3.510
Clock Skew 0.000
\SGPIO_Target:TargetShiftReg:u1\/ce1_comb \SGPIO_Target:sync_sm_1\/main_1 89.087 MHz 11.225 988.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ \SGPIO_Target:TargetShiftReg:u1\/clock \SGPIO_Target:TargetShiftReg:u1\/ce1_comb 5.030
Route 1 \SGPIO_Target:sync_dp\ \SGPIO_Target:TargetShiftReg:u1\/ce1_comb \SGPIO_Target:sync_sm_1\/main_1 2.685
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ SETUP 3.510
Clock Skew 0.000
\SGPIO_Target:rising_sclock\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_1 91.166 MHz 10.969 989.031
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \SGPIO_Target:rising_sclock\ \SGPIO_Target:rising_sclock\/clock_0 \SGPIO_Target:rising_sclock\/q 1.250
Route 1 \SGPIO_Target:rising_sclock\ \SGPIO_Target:rising_sclock\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_1 2.549
datapathcell1 U(1,0) 1 \SGPIO_Target:TargetShiftReg:u0\ SETUP 7.170
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
SCLOCK(0)/fb Net_719/main_0 73.697 MHz 13.569 28.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 4.047
Route 1 Net_706 SCLOCK(0)/fb Net_719/main_0 6.012
macrocell6 U(1,0) 1 Net_719 SETUP 3.510
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:falling_sclock\/main_0 73.697 MHz 13.569 28.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 4.047
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:falling_sclock\/main_0 6.012
macrocell13 U(1,0) 1 \SGPIO_Target:falling_sclock\ SETUP 3.510
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:rising_sclock\/main_0 73.697 MHz 13.569 28.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 4.047
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:rising_sclock\/main_0 6.012
macrocell14 U(1,0) 1 \SGPIO_Target:rising_sclock\ SETUP 3.510
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:f1_load\/main_0 75.324 MHz 13.276 28.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 4.047
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:f1_load\/main_0 5.719
macrocell12 U(0,0) 1 \SGPIO_Target:f1_load\ SETUP 3.510
Clock Skew 0.000
SDOUT(0)/fb \SGPIO_Target:route_si\/main_0 76.441 MHz 13.082 28.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[5] 1 SDOUT(0) SDOUT(0)/in_clock SDOUT(0)/fb 4.047
Route 1 Net_708 SDOUT(0)/fb \SGPIO_Target:route_si\/main_0 5.525
macrocell15 U(1,0) 1 \SGPIO_Target:route_si\ SETUP 3.510
Clock Skew 0.000
SLOAD(0)/fb \SGPIO_Target:status_1\/main_1 76.752 MHz 13.029 28.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[7] 1 SLOAD(0) SLOAD(0)/in_clock SLOAD(0)/fb 4.047
Route 1 Net_707 SLOAD(0)/fb \SGPIO_Target:status_1\/main_1 5.472
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ SETUP 3.510
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:sclock_d\/main_0 78.709 MHz 12.705 28.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 4.047
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:sclock_d\/main_0 5.148
macrocell16 U(1,1) 1 \SGPIO_Target:sclock_d\ SETUP 3.510
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:status_1\/main_0 78.709 MHz 12.705 28.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 4.047
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:status_1\/main_0 5.148
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ SETUP 3.510
Clock Skew 0.000
SDOUT(0)/fb \SGPIO_Target:status_1\/main_2 81.873 MHz 12.214 29.453
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[5] 1 SDOUT(0) SDOUT(0)/in_clock SDOUT(0)/fb 4.047
Route 1 Net_708 SDOUT(0)/fb \SGPIO_Target:status_1\/main_2 4.657
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ SETUP 3.510
Clock Skew 0.000
SLOAD(0)/fb \SGPIO_Target:sload_d\/main_0 82.122 MHz 12.177 29.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[7] 1 SLOAD(0) SLOAD(0)/in_clock SLOAD(0)/fb 4.047
Route 1 Net_707 SLOAD(0)/fb \SGPIO_Target:sload_d\/main_0 4.620
macrocell17 U(1,0) 1 \SGPIO_Target:sload_d\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SGPIO_Target:TargetShiftReg:u1\/sor \SGPIO_Target:TargetShiftReg:u0\/sil 1.240
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ \SGPIO_Target:TargetShiftReg:u1\/clock \SGPIO_Target:TargetShiftReg:u1\/sor 1.240
Route 1 \SGPIO_Target:TargetShiftReg:u1.sor__sig\ \SGPIO_Target:TargetShiftReg:u1\/sor \SGPIO_Target:TargetShiftReg:u0\/sil 0.000
datapathcell1 U(1,0) 1 \SGPIO_Target:TargetShiftReg:u0\ HOLD 0.000
Clock Skew 0.000
Net_719/q Net_719/main_1 3.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_719 Net_719/clock_0 Net_719/q 1.250
macrocell6 U(1,0) 1 Net_719 Net_719/q Net_719/main_1 2.234
macrocell6 U(1,0) 1 Net_719 HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:sync_sm_1\/q \SGPIO_Target:status_0\/main_4 3.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/clock_0 \SGPIO_Target:sync_sm_1\/q 1.250
Route 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/q \SGPIO_Target:status_0\/main_4 2.238
macrocell18 U(0,0) 1 \SGPIO_Target:status_0\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:sync_sm_1\/q \SGPIO_Target:sync_sm_1\/main_4 3.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/clock_0 \SGPIO_Target:sync_sm_1\/q 1.250
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ \SGPIO_Target:sync_sm_1\/q \SGPIO_Target:sync_sm_1\/main_4 2.238
macrocell20 U(0,0) 1 \SGPIO_Target:sync_sm_1\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:sload_d\/q \SGPIO_Target:sload_d\/main_2 3.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \SGPIO_Target:sload_d\ \SGPIO_Target:sload_d\/clock_0 \SGPIO_Target:sload_d\/q 1.250
macrocell17 U(1,0) 1 \SGPIO_Target:sload_d\ \SGPIO_Target:sload_d\/q \SGPIO_Target:sload_d\/main_2 2.539
macrocell17 U(1,0) 1 \SGPIO_Target:sload_d\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:route_si\/q \SGPIO_Target:TargetShiftReg:u1\/route_si 3.790
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \SGPIO_Target:route_si\ \SGPIO_Target:route_si\/clock_0 \SGPIO_Target:route_si\/q 1.250
Route 1 \SGPIO_Target:route_si\ \SGPIO_Target:route_si\/q \SGPIO_Target:TargetShiftReg:u1\/route_si 2.540
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:sload_d\/q \SGPIO_Target:route_si\/main_2 3.793
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \SGPIO_Target:sload_d\ \SGPIO_Target:sload_d\/clock_0 \SGPIO_Target:sload_d\/q 1.250
Route 1 \SGPIO_Target:sload_d\ \SGPIO_Target:sload_d\/q \SGPIO_Target:route_si\/main_2 2.543
macrocell15 U(1,0) 1 \SGPIO_Target:route_si\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:rising_sclock\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_1 3.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \SGPIO_Target:rising_sclock\ \SGPIO_Target:rising_sclock\/clock_0 \SGPIO_Target:rising_sclock\/q 1.250
Route 1 \SGPIO_Target:rising_sclock\ \SGPIO_Target:rising_sclock\/q \SGPIO_Target:TargetShiftReg:u1\/cs_addr_1 2.548
datapathcell2 U(0,0) 1 \SGPIO_Target:TargetShiftReg:u1\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:rising_sclock\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_1 3.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \SGPIO_Target:rising_sclock\ \SGPIO_Target:rising_sclock\/clock_0 \SGPIO_Target:rising_sclock\/q 1.250
Route 1 \SGPIO_Target:rising_sclock\ \SGPIO_Target:rising_sclock\/q \SGPIO_Target:TargetShiftReg:u0\/cs_addr_1 2.549
datapathcell1 U(1,0) 1 \SGPIO_Target:TargetShiftReg:u0\ HOLD 0.000
Clock Skew 0.000
\SGPIO_Target:tc_d\/q \SGPIO_Target:tc_d\/main_2 3.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,0) 1 \SGPIO_Target:tc_d\ \SGPIO_Target:tc_d\/clock_0 \SGPIO_Target:tc_d\/q 1.250
macrocell21 U(1,0) 1 \SGPIO_Target:tc_d\ \SGPIO_Target:tc_d\/q \SGPIO_Target:tc_d\/main_2 2.682
macrocell21 U(1,0) 1 \SGPIO_Target:tc_d\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
SLOAD(0)/fb \SGPIO_Target:sload_d\/main_0 7.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[7] 1 SLOAD(0) SLOAD(0)/in_clock SLOAD(0)/fb 2.740
Route 1 Net_707 SLOAD(0)/fb \SGPIO_Target:sload_d\/main_0 4.620
macrocell17 U(1,0) 1 \SGPIO_Target:sload_d\ HOLD 0.000
Clock Skew 0.000
SDOUT(0)/fb \SGPIO_Target:status_1\/main_2 7.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[5] 1 SDOUT(0) SDOUT(0)/in_clock SDOUT(0)/fb 2.740
Route 1 Net_708 SDOUT(0)/fb \SGPIO_Target:status_1\/main_2 4.657
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ HOLD 0.000
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:sclock_d\/main_0 7.888
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 2.740
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:sclock_d\/main_0 5.148
macrocell16 U(1,1) 1 \SGPIO_Target:sclock_d\ HOLD 0.000
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:status_1\/main_0 7.888
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 2.740
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:status_1\/main_0 5.148
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ HOLD 0.000
Clock Skew 0.000
SLOAD(0)/fb \SGPIO_Target:status_1\/main_1 8.212
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[7] 1 SLOAD(0) SLOAD(0)/in_clock SLOAD(0)/fb 2.740
Route 1 Net_707 SLOAD(0)/fb \SGPIO_Target:status_1\/main_1 5.472
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ HOLD 0.000
Clock Skew 0.000
SDOUT(0)/fb \SGPIO_Target:route_si\/main_0 8.265
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P0[5] 1 SDOUT(0) SDOUT(0)/in_clock SDOUT(0)/fb 2.740
Route 1 Net_708 SDOUT(0)/fb \SGPIO_Target:route_si\/main_0 5.525
macrocell15 U(1,0) 1 \SGPIO_Target:route_si\ HOLD 0.000
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:f1_load\/main_0 8.459
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 2.740
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:f1_load\/main_0 5.719
macrocell12 U(0,0) 1 \SGPIO_Target:f1_load\ HOLD 0.000
Clock Skew 0.000
SCLOCK(0)/fb Net_719/main_0 8.752
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 2.740
Route 1 Net_706 SCLOCK(0)/fb Net_719/main_0 6.012
macrocell6 U(1,0) 1 Net_719 HOLD 0.000
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:falling_sclock\/main_0 8.752
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 2.740
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:falling_sclock\/main_0 6.012
macrocell13 U(1,0) 1 \SGPIO_Target:falling_sclock\ HOLD 0.000
Clock Skew 0.000
SCLOCK(0)/fb \SGPIO_Target:rising_sclock\/main_0 8.752
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell6 P0[7] 1 SCLOCK(0) SCLOCK(0)/in_clock SCLOCK(0)/fb 2.740
Route 1 Net_706 SCLOCK(0)/fb \SGPIO_Target:rising_sclock\/main_0 6.012
macrocell14 U(1,0) 1 \SGPIO_Target:rising_sclock\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1(FFB)
Source Destination Delay (ns)
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out ACTIVITY_LED_3(0)_PAD 34.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_691/main_0 6.636
macrocell3 U(0,1) 1 Net_691 Net_691/main_0 Net_691/q 3.350
Route 1 Net_691 Net_691/q ACTIVITY_LED_3(0)/pin_input 5.883
iocell3 P2[5] 1 ACTIVITY_LED_3(0) ACTIVITY_LED_3(0)/pin_input ACTIVITY_LED_3(0)/pad_out 18.610
Route 1 ACTIVITY_LED_3(0)_PAD ACTIVITY_LED_3(0)/pad_out ACTIVITY_LED_3(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_3(0)_PAD 34.313
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_749/main_1 6.626
macrocell9 U(1,1) 1 Net_749 Net_749/main_1 Net_749/q 3.350
Route 1 Net_749 Net_749/q STATUS_LED_3(0)/pin_input 5.917
iocell16 P2[7] 1 STATUS_LED_3(0) STATUS_LED_3(0)/pin_input STATUS_LED_3(0)/pad_out 18.420
Route 1 STATUS_LED_3(0)_PAD STATUS_LED_3(0)/pad_out STATUS_LED_3(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_4(0)_PAD 34.229
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_750/main_1 6.477
macrocell10 U(1,1) 1 Net_750 Net_750/main_1 Net_750/q 3.350
Route 1 Net_750 Net_750/q STATUS_LED_4(0)/pin_input 5.892
iocell17 P2[6] 1 STATUS_LED_4(0) STATUS_LED_4(0)/pin_input STATUS_LED_4(0)/pad_out 18.510
Route 1 STATUS_LED_4(0)_PAD STATUS_LED_4(0)/pad_out STATUS_LED_4(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out ACTIVITY_LED_4(0)_PAD 33.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_692/main_1 6.636
macrocell4 U(0,1) 1 Net_692 Net_692/main_1 Net_692/q 3.350
Route 1 Net_692 Net_692/q ACTIVITY_LED_4(0)/pin_input 5.543
iocell4 P2[4] 1 ACTIVITY_LED_4(0) ACTIVITY_LED_4(0)/pin_input ACTIVITY_LED_4(0)/pad_out 18.370
Route 1 ACTIVITY_LED_4(0)_PAD ACTIVITY_LED_4(0)/pad_out ACTIVITY_LED_4(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out ACTIVITY_LED_1(0)_PAD 31.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_656/main_0 6.626
macrocell1 U(1,1) 1 Net_656 Net_656/main_0 Net_656/q 3.350
Route 1 Net_656 Net_656/q ACTIVITY_LED_1(0)/pin_input 5.910
iocell1 P0[1] 1 ACTIVITY_LED_1(0) ACTIVITY_LED_1(0)/pin_input ACTIVITY_LED_1(0)/pad_out 15.980
Route 1 ACTIVITY_LED_1(0)_PAD ACTIVITY_LED_1(0)/pad_out ACTIVITY_LED_1(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out ACTIVITY_LED_2(0)_PAD 31.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_690/main_0 6.626
macrocell2 U(1,1) 1 Net_690 Net_690/main_0 Net_690/q 3.350
Route 1 Net_690 Net_690/q ACTIVITY_LED_2(0)/pin_input 5.910
iocell2 P0[0] 1 ACTIVITY_LED_2(0) ACTIVITY_LED_2(0)/pin_input ACTIVITY_LED_2(0)/pad_out 15.530
Route 1 ACTIVITY_LED_2(0)_PAD ACTIVITY_LED_2(0)/pad_out ACTIVITY_LED_2(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_2(0)_PAD 31.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_748/main_1 6.477
macrocell8 U(1,1) 1 Net_748 Net_748/main_1 Net_748/q 3.350
Route 1 Net_748 Net_748/q STATUS_LED_2(0)/pin_input 6.194
iocell15 P1[0] 1 STATUS_LED_2(0) STATUS_LED_2(0)/pin_input STATUS_LED_2(0)/pad_out 15.120
Route 1 STATUS_LED_2(0)_PAD STATUS_LED_2(0)/pad_out STATUS_LED_2(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_4Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_1(0)_PAD 30.948
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_4Hz:cy_m0s8_tcpwm_1\ \PWM_4Hz:cy_m0s8_tcpwm_1\/clock \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 PWM_4H \PWM_4Hz:cy_m0s8_tcpwm_1\/line_out Net_747/main_1 6.626
macrocell7 U(1,1) 1 Net_747 Net_747/main_1 Net_747/q 3.350
Route 1 Net_747 Net_747/q STATUS_LED_1(0)/pin_input 5.762
iocell14 P3[5] 1 STATUS_LED_1(0) STATUS_LED_1(0)/pin_input STATUS_LED_1(0)/pad_out 15.210
Route 1 STATUS_LED_1(0)_PAD STATUS_LED_1(0)/pad_out STATUS_LED_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_2
Source Destination Delay (ns)
Net_719/q SDIN(0)_PAD 23.811
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_719 Net_719/clock_0 Net_719/q 1.250
Route 1 Net_719 Net_719/q SDIN(0)/pin_input 5.971
iocell7 P0[4] 1 SDIN(0) SDIN(0)/pin_input SDIN(0)/pad_out 16.590
Route 1 SDIN(0)_PAD SDIN(0)/pad_out SDIN(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_4(FFB)
Source Destination Delay (ns)
\PWM_1Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_4(0)_PAD 36.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1Hz:cy_m0s8_tcpwm_1\ \PWM_1Hz:cy_m0s8_tcpwm_1\/clock \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_883 \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out Net_750/main_0 8.293
macrocell10 U(1,1) 1 Net_750 Net_750/main_0 Net_750/q 3.350
Route 1 Net_750 Net_750/q STATUS_LED_4(0)/pin_input 5.892
iocell17 P2[6] 1 STATUS_LED_4(0) STATUS_LED_4(0)/pin_input STATUS_LED_4(0)/pad_out 18.510
Route 1 STATUS_LED_4(0)_PAD STATUS_LED_4(0)/pad_out STATUS_LED_4(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_1Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_3(0)_PAD 35.400
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1Hz:cy_m0s8_tcpwm_1\ \PWM_1Hz:cy_m0s8_tcpwm_1\/clock \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_883 \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out Net_749/main_0 7.713
macrocell9 U(1,1) 1 Net_749 Net_749/main_0 Net_749/q 3.350
Route 1 Net_749 Net_749/q STATUS_LED_3(0)/pin_input 5.917
iocell16 P2[7] 1 STATUS_LED_3(0) STATUS_LED_3(0)/pin_input STATUS_LED_3(0)/pad_out 18.420
Route 1 STATUS_LED_3(0)_PAD STATUS_LED_3(0)/pad_out STATUS_LED_3(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_1Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_2(0)_PAD 32.957
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1Hz:cy_m0s8_tcpwm_1\ \PWM_1Hz:cy_m0s8_tcpwm_1\/clock \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_883 \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out Net_748/main_0 8.293
macrocell8 U(1,1) 1 Net_748 Net_748/main_0 Net_748/q 3.350
Route 1 Net_748 Net_748/q STATUS_LED_2(0)/pin_input 6.194
iocell15 P1[0] 1 STATUS_LED_2(0) STATUS_LED_2(0)/pin_input STATUS_LED_2(0)/pad_out 15.120
Route 1 STATUS_LED_2(0)_PAD STATUS_LED_2(0)/pad_out STATUS_LED_2(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_1Hz:cy_m0s8_tcpwm_1\/line_out STATUS_LED_1(0)_PAD 32.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1Hz:cy_m0s8_tcpwm_1\ \PWM_1Hz:cy_m0s8_tcpwm_1\/clock \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_883 \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out Net_747/main_0 7.713
macrocell7 U(1,1) 1 Net_747 Net_747/main_0 Net_747/q 3.350
Route 1 Net_747 Net_747/q STATUS_LED_1(0)/pin_input 5.762
iocell14 P3[5] 1 STATUS_LED_1(0) STATUS_LED_1(0)/pin_input STATUS_LED_1(0)/pad_out 15.210
Route 1 STATUS_LED_1(0)_PAD STATUS_LED_1(0)/pad_out STATUS_LED_1(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_1Hz:cy_m0s8_tcpwm_1\/line_out Pin_1(0)_PAD 17.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1Hz:cy_m0s8_tcpwm_1\ \PWM_1Hz:cy_m0s8_tcpwm_1\/clock \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_883 \PWM_1Hz:cy_m0s8_tcpwm_1\/line_out Pin_1(0)/pin_input 3.424
iocell5 P3[6] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 14.220
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyHFCLK
Source Destination Delay (ns)
\SGPIOActivityReg:Sync:ctrl_reg\/control_2 ACTIVITY_LED_3(0)_PAD 33.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \SGPIOActivityReg:Sync:ctrl_reg\ \SGPIOActivityReg:Sync:ctrl_reg\/busclk \SGPIOActivityReg:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_223 \SGPIOActivityReg:Sync:ctrl_reg\/control_2 Net_691/main_1 2.829
macrocell3 U(0,1) 1 Net_691 Net_691/main_1 Net_691/q 3.350
Route 1 Net_691 Net_691/q ACTIVITY_LED_3(0)/pin_input 5.883
iocell3 P2[5] 1 ACTIVITY_LED_3(0) ACTIVITY_LED_3(0)/pin_input ACTIVITY_LED_3(0)/pad_out 18.610
Route 1 ACTIVITY_LED_3(0)_PAD ACTIVITY_LED_3(0)/pad_out ACTIVITY_LED_3(0)_PAD 0.000
Clock Clock path delay 0.000
\SGPIOActivityReg:Sync:ctrl_reg\/control_3 ACTIVITY_LED_4(0)_PAD 32.668
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \SGPIOActivityReg:Sync:ctrl_reg\ \SGPIOActivityReg:Sync:ctrl_reg\/busclk \SGPIOActivityReg:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_157 \SGPIOActivityReg:Sync:ctrl_reg\/control_3 Net_692/main_0 2.825
macrocell4 U(0,1) 1 Net_692 Net_692/main_0 Net_692/q 3.350
Route 1 Net_692 Net_692/q ACTIVITY_LED_4(0)/pin_input 5.543
iocell4 P2[4] 1 ACTIVITY_LED_4(0) ACTIVITY_LED_4(0)/pin_input ACTIVITY_LED_4(0)/pad_out 18.370
Route 1 ACTIVITY_LED_4(0)_PAD ACTIVITY_LED_4(0)/pad_out ACTIVITY_LED_4(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusControlReg:Sync:ctrl_reg\/control_6 STATUS_LED_4(0)_PAD 32.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,1) 1 \StatusControlReg:Sync:ctrl_reg\ \StatusControlReg:Sync:ctrl_reg\/busclk \StatusControlReg:Sync:ctrl_reg\/control_6 2.580
Route 1 control_6 \StatusControlReg:Sync:ctrl_reg\/control_6 Net_750/main_3 2.314
macrocell10 U(1,1) 1 Net_750 Net_750/main_3 Net_750/q 3.350
Route 1 Net_750 Net_750/q STATUS_LED_4(0)/pin_input 5.892
iocell17 P2[6] 1 STATUS_LED_4(0) STATUS_LED_4(0)/pin_input STATUS_LED_4(0)/pad_out 18.510
Route 1 STATUS_LED_4(0)_PAD STATUS_LED_4(0)/pad_out STATUS_LED_4(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusControlReg:Sync:ctrl_reg\/control_4 STATUS_LED_3(0)_PAD 32.581
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,1) 1 \StatusControlReg:Sync:ctrl_reg\ \StatusControlReg:Sync:ctrl_reg\/busclk \StatusControlReg:Sync:ctrl_reg\/control_4 2.580
Route 1 control_4 \StatusControlReg:Sync:ctrl_reg\/control_4 Net_749/main_3 2.314
macrocell9 U(1,1) 1 Net_749 Net_749/main_3 Net_749/q 3.350
Route 1 Net_749 Net_749/q STATUS_LED_3(0)/pin_input 5.917
iocell16 P2[7] 1 STATUS_LED_3(0) STATUS_LED_3(0)/pin_input STATUS_LED_3(0)/pad_out 18.420
Route 1 STATUS_LED_3(0)_PAD STATUS_LED_3(0)/pad_out STATUS_LED_3(0)_PAD 0.000
Clock Clock path delay 0.000
\SGPIOActivityReg:Sync:ctrl_reg\/control_0 ACTIVITY_LED_1(0)_PAD 30.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \SGPIOActivityReg:Sync:ctrl_reg\ \SGPIOActivityReg:Sync:ctrl_reg\/busclk \SGPIOActivityReg:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_228 \SGPIOActivityReg:Sync:ctrl_reg\/control_0 Net_656/main_1 2.846
macrocell1 U(1,1) 1 Net_656 Net_656/main_1 Net_656/q 3.350
Route 1 Net_656 Net_656/q ACTIVITY_LED_1(0)/pin_input 5.910
iocell1 P0[1] 1 ACTIVITY_LED_1(0) ACTIVITY_LED_1(0)/pin_input ACTIVITY_LED_1(0)/pad_out 15.980
Route 1 ACTIVITY_LED_1(0)_PAD ACTIVITY_LED_1(0)/pad_out ACTIVITY_LED_1(0)_PAD 0.000
Clock Clock path delay 0.000
\SGPIOActivityReg:Sync:ctrl_reg\/control_1 ACTIVITY_LED_2(0)_PAD 30.201
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \SGPIOActivityReg:Sync:ctrl_reg\ \SGPIOActivityReg:Sync:ctrl_reg\/busclk \SGPIOActivityReg:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_224 \SGPIOActivityReg:Sync:ctrl_reg\/control_1 Net_690/main_1 2.831
macrocell2 U(1,1) 1 Net_690 Net_690/main_1 Net_690/q 3.350
Route 1 Net_690 Net_690/q ACTIVITY_LED_2(0)/pin_input 5.910
iocell2 P0[0] 1 ACTIVITY_LED_2(0) ACTIVITY_LED_2(0)/pin_input ACTIVITY_LED_2(0)/pad_out 15.530
Route 1 ACTIVITY_LED_2(0)_PAD ACTIVITY_LED_2(0)/pad_out ACTIVITY_LED_2(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusControlReg:Sync:ctrl_reg\/control_2 STATUS_LED_2(0)_PAD 29.560
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,1) 1 \StatusControlReg:Sync:ctrl_reg\ \StatusControlReg:Sync:ctrl_reg\/busclk \StatusControlReg:Sync:ctrl_reg\/control_2 2.580
Route 1 control_2 \StatusControlReg:Sync:ctrl_reg\/control_2 Net_748/main_3 2.316
macrocell8 U(1,1) 1 Net_748 Net_748/main_3 Net_748/q 3.350
Route 1 Net_748 Net_748/q STATUS_LED_2(0)/pin_input 6.194
iocell15 P1[0] 1 STATUS_LED_2(0) STATUS_LED_2(0)/pin_input STATUS_LED_2(0)/pad_out 15.120
Route 1 STATUS_LED_2(0)_PAD STATUS_LED_2(0)/pad_out STATUS_LED_2(0)_PAD 0.000
Clock Clock path delay 0.000
\StatusControlReg:Sync:ctrl_reg\/control_0 STATUS_LED_1(0)_PAD 29.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,1) 1 \StatusControlReg:Sync:ctrl_reg\ \StatusControlReg:Sync:ctrl_reg\/busclk \StatusControlReg:Sync:ctrl_reg\/control_0 2.580
Route 1 control_0 \StatusControlReg:Sync:ctrl_reg\/control_0 Net_747/main_3 2.305
macrocell7 U(1,1) 1 Net_747 Net_747/main_3 Net_747/q 3.350
Route 1 Net_747 Net_747/q STATUS_LED_1(0)/pin_input 5.762
iocell14 P3[5] 1 STATUS_LED_1(0) STATUS_LED_1(0)/pin_input STATUS_LED_1(0)/pad_out 15.210
Route 1 STATUS_LED_1(0)_PAD STATUS_LED_1(0)/pad_out STATUS_LED_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SGPIO_Target:SyncCtlTCR:TargetControlReg\/control_1 \SGPIO_Target:status_1\/ap_0 204.708 MHz 4.885 995.115
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \SGPIO_Target:SyncCtlTCR:TargetControlReg\ \SGPIO_Target:SyncCtlTCR:TargetControlReg\/clock \SGPIO_Target:SyncCtlTCR:TargetControlReg\/control_1 2.580
Route 1 \SGPIO_Target:control_1\ \SGPIO_Target:SyncCtlTCR:TargetControlReg\/control_1 \SGPIO_Target:status_1\/ap_0 2.305
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\SGPIO_Target:SyncCtlTCR:TargetControlReg\/control_1 \SGPIO_Target:status_1\/ap_0 4.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \SGPIO_Target:SyncCtlTCR:TargetControlReg\ \SGPIO_Target:SyncCtlTCR:TargetControlReg\/clock \SGPIO_Target:SyncCtlTCR:TargetControlReg\/control_1 2.040
Route 1 \SGPIO_Target:control_1\ \SGPIO_Target:SyncCtlTCR:TargetControlReg\/control_1 \SGPIO_Target:status_1\/ap_0 2.305
macrocell19 U(1,1) 1 \SGPIO_Target:status_1\ REMOVAL 0.000
Clock Skew 0.000