Static Timing Analysis

Project : EVCharger
Build Time : 03/03/21 09:23:44
Device : CY8C4247AZI-L485
Temperature : -40C - 85C
VBUS : 5.00
VDDA_0 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDIO_0 : 3.30
VDDIO_2 : 3.30
VDDIO_3 : 3.30
VDDIO_4 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
Violation Source Clock Destination Clock Slack(ns)
Hold
CyHFClk \Counter_1:CounterUDB:overflow_reg_i\/q -6.430
CyHFClk \Counter_2:CounterUDB:overflow_reg_i\/q -8.070
\Relays_1:Sync:ctrl_reg\/control_1 \Relays_1:Sync:ctrl_reg\/control_1 -6.238
Async
Clock_1(FFB) Clock_1
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_Seq_1_intClock(FFB) ADC_SAR_Seq_1_intClock(FFB) 1.655 MHz 1.655 MHz N/A
Clock_1(FFB) Clock_1(FFB) 24.000 MHz 24.000 MHz N/A
CyHFClk CyHFClk 48.000 MHz 48.000 MHz -231000231.000  Hz Frequency
Clock_1 CyHFClk 24.000 MHz 24.000 MHz 55.723 MHz
ADC_SAR_Seq_1_intClock CyHFClk 1.655 MHz 1.655 MHz N/A
UART_SCBCLK CyHFClk 1.371 MHz 1.371 MHz N/A
Clock_3 CyHFClk 23.438 kHz 23.438 kHz 39.852 MHz
\Relays_1:Sync:ctrl_reg\/control_1 CyHFClk UNKNOWN UNKNOWN N/A
\Counter_2:CounterUDB:overflow_reg_i\/q CyHFClk UNKNOWN UNKNOWN N/A
\Counter_1:CounterUDB:overflow_reg_i\/q CyHFClk UNKNOWN UNKNOWN N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFClk CyLFClk 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySysClk CySysClk 48.000 MHz 48.000 MHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 1.371 MHz 1.371 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 55.723 MHz 17.946 23.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.576
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:db_cnt_0\/main_5 57.372 MHz 17.430 24.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:db_cnt_0_split\/main_8 2.601
macrocell29 U(1,3) 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/main_8 \PWM:PWMUDB:db_cnt_0_split\/q 3.350
Route 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/q \PWM:PWMUDB:db_cnt_0\/main_5 2.289
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM:PWMUDB:db_cnt_0\/main_5 59.478 MHz 16.813 24.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/ce0_comb 5.060
Route 1 \PWM:PWMUDB:cmp1_eq\ \PWM:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM:PWMUDB:db_cnt_0_split\/main_7 2.604
macrocell29 U(1,3) 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/main_7 \PWM:PWMUDB:db_cnt_0_split\/q 3.350
Route 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/q \PWM:PWMUDB:db_cnt_0\/main_5 2.289
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 61.106 MHz 16.365 25.302
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.595
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM:PWMUDB:pwm_db_reg\/q \PWM:PWMUDB:db_cnt_0\/main_5 62.504 MHz 15.999 25.668
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \PWM:PWMUDB:pwm_db_reg\ \PWM:PWMUDB:pwm_db_reg\/clock_0 \PWM:PWMUDB:pwm_db_reg\/q 1.250
Route 1 \PWM:PWMUDB:pwm_db_reg\ \PWM:PWMUDB:pwm_db_reg\/q \PWM:PWMUDB:db_cnt_0_split\/main_1 5.600
macrocell29 U(1,3) 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/main_1 \PWM:PWMUDB:db_cnt_0_split\/q 3.350
Route 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/q \PWM:PWMUDB:db_cnt_0\/main_5 2.289
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:db_ph2_run_temp\/q \PWM:PWMUDB:db_cnt_0\/main_5 66.547 MHz 15.027 26.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,2) 1 \PWM:PWMUDB:db_ph2_run_temp\ \PWM:PWMUDB:db_ph2_run_temp\/clock_0 \PWM:PWMUDB:db_ph2_run_temp\/q 1.250
Route 1 \PWM:PWMUDB:db_ph2_run_temp\ \PWM:PWMUDB:db_ph2_run_temp\/q \PWM:PWMUDB:db_cnt_0_split\/main_3 4.628
macrocell29 U(1,3) 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/main_3 \PWM:PWMUDB:db_cnt_0_split\/q 3.350
Route 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/q \PWM:PWMUDB:db_cnt_0\/main_5 2.289
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:pwm_db_reg\/main_2 68.060 MHz 14.693 26.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:pwm_db_reg\/main_2 5.503
macrocell17 U(1,0) 1 \PWM:PWMUDB:pwm_db_reg\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:genblk7:dbctrlreg\/control_0 \PWM:PWMUDB:db_cnt_0\/main_5 68.381 MHz 14.624 27.043
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \PWM:PWMUDB:genblk7:dbctrlreg\ \PWM:PWMUDB:genblk7:dbctrlreg\/clock \PWM:PWMUDB:genblk7:dbctrlreg\/control_0 2.580
Route 1 \PWM:PWMUDB:dbcontrol_0\ \PWM:PWMUDB:genblk7:dbctrlreg\/control_0 \PWM:PWMUDB:db_cnt_0_split\/main_4 2.895
macrocell29 U(1,3) 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/main_4 \PWM:PWMUDB:db_cnt_0_split\/q 3.350
Route 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/q \PWM:PWMUDB:db_cnt_0\/main_5 2.289
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:db_cnt_1\/q \PWM:PWMUDB:db_cnt_0\/main_5 69.449 MHz 14.399 27.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,2) 1 \PWM:PWMUDB:db_cnt_1\ \PWM:PWMUDB:db_cnt_1\/clock_0 \PWM:PWMUDB:db_cnt_1\/q 1.250
Route 1 \PWM:PWMUDB:db_cnt_1\ \PWM:PWMUDB:db_cnt_1\/q \PWM:PWMUDB:db_cnt_0_split\/main_5 4.000
macrocell29 U(1,3) 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/main_5 \PWM:PWMUDB:db_cnt_0_split\/q 3.350
Route 1 \PWM:PWMUDB:db_cnt_0_split\ \PWM:PWMUDB:db_cnt_0_split\/q \PWM:PWMUDB:db_cnt_0\/main_5 2.289
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM:PWMUDB:pwm_db_reg\/main_1 71.023 MHz 14.080 27.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/ce0_comb 5.060
Route 1 \PWM:PWMUDB:cmp1_eq\ \PWM:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM:PWMUDB:pwm_db_reg\/main_1 5.510
macrocell17 U(1,0) 1 \PWM:PWMUDB:pwm_db_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 42666.7ns(23.4375 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Sync_2:genblk1[0]:INST\/out \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_0 39.852 MHz 25.093 42641.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.480
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out Net_2263/main_0 4.181
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_0 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_0 4.552
datapathcell3 U(0,1) 1 \Counter_1:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\EdgeDetect_2:last\/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_0 42.196 MHz 23.699 42642.968
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/clock_0 \EdgeDetect_2:last\/q 1.250
Route 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/q Net_2263/main_1 3.017
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_1 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_0 4.552
datapathcell3 U(0,1) 1 \Counter_1:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_0 43.016 MHz 23.247 42643.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.480
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out Net_2263/main_0 4.181
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_0 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.706
datapathcell2 U(0,0) 1 \Counter_2:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_1 43.018 MHz 23.246 42643.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(0,1) 1 \Counter_1:CounterUDB:sCTRLReg:ctrlreg\ \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_7 2.580
Route 1 \Counter_1:CounterUDB:control_7\ \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_1:CounterUDB:count_enable\/main_1 2.918
macrocell9 U(0,0) 1 \Counter_1:CounterUDB:count_enable\ \Counter_1:CounterUDB:count_enable\/main_1 \Counter_1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_1:CounterUDB:count_enable\ \Counter_1:CounterUDB:count_enable\/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.868
datapathcell3 U(0,1) 1 \Counter_1:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Counter_1:CounterUDB:disable_run_i\/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_1 45.098 MHz 22.174 42644.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ \Counter_1:CounterUDB:disable_run_i\/clock_0 \Counter_1:CounterUDB:disable_run_i\/q 1.250
Route 1 \Counter_1:CounterUDB:disable_run_i\ \Counter_1:CounterUDB:disable_run_i\/q \Counter_1:CounterUDB:count_enable\/main_2 3.176
macrocell9 U(0,0) 1 \Counter_1:CounterUDB:count_enable\ \Counter_1:CounterUDB:count_enable\/main_2 \Counter_1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_1:CounterUDB:count_enable\ \Counter_1:CounterUDB:count_enable\/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.868
datapathcell3 U(0,1) 1 \Counter_1:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_1 45.504 MHz 21.976 42644.691
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,0) 1 \Counter_2:CounterUDB:sCTRLReg:ctrlreg\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_7 2.580
Route 1 \Counter_2:CounterUDB:control_7\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_2:CounterUDB:count_enable\/main_0 2.266
macrocell5 U(0,0) 1 \Counter_2:CounterUDB:count_enable\ \Counter_2:CounterUDB:count_enable\/main_0 \Counter_2:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_2:CounterUDB:count_enable\ \Counter_2:CounterUDB:count_enable\/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.250
datapathcell2 U(0,0) 1 \Counter_2:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\EdgeDetect_2:last\/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_0 45.760 MHz 21.853 42644.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/clock_0 \EdgeDetect_2:last\/q 1.250
Route 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/q Net_2263/main_1 3.017
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_1 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.706
datapathcell2 U(0,0) 1 \Counter_2:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Counter_2:CounterUDB:disable_run_i\/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_1 45.983 MHz 21.747 42644.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ \Counter_2:CounterUDB:disable_run_i\/clock_0 \Counter_2:CounterUDB:disable_run_i\/q 1.250
Route 1 \Counter_2:CounterUDB:disable_run_i\ \Counter_2:CounterUDB:disable_run_i\/q \Counter_2:CounterUDB:count_enable\/main_1 3.367
macrocell5 U(0,0) 1 \Counter_2:CounterUDB:count_enable\ \Counter_2:CounterUDB:count_enable\/main_1 \Counter_2:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_2:CounterUDB:count_enable\ \Counter_2:CounterUDB:count_enable\/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.250
datapathcell2 U(0,0) 1 \Counter_2:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Counter_2:CounterUDB:count_stored_i\/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_1 46.106 MHz 21.689 42644.978
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(0,0) 1 \Counter_2:CounterUDB:count_stored_i\ \Counter_2:CounterUDB:count_stored_i\/clock_0 \Counter_2:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_2:CounterUDB:count_stored_i\ \Counter_2:CounterUDB:count_stored_i\/q \Counter_1:CounterUDB:count_enable\/main_0 2.691
macrocell9 U(0,0) 1 \Counter_1:CounterUDB:count_enable\ \Counter_1:CounterUDB:count_enable\/main_0 \Counter_1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_1:CounterUDB:count_enable\ \Counter_1:CounterUDB:count_enable\/q \Counter_1:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.868
datapathcell3 U(0,1) 1 \Counter_1:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
\Counter_2:CounterUDB:count_stored_i\/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_1 47.472 MHz 21.065 42645.602
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(0,0) 1 \Counter_2:CounterUDB:count_stored_i\ \Counter_2:CounterUDB:count_stored_i\/clock_0 \Counter_2:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_2:CounterUDB:count_stored_i\ \Counter_2:CounterUDB:count_stored_i\/q \Counter_2:CounterUDB:count_enable\/main_2 2.685
macrocell5 U(0,0) 1 \Counter_2:CounterUDB:count_enable\ \Counter_2:CounterUDB:count_enable\/main_2 \Counter_2:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_2:CounterUDB:count_enable\ \Counter_2:CounterUDB:count_enable\/q \Counter_2:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.250
datapathcell2 U(0,0) 1 \Counter_2:CounterUDB:sC8:counterdp:u0\ SETUP 11.530
Clock Skew 0.000
Path Delay Requirement : 20.8333ns
Affects clock : CyHFClk
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 -2.380 23.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ \Relays_1:Sync:ctrl_reg\/busclk \Relays_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_2986 \Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 2.896
macrocell33 U(0,3) 1 Net_3011 SETUP 3.510
Clock Skew -11.366
Path Delay Requirement : 20.8333ns
Affects clock : CyHFClk
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 -4.020 24.853
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ \Relays_1:Sync:ctrl_reg\/busclk \Relays_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_2986 \Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 2.896
macrocell33 U(0,3) 1 Net_3011 SETUP 3.510
Clock Skew -13.006
Path Delay Requirement : 42666.7ns
Affects clock : Clock_3
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 101.358 MHz 9.866 42655.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:overflow_status\/main_1 2.618
macrocell8 U(0,1) 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/main_1 \Counter_1:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 2.328
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 163.239 MHz 6.126 42659.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 2.616
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 42666.7ns
Affects clock : Clock_3
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 101.358 MHz 9.866 42655.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:overflow_status\/main_1 2.618
macrocell8 U(0,1) 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/main_1 \Counter_1:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 2.328
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 163.239 MHz 6.126 42659.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 2.616
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 42666.7ns
Affects clock : Clock_3
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 75.228 MHz 13.293 42652.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:overflow_status\/main_1 4.757
macrocell4 U(0,2) 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/main_1 \Counter_2:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 3.616
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 172.236 MHz 5.806 42659.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 2.296
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 42666.7ns
Affects clock : Clock_3
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 75.228 MHz 13.293 42652.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:overflow_status\/main_1 4.757
macrocell4 U(0,2) 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/main_1 \Counter_2:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 3.616
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 172.236 MHz 5.806 42659.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 2.296
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 20.8333ns
Affects clock : CyHFClk
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -4.329 22.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 SETUP 3.510
Clock Skew -10.453
Path Delay Requirement : 20.8333ns
Affects clock : CyHFClk
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -6.129 24.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 SETUP 3.510
Clock Skew -12.253
Path Delay Requirement : 41.6667ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -4.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 SETUP 3.510
Clock Skew -10.352
Path Delay Requirement : 20.8333ns
Affects clock : CyHFClk
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -4.329 22.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 SETUP 3.510
Clock Skew -10.453
Path Delay Requirement : 20.8333ns
Affects clock : CyHFClk
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -6.129 24.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 SETUP 3.510
Clock Skew -12.253
Path Delay Requirement : 20.8333ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -4.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 SETUP 3.510
Clock Skew -10.352
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM:PWMUDB:status_0\/q \PWM:PWMUDB:genblk8:stsreg\/status_0 2.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,1) 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/clock_0 \PWM:PWMUDB:status_0\/q 1.250
Route 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/q \PWM:PWMUDB:genblk8:stsreg\/status_0 3.684
statusicell1 U(1,3) 1 \PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(1,1) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 2.308
macrocell25 U(1,1) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
AMuxHw_1_Decoder_old_id_0/q AMuxHw_1_Decoder_one_hot_0/main_1 3.568
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,2) 1 AMuxHw_1_Decoder_old_id_0 AMuxHw_1_Decoder_old_id_0/clock_0 AMuxHw_1_Decoder_old_id_0/q 1.250
Route 1 AMuxHw_1_Decoder_old_id_0 AMuxHw_1_Decoder_old_id_0/q AMuxHw_1_Decoder_one_hot_0/main_1 2.318
macrocell14 U(1,2) 1 AMuxHw_1_Decoder_one_hot_0 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:db_ph2_run_temp\/q \PWM:PWMUDB:db_ph2_run_temp\/main_2 4.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,2) 1 \PWM:PWMUDB:db_ph2_run_temp\ \PWM:PWMUDB:db_ph2_run_temp\/clock_0 \PWM:PWMUDB:db_ph2_run_temp\/q 1.250
macrocell21 U(1,2) 1 \PWM:PWMUDB:db_ph2_run_temp\ \PWM:PWMUDB:db_ph2_run_temp\/q \PWM:PWMUDB:db_ph2_run_temp\/main_2 2.785
macrocell21 U(1,2) 1 \PWM:PWMUDB:db_ph2_run_temp\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:db_cnt_0\/q \PWM:PWMUDB:db_ph1_run_temp\/main_4 4.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,3) 1 \PWM:PWMUDB:db_cnt_0\ \PWM:PWMUDB:db_cnt_0\/clock_0 \PWM:PWMUDB:db_cnt_0\/q 1.250
Route 1 \PWM:PWMUDB:db_cnt_0\ \PWM:PWMUDB:db_cnt_0\/q \PWM:PWMUDB:db_ph1_run_temp\/main_4 2.789
macrocell20 U(1,3) 1 \PWM:PWMUDB:db_ph1_run_temp\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:db_ph2_run_temp\/q \PWM:PWMUDB:db_cnt_1\/main_3 4.044
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,2) 1 \PWM:PWMUDB:db_ph2_run_temp\ \PWM:PWMUDB:db_ph2_run_temp\/clock_0 \PWM:PWMUDB:db_ph2_run_temp\/q 1.250
Route 1 \PWM:PWMUDB:db_ph2_run_temp\ \PWM:PWMUDB:db_ph2_run_temp\/q \PWM:PWMUDB:db_cnt_1\/main_3 2.794
macrocell22 U(1,2) 1 \PWM:PWMUDB:db_cnt_1\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:pwm_db_reg\/q Net_2216/main_1 4.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \PWM:PWMUDB:pwm_db_reg\ \PWM:PWMUDB:pwm_db_reg\/clock_0 \PWM:PWMUDB:pwm_db_reg\/q 1.250
Route 1 \PWM:PWMUDB:pwm_db_reg\ \PWM:PWMUDB:pwm_db_reg\/q Net_2216/main_1 2.850
macrocell19 U(1,1) 1 Net_2216 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:db_cnt_1\/q \PWM:PWMUDB:db_ph2_run_temp\/main_3 4.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,2) 1 \PWM:PWMUDB:db_cnt_1\ \PWM:PWMUDB:db_cnt_1\/clock_0 \PWM:PWMUDB:db_cnt_1\/q 1.250
Route 1 \PWM:PWMUDB:db_cnt_1\ \PWM:PWMUDB:db_cnt_1\/q \PWM:PWMUDB:db_ph2_run_temp\/main_3 3.086
macrocell21 U(1,2) 1 \PWM:PWMUDB:db_ph2_run_temp\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 4.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,3) 1 \PWM:PWMUDB:genblk1:ctrlreg\ \PWM:PWMUDB:genblk1:ctrlreg\/clock \PWM:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM:PWMUDB:control_7\ \PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.301
macrocell16 U(0,3) 1 \PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:db_cnt_1\/q \PWM:PWMUDB:db_cnt_1\/main_5 4.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,2) 1 \PWM:PWMUDB:db_cnt_1\ \PWM:PWMUDB:db_cnt_1\/clock_0 \PWM:PWMUDB:db_cnt_1\/q 1.250
macrocell22 U(1,2) 1 \PWM:PWMUDB:db_cnt_1\ \PWM:PWMUDB:db_cnt_1\/q \PWM:PWMUDB:db_cnt_1\/main_5 3.102
macrocell22 U(1,2) 1 \PWM:PWMUDB:db_cnt_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Sync_2:genblk1[0]:INST\/out \Counter_2:CounterUDB:disable_run_i\/main_0 3.108
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.000
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out \Counter_2:CounterUDB:disable_run_i\/main_0 3.108
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out \Counter_1:CounterUDB:disable_run_i\/main_0 3.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.000
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out \Counter_1:CounterUDB:disable_run_i\/main_0 3.117
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Counter_1:CounterUDB:disable_run_i\/q \Counter_1:CounterUDB:disable_run_i\/main_2 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ \Counter_1:CounterUDB:disable_run_i\/clock_0 \Counter_1:CounterUDB:disable_run_i\/q 1.250
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ \Counter_1:CounterUDB:disable_run_i\/q \Counter_1:CounterUDB:disable_run_i\/main_2 2.287
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Counter_2:CounterUDB:disable_run_i\/q \Counter_2:CounterUDB:disable_run_i\/main_2 3.894
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ \Counter_2:CounterUDB:disable_run_i\/clock_0 \Counter_2:CounterUDB:disable_run_i\/q 1.250
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ \Counter_2:CounterUDB:disable_run_i\/q \Counter_2:CounterUDB:disable_run_i\/main_2 2.644
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out \EdgeDetect_2:last\/main_0 4.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.000
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out \EdgeDetect_2:last\/main_0 4.170
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ HOLD 0.000
Clock Skew 0.000
\Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_2 \Counter_2:CounterUDB:prevCompare\/main_0 4.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,0) 1 \Counter_2:CounterUDB:sCTRLReg:ctrlreg\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_2 2.040
Route 1 \Counter_2:CounterUDB:ctrl_cmod_2\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_2 \Counter_2:CounterUDB:prevCompare\/main_0 2.690
macrocell30 U(0,0) 1 \Counter_2:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_1 \Counter_2:CounterUDB:prevCompare\/main_1 4.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,0) 1 \Counter_2:CounterUDB:sCTRLReg:ctrlreg\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_1 2.040
Route 1 \Counter_2:CounterUDB:ctrl_cmod_1\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_1 \Counter_2:CounterUDB:prevCompare\/main_1 2.691
macrocell30 U(0,0) 1 \Counter_2:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_0 \Counter_2:CounterUDB:prevCompare\/main_2 4.760
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(0,0) 1 \Counter_2:CounterUDB:sCTRLReg:ctrlreg\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_0 2.040
Route 1 \Counter_2:CounterUDB:ctrl_cmod_0\ \Counter_2:CounterUDB:sCTRLReg:ctrlreg\/control_0 \Counter_2:CounterUDB:prevCompare\/main_2 2.720
macrocell30 U(0,0) 1 \Counter_2:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_0 \Counter_1:CounterUDB:prevCompare\/main_2 4.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(0,1) 1 \Counter_1:CounterUDB:sCTRLReg:ctrlreg\ \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_0 2.040
Route 1 \Counter_1:CounterUDB:ctrl_cmod_0\ \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_0 \Counter_1:CounterUDB:prevCompare\/main_2 2.894
macrocell36 U(0,2) 1 \Counter_1:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_2 \Counter_1:CounterUDB:prevCompare\/main_0 5.240
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(0,1) 1 \Counter_1:CounterUDB:sCTRLReg:ctrlreg\ \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_2 2.040
Route 1 \Counter_1:CounterUDB:ctrl_cmod_2\ \Counter_1:CounterUDB:sCTRLReg:ctrlreg\/control_2 \Counter_1:CounterUDB:prevCompare\/main_0 3.200
macrocell36 U(0,2) 1 \Counter_1:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 -6.430 HOLD
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ \Relays_1:Sync:ctrl_reg\/busclk \Relays_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_2986 \Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 2.896
macrocell33 U(0,3) 1 Net_3011 HOLD 0.000
Clock Skew -11.366
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 -8.070 HOLD
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ \Relays_1:Sync:ctrl_reg\/busclk \Relays_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_2986 \Relays_1:Sync:ctrl_reg\/control_0 Net_3011/main_0 2.896
macrocell33 U(0,3) 1 Net_3011 HOLD 0.000
Clock Skew -13.006
Source Destination Slack (ns) Violation
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 3.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 2.616
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 7.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:overflow_status\/main_1 2.618
macrocell8 U(0,1) 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/main_1 \Counter_1:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 2.328
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 3.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:disable_run_i\/main_4 2.616
macrocell34 U(0,1) 1 \Counter_1:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 7.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(0,1) 1 \Counter_1:CounterUDB:overflow_reg_i\ Input Delay \Counter_1:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_1:CounterUDB:overflow_reg_i\ \Counter_1:CounterUDB:overflow_reg_i\/q \Counter_1:CounterUDB:overflow_status\/main_1 2.618
macrocell8 U(0,1) 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/main_1 \Counter_1:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_1:CounterUDB:overflow_status\ \Counter_1:CounterUDB:overflow_status\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/status_2 2.328
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 3.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 2.296
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 10.973
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:overflow_status\/main_1 4.757
macrocell4 U(0,2) 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/main_1 \Counter_2:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 3.616
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 3.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:disable_run_i\/main_4 2.296
macrocell27 U(0,1) 1 \Counter_2:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 10.973
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,1) 1 \Counter_2:CounterUDB:overflow_reg_i\ Input Delay \Counter_2:CounterUDB:overflow_reg_i\/q 0.000
Route 1 \Counter_2:CounterUDB:overflow_reg_i\ \Counter_2:CounterUDB:overflow_reg_i\/q \Counter_2:CounterUDB:overflow_status\/main_1 4.757
macrocell4 U(0,2) 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/main_1 \Counter_2:CounterUDB:overflow_status\/q 3.350
Route 1 \Counter_2:CounterUDB:overflow_status\ \Counter_2:CounterUDB:overflow_status\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/status_2 3.616
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 15.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 HOLD 0.000
Clock Skew -10.453
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 13.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 HOLD 0.000
Clock Skew -12.253
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 -6.238 HOLD
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 HOLD 0.000
Clock Skew -10.892
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 15.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 HOLD 0.000
Clock Skew -10.453
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 13.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 HOLD 0.000
Clock Skew -12.253
Source Destination Slack (ns) Violation
\Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 14.595
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,2) 1 \Relays_1:Sync:ctrl_reg\ Input Delay \Relays_1:Sync:ctrl_reg\/control_1 0.000
Route 1 Net_3017 \Relays_1:Sync:ctrl_reg\/control_1 Net_3018/main_0 2.614
macrocell32 U(0,2) 1 Net_3018 HOLD 0.000
Clock Skew -10.892
+ Asynchronous Clock Crossing Section
+ Source Clock Clock_1(FFB)
Source Destination Delay (ns)
\TCPWM:cy_m0s8_tcpwm_1\/line_compl AMuxHw_1_Decoder_one_hot_0/main_0 10.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \TCPWM:cy_m0s8_tcpwm_1\ \TCPWM:cy_m0s8_tcpwm_1\/clock \TCPWM:cy_m0s8_tcpwm_1\/line_compl 0.000
Route 1 Net_2578 \TCPWM:cy_m0s8_tcpwm_1\/line_compl AMuxHw_1_Decoder_one_hot_0/main_0 7.300
macrocell14 U(1,2) 1 AMuxHw_1_Decoder_one_hot_0 SETUP 3.510
Clock Skew 0.000
\TCPWM:cy_m0s8_tcpwm_1\/line_compl AMuxHw_1_Decoder_old_id_0/main_0 10.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \TCPWM:cy_m0s8_tcpwm_1\ \TCPWM:cy_m0s8_tcpwm_1\/clock \TCPWM:cy_m0s8_tcpwm_1\/line_compl 0.000
Route 1 Net_2578 \TCPWM:cy_m0s8_tcpwm_1\/line_compl AMuxHw_1_Decoder_old_id_0/main_0 6.744
macrocell13 U(1,2) 1 AMuxHw_1_Decoder_old_id_0 SETUP 3.510
Clock Skew 0.000
\TCPWM:cy_m0s8_tcpwm_1\/line_compl AMuxHw_1_Decoder_one_hot_1/main_0 8.623
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \TCPWM:cy_m0s8_tcpwm_1\ \TCPWM:cy_m0s8_tcpwm_1\/clock \TCPWM:cy_m0s8_tcpwm_1\/line_compl 0.000
Route 1 Net_2578 \TCPWM:cy_m0s8_tcpwm_1\/line_compl AMuxHw_1_Decoder_one_hot_1/main_0 5.113
macrocell15 U(1,1) 1 AMuxHw_1_Decoder_one_hot_1 SETUP 3.510
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_2215/q PumpP(0)_PAD 25.774
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,2) 1 Net_2215 Net_2215/clock_0 Net_2215/q 1.250
Route 1 Net_2215 Net_2215/q Net_2949/main_0 2.319
macrocell6 U(0,2) 1 Net_2949 Net_2949/main_0 Net_2949/q 3.350
Route 1 Net_2949 Net_2949/q PumpP(0)/pin_input 5.545
iocell26 P4[2] 1 PumpP(0) PumpP(0)/pin_input PumpP(0)/pad_out 13.310
Route 1 PumpP(0)_PAD PumpP(0)/pad_out PumpP(0)_PAD 0.000
Clock Clock path delay 0.000
Net_2216/q PumpN(0)_PAD 20.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 Net_2216 Net_2216/clock_0 Net_2216/q 1.250
Route 1 Net_2216 Net_2216/q PumpN(0)/pin_input 6.178
iocell27 P4[3] 1 PumpN(0) PumpN(0)/pin_input PumpN(0)/pad_out 13.370
Route 1 PumpN(0)_PAD PumpN(0)/pad_out PumpN(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_1(FFB)
Source Destination Delay (ns)
\TCPWM:cy_m0s8_tcpwm_1\/line PilotSw(0)_PAD 13.910
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \TCPWM:cy_m0s8_tcpwm_1\ \TCPWM:cy_m0s8_tcpwm_1\/clock \TCPWM:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_1923 \TCPWM:cy_m0s8_tcpwm_1\/line PilotSw(0)/pin_input 1.000
iocell13 P3[0] 1 PilotSw(0) PilotSw(0)/pin_input PilotSw(0)/pad_out 12.910
Route 1 PilotSw(0)_PAD PilotSw(0)/pad_out PilotSw(0)_PAD 0.000
Clock Clock path delay 0.000
+ \Counter_1:CounterUDB:overflow_reg_i\/q
Source Destination Delay (ns)
Net_3011/q RelayN(0)_PAD 33.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(0,3) 1 Net_3011 Net_3011/clock_0 Net_3011/q 1.250
Route 1 Net_3011 Net_3011/q RelayN(0)/pin_input 5.541
iocell24 P0[4] 1 RelayN(0) RelayN(0)/pin_input RelayN(0)/pad_out 15.380
Route 1 RelayN(0)_PAD RelayN(0)/pad_out RelayN(0)_PAD 0.000
Clock Clock path delay 11.366
Net_3018/q RelayL(0)_PAD 32.637
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(0,2) 1 Net_3018 Net_3018/clock_0 Net_3018/q 1.250
Route 1 Net_3018 Net_3018/q RelayL(0)/pin_input 5.924
iocell21 P0[5] 1 RelayL(0) RelayL(0)/pin_input RelayL(0)/pad_out 15.010
Route 1 RelayL(0)_PAD RelayL(0)/pad_out RelayL(0)_PAD 0.000
Clock Clock path delay 10.453
+ \Counter_2:CounterUDB:overflow_reg_i\/q
Source Destination Delay (ns)
Net_3011/q RelayN(0)_PAD 35.177
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(0,3) 1 Net_3011 Net_3011/clock_0 Net_3011/q 1.250
Route 1 Net_3011 Net_3011/q RelayN(0)/pin_input 5.541
iocell24 P0[4] 1 RelayN(0) RelayN(0)/pin_input RelayN(0)/pad_out 15.380
Route 1 RelayN(0)_PAD RelayN(0)/pad_out RelayN(0)_PAD 0.000
Clock Clock path delay 13.006
Net_3018/q RelayL(0)_PAD 34.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(0,2) 1 Net_3018 Net_3018/clock_0 Net_3018/q 1.250
Route 1 Net_3018 Net_3018/q RelayL(0)/pin_input 5.924
iocell21 P0[5] 1 RelayL(0) RelayL(0)/pin_input RelayL(0)/pad_out 15.010
Route 1 RelayL(0)_PAD RelayL(0)/pad_out RelayL(0)_PAD 0.000
Clock Clock path delay 12.253
+ \Relays_1:Sync:ctrl_reg\/control_1
Source Destination Delay (ns)
Net_3018/q RelayL(0)_PAD 33.076
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(0,2) 1 Net_3018 Net_3018/clock_0 Net_3018/q 1.250
Route 1 Net_3018 Net_3018/q RelayL(0)/pin_input 5.924
iocell21 P0[5] 1 RelayL(0) RelayL(0)/pin_input RelayL(0)/pad_out 15.010
Route 1 RelayL(0)_PAD RelayL(0)/pad_out RelayL(0)_PAD 0.000
Clock Clock path delay 10.892
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 42666.7ns(23.4375 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Sync_2:genblk1[0]:INST\/out \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 70.746 MHz 14.135 42652.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.480
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out Net_2263/main_0 4.181
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_0 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 5.124
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\EdgeDetect_2:last\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 78.487 MHz 12.741 42653.926
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/clock_0 \EdgeDetect_2:last\/q 1.250
Route 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/q Net_2263/main_1 3.017
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_1 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 5.124
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 85.143 MHz 11.745 42654.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.480
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out Net_2263/main_0 4.181
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_0 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 2.734
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\EdgeDetect_2:last\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 96.609 MHz 10.351 42656.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/clock_0 \EdgeDetect_2:last\/q 1.250
Route 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/q Net_2263/main_1 3.017
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_1 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 2.734
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Sync_2:genblk1[0]:INST\/out \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 10.265
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.000
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out Net_2263/main_0 4.181
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_0 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 2.734
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\EdgeDetect_2:last\/q \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 10.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/clock_0 \EdgeDetect_2:last\/q 1.250
Route 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/q Net_2263/main_1 3.017
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_1 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_2:CounterUDB:sSTSReg:stsreg\/reset 2.734
statusicell2 U(0,0) 1 \Counter_2:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 12.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.000
Route 1 Net_2262 \Sync_2:genblk1[0]:INST\/out Net_2263/main_0 4.181
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_0 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 5.124
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\EdgeDetect_2:last\/q \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 12.741
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,0) 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/clock_0 \EdgeDetect_2:last\/q 1.250
Route 1 \EdgeDetect_2:last\ \EdgeDetect_2:last\/q Net_2263/main_1 3.017
macrocell2 U(0,0) 1 Net_2263 Net_2263/main_1 Net_2263/q 3.350
Route 1 Net_2263 Net_2263/q \Counter_1:CounterUDB:sSTSReg:stsreg\/reset 5.124
statusicell3 U(0,1) 1 \Counter_1:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000