Static Timing Analysis

Project : PSOCBLE_PERIPHERAL
Build Time : 01/24/19 23:52:18
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_intClock(FFB) ADC_SAR_intClock(FFB) 1.000 MHz 1.000 MHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
ADC_SAR_intClock CyHFCLK 1.000 MHz 1.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Clock To Output Section
+ ADC_SAR_intClock(FFB)
Source Destination Delay (ns)
\ADC_SAR:cy_psoc4_sar\/tr_sar_out salidaADC(0)_PAD 20.346
Type Location Fanout Instance/Net Source Dest Delay (ns)
p4sarcell F(SARADC,0) 1 \ADC_SAR:cy_psoc4_sar\ \ADC_SAR:cy_psoc4_sar\/clock \ADC_SAR:cy_psoc4_sar\/tr_sar_out 0.000
Route 1 Net_80 \ADC_SAR:cy_psoc4_sar\/tr_sar_out salidaADC(0)/pin_input 5.679
iocell1 P3[7] 1 salidaADC(0) salidaADC(0)/pin_input salidaADC(0)/pad_out 14.667
Route 1 salidaADC(0)_PAD salidaADC(0)/pad_out salidaADC(0)_PAD 0.000
Clock Clock path delay 0.000