Static Timing Analysis

Project : CySmartDisplay
Build Time : 05/11/17 01:09:23
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA.1 : 5.00
VDDA.CTB : 5.00
VDDD.0 : 5.00
VDDIO_0 : 5.00
VDDIO_1 : 5.00
VDDIO_2 : 5.00
VDDR_BGLS : 5.00
VDDR_HF : 5.00
VDDR_HLS : 5.00
VDDR_LF : 5.00
VDDR_SYN : 5.00
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
CyHFCLK Clock_1 -0.218
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 47.504 MHz Frequency
Timer_CLK CyHFCLK 16.000 MHz 16.000 MHz N/A
Clock_1 CyHFCLK 76.800 kHz 76.800 kHz 44.819 MHz
MAX7219_SCBCLK CyHFCLK 8.000 MHz 8.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
MAX7219_SCBCLK(FFB) MAX7219_SCBCLK(FFB) 8.000 MHz 8.000 MHz N/A
Timer_CLK(FFB) Timer_CLK(FFB) 16.000 MHz 16.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 13020.8ns(76.8 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.819 MHz 22.312 12998.521
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.209
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.233
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.475 MHz 21.517 12999.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.164
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.233
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.557 MHz 21.479 12999.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.126
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.233
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.154 MHz 21.207 12999.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.854
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.233
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 49.561 MHz 20.177 13000.656
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 7.520
macrocell10 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.069 MHz 16.111 13004.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 3.646
macrocell22 U(1,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.265
statusicell2 U(1,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 64.053 MHz 15.612 13005.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,0) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_1 2.955
macrocell10 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:rx_state_0\/main_10 64.566 MHz 15.488 13005.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_state_0\/main_10 10.728
macrocell11 U(1,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:rx_status_3\/main_7 64.566 MHz 15.488 13005.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_status_3\/main_7 10.728
macrocell15 U(1,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:rx_address_detected\/q \UART:BUART:sRX:RxBitCounter\/load 65.686 MHz 15.224 13005.609
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/clock_0 \UART:BUART:rx_address_detected\/q 1.250
Route 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/q \UART:BUART:rx_counter_load\/main_0 4.077
macrocell7 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 47.504 MHz 21.051 -0.218 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_postpoll\/main_0 5.597
macrocell10 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_last\/main_0 72.685 MHz 13.758 7.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_last\/main_0 6.201
macrocell8 U(1,1) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_2\/main_0 72.685 MHz 13.758 7.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_state_2\/main_0 6.201
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_0\/main_0 72.722 MHz 13.751 7.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_state_0\/main_0 6.194
macrocell11 U(1,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_status_3\/main_0 72.722 MHz 13.751 7.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_status_3\/main_0 6.194
macrocell15 U(1,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_1\/main_0 75.953 MHz 13.166 7.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:pollcount_1\/main_0 5.609
macrocell4 U(1,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_0\/main_0 76.023 MHz 13.154 7.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_56 Rx(0)/fb \UART:BUART:pollcount_0\/main_0 5.597
macrocell3 U(1,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.317
statusicell1 U(0,1) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.480
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell24 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.230
macrocell24 U(0,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.561
macrocell21 U(0,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 3.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,1) 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/clock_0 \UART:BUART:rx_last\/q 1.250
Route 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 2.313
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.572
macrocell20 U(0,0) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.572
macrocell24 U(0,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 2.584
macrocell9 U(1,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_5 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_5 2.584
macrocell11 U(1,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_3\/main_4 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_3\/main_4 2.584
macrocell13 U(1,1) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_status_3\/main_5 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_status_3\/main_5 2.584
macrocell15 U(1,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx(0)/fb \UART:BUART:pollcount_0\/main_0 8.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:pollcount_0\/main_0 5.597
macrocell3 U(1,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_1\/main_0 8.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:pollcount_1\/main_0 5.609
macrocell4 U(1,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_0\/main_0 8.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_state_0\/main_0 6.194
macrocell11 U(1,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_status_3\/main_0 8.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_status_3\/main_0 6.194
macrocell15 U(1,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_last\/main_0 8.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_last\/main_0 6.201
macrocell8 U(1,1) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_2\/main_0 8.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_state_2\/main_0 6.201
macrocell12 U(1,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P1[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_56 Rx(0)/fb \UART:BUART:rx_postpoll\/main_0 5.597
macrocell10 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx(0)_PAD 27.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_52/main_0 3.145
macrocell1 U(0,1) 1 Net_52 Net_52/main_0 Net_52/q 3.350
Route 1 Net_52 Net_52/q Tx(0)/pin_input 6.146
iocell3 P1[5] 1 Tx(0) Tx(0)/pin_input Tx(0)/pad_out 14.059
Route 1 Tx(0)_PAD Tx(0)/pad_out Tx(0)_PAD 0.000
Clock Clock path delay 0.000