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00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
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00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
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00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
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00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
00000000 a BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$WCHAR32$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2
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402e1058 a CyBle_cy_m0s8_ble__DEVICE_RAND_ADDR_L
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402e00d8 a CyBle_cy_m0s8_ble__DSM3
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402e00dc a CyBle_cy_m0s8_ble__DSM4
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402e00e0 a CyBle_cy_m0s8_ble__DSM5
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402e14a0 a CyBle_cy_m0s8_ble__ENC_INTR
402e14a0 a CyBle_cy_m0s8_ble__ENC_INTR
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402e1498 a CyBle_cy_m0s8_ble__ENC_INTR_EN
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402e1420 a CyBle_cy_m0s8_ble__ENC_KEY0
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402e1428 a CyBle_cy_m0s8_ble__ENC_KEY2
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402e142c a CyBle_cy_m0s8_ble__ENC_KEY3
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402e1430 a CyBle_cy_m0s8_ble__ENC_KEY4
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402e1434 a CyBle_cy_m0s8_ble__ENC_KEY5
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402e1438 a CyBle_cy_m0s8_ble__ENC_KEY6
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402e143c a CyBle_cy_m0s8_ble__ENC_KEY7
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402e2200 a CyBle_cy_m0s8_ble__ENC_MEM_BASE_ADDR
402e1488 a CyBle_cy_m0s8_ble__ENC_PARAMS
402e1488 a CyBle_cy_m0s8_ble__ENC_PARAMS
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402e1010 a CyBle_cy_m0s8_ble__EVENT_ENABLE
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402e1008 a CyBle_cy_m0s8_ble__EVENT_INTR
402e0044 a CyBle_cy_m0s8_ble__FCAL_TEST
402e0044 a CyBle_cy_m0s8_ble__FCAL_TEST
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402e004c a CyBle_cy_m0s8_ble__FPD_TEST
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402e000c a CyBle_cy_m0s8_ble__FSM
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402e0064 a CyBle_cy_m0s8_ble__IM
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402e1040 a CyBle_cy_m0s8_ble__INIT_INTERVAL
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402e1050 a CyBle_cy_m0s8_ble__INIT_INTR
402e1054 a CyBle_cy_m0s8_ble__INIT_NEXT_INSTANT
402e1054 a CyBle_cy_m0s8_ble__INIT_NEXT_INSTANT
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402e10f8 a CyBle_cy_m0s8_ble__INIT_SCN_ADV_RX_FIFO
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402e1044 a CyBle_cy_m0s8_ble__INIT_WINDOW
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402e00c4 a CyBle_cy_m0s8_ble__IQMIS
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402e1410 a CyBle_cy_m0s8_ble__IV_MASTER0
402e1414 a CyBle_cy_m0s8_ble__IV_MASTER1
402e1414 a CyBle_cy_m0s8_ble__IV_MASTER1
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402e1418 a CyBle_cy_m0s8_ble__IV_SLAVE0
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402e141c a CyBle_cy_m0s8_ble__IV_SLAVE1
402e0028 a CyBle_cy_m0s8_ble__KVCAL
402e0028 a CyBle_cy_m0s8_ble__KVCAL
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402e0068 a CyBle_cy_m0s8_ble__LDO_BYPASS
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402e1a20 a CyBle_cy_m0s8_ble__LE_PING_TIMER_ADDR
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00000000 a CYFLD_BLE_BLELL_ADV_SCAN_RSP_RX_DATA__OFFSET
00000000 a CYFLD_BLE_BLELL_ADV_SCAN_RSP_RX_DATA__OFFSET
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00000009 a CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE
00000004 a CYFLD_BLE_BLELL_ADV_SCN_REQ_RX_EN__OFFSET
00000004 a CYFLD_BLE_BLELL_ADV_SCN_REQ_RX_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_SCN_REQ_RX_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_SCN_REQ_RX_EN__SIZE
00000000 a CYFLD_BLE_BLELL_ADV_STRT_EN__OFFSET
00000000 a CYFLD_BLE_BLELL_ADV_STRT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_STRT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_STRT_EN__SIZE
00000000 a CYFLD_BLE_BLELL_ADV_STRT_INTR__OFFSET
00000000 a CYFLD_BLE_BLELL_ADV_STRT_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_STRT_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_STRT_INTR__SIZE
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00000007 a CYFLD_BLE_BLELL_ADV_TIMEOUT__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_TIMEOUT__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_TIMEOUT__SIZE
00000007 a CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__OFFSET
00000007 a CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__SIZE
00000000 a CYFLD_BLE_BLELL_ADV_TRANSMIT_POWER__OFFSET
00000000 a CYFLD_BLE_BLELL_ADV_TRANSMIT_POWER__OFFSET
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00000000 a CYFLD_BLE_BLELL_ADV_TX_DATA__OFFSET
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00000001 a CYFLD_BLE_BLELL_ADV_TX_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_TX_EN__SIZE
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00000002 a CYFLD_BLE_BLELL_ADV_TX_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_TX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_TX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_ADV_TYPE__OFFSET
00000001 a CYFLD_BLE_BLELL_ADV_TYPE__OFFSET
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00000001 a CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE
00000001 a CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE
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00000001 a CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE
00000001 a CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE
00000000 a CYFLD_BLE_BLELL_AUTH_PASS_INTR__OFFSET
00000000 a CYFLD_BLE_BLELL_AUTH_PASS_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_AUTH_PASS_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_AUTH_PASS_INTR__SIZE
00000000 a CYFLD_BLE_BLELL_AUTH_PASS_INTR_EN__OFFSET
00000000 a CYFLD_BLE_BLELL_AUTH_PASS_INTR_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_AUTH_PASS_INTR_EN__SIZE
00000001 a CYFLD_BLE_BLELL_AUTH_PASS_INTR_EN__SIZE
0000000b a CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET
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00000001 a CYFLD_BLE_BLELL_BACKOFF_ENABLE__SIZE
00000001 a CYFLD_BLE_BLELL_BACKOFF_ENABLE__SIZE
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00000002 a CYFLD_BLE_BLELL_CCM_PROC_INTR__OFFSET
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00000001 a CYFLD_BLE_BLELL_CCM_PROC_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_CCM_PROC_INTR__SIZE
00000002 a CYFLD_BLE_BLELL_CCM_PROC_INTR_EN__OFFSET
00000002 a CYFLD_BLE_BLELL_CCM_PROC_INTR_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_CCM_PROC_INTR_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CCM_PROC_INTR_EN__SIZE
00000000 a CYFLD_BLE_BLELL_CE_INSTANT__OFFSET
00000000 a CYFLD_BLE_BLELL_CE_INSTANT__OFFSET
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00000001 a CYFLD_BLE_BLELL_CE_RX__SIZE
00000001 a CYFLD_BLE_BLELL_CE_RX__SIZE
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00000001 a CYFLD_BLE_BLELL_CE_RX_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CE_RX_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CE_TX_ACK__SIZE
00000001 a CYFLD_BLE_BLELL_CE_TX_ACK__SIZE
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00000001 a CYFLD_BLE_BLELL_CE_TX_ACK_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CE_TX_ACK_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CLOSE_CE__SIZE
00000001 a CYFLD_BLE_BLELL_CLOSE_CE__SIZE
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00000001 a CYFLD_BLE_BLELL_CLOSE_CE_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CLOSE_CE_INT_EN__SIZE
00000000 a CYFLD_BLE_BLELL_COMMAND__OFFSET
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00000001 a CYFLD_BLE_BLELL_CON_UPDT_DONE__SIZE
00000001 a CYFLD_BLE_BLELL_CON_UPDT_DONE__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_ACTIVE__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_ACTIVE__SIZE
00000000 a CYFLD_BLE_BLELL_CONN_CL_INT_EN__OFFSET
00000000 a CYFLD_BLE_BLELL_CONN_CL_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_CONN_CL_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_CL_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_CLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_CLK_GATE_EN__SIZE
00000000 a CYFLD_BLE_BLELL_CONN_CLOSED__OFFSET
00000000 a CYFLD_BLE_BLELL_CONN_CLOSED__OFFSET
00000001 a CYFLD_BLE_BLELL_CONN_CLOSED__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_CLOSED__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_CREATED__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_CREATED__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_ESTB__OFFSET
00000001 a CYFLD_BLE_BLELL_CONN_ESTB__OFFSET
00000001 a CYFLD_BLE_BLELL_CONN_ESTB__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_ESTB__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_ESTB_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_CONN_ESTB_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_CONN_ESTB_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_ESTB_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_REQ_1SLOT_EARLY__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_REQ_1SLOT_EARLY__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_REQ_RX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_REQ_RX_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_REQ_TX_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_REQ_TX_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CONN_UPDATE_INTR_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CONN_UPDATE_INTR_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_CORECLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_CORECLK_GATE_EN__SIZE
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00000000 a CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_H__OFFSET
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00000000 a CYFLD_BLE_BLELL_DEVICE_RAND_ADDR_M__OFFSET
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00000001 a CYFLD_BLE_BLELL_DLE__OFFSET
00000001 a CYFLD_BLE_BLELL_DLE__OFFSET
00000001 a CYFLD_BLE_BLELL_DLE__SIZE
00000001 a CYFLD_BLE_BLELL_DLE__SIZE
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00000001 a CYFLD_BLE_BLELL_DSM_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_DSM_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_DSM_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_DSM_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_DSM_SLOT_VARIANCE__SIZE
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00000001 a CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE
00000001 a CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE
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00000001 a CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ECB_CCM__OFFSET
00000001 a CYFLD_BLE_BLELL_ECB_CCM__OFFSET
00000001 a CYFLD_BLE_BLELL_ECB_CCM__SIZE
00000001 a CYFLD_BLE_BLELL_ECB_CCM__SIZE
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00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ECB_PROC_INTR_EN__SIZE
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0000000d a CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__OFFSET
00000001 a CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE
00000001 a CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE
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00000001 a CYFLD_BLE_BLELL_ENC_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_ENC_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_ENC_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_ENC_INTR__SIZE
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00000000 a CYFLD_BLE_BLELL_ENC_KEY__OFFSET
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00000000 a CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET
00000000 a CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET
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0000000d a CYFLD_BLE_BLELL_EXTEND_CU_TX_WIN__OFFSET
0000000d a CYFLD_BLE_BLELL_EXTEND_CU_TX_WIN__OFFSET
00000001 a CYFLD_BLE_BLELL_EXTEND_CU_TX_WIN__SIZE
00000001 a CYFLD_BLE_BLELL_EXTEND_CU_TX_WIN__SIZE
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00000000 a CYFLD_BLE_BLELL_HOP_INCREMENT_2__OFFSET
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00000001 a CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE
00000001 a CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE
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00000001 a CYFLD_BLE_BLELL_IN_DATA_CLEAR__SIZE
00000001 a CYFLD_BLE_BLELL_IN_DATA_CLEAR__SIZE
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00000001 a CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
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00000009 a CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_CLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_CLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_WINDOW_INR__OFFSET
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_WINDOW_INR__OFFSET
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_WINDOW_INR__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_CLOSE_WINDOW_INR__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_INT_EN__SIZE
00000000 a CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__OFFSET
00000000 a CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_INTR__SIZE
00000000 a CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__OFFSET
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00000001 a CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE
00000000 a CYFLD_BLE_BLELL_INIT_SCAN_INTERVAL__OFFSET
00000000 a CYFLD_BLE_BLELL_INIT_SCAN_INTERVAL__OFFSET
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00000000 a CYFLD_BLE_BLELL_INIT_STRT_EN__OFFSET
00000000 a CYFLD_BLE_BLELL_INIT_STRT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_INIT_STRT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_STRT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_INIT_TX_START_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INIT_TX_START_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE
00000001 a CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE
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00000001 a CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE
00000001 a CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE
00000000 a CYFLD_BLE_BLELL_IV_MASTER_LOWER__OFFSET
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00000000 a CYFLD_BLE_BLELL_LIST_INDEX__TX_ACK_3_0__OFFSET
00000000 a CYFLD_BLE_BLELL_LIST_INDEX__TX_ACK_3_0__OFFSET
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00000000 a CYFLD_BLE_BLELL_LIST_INDEX__TX_SENT_3_0__OFFSET
00000000 a CYFLD_BLE_BLELL_LIST_INDEX__TX_SENT_3_0__OFFSET
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00000001 a CYFLD_BLE_BLELL_LLH_IDLE__SIZE
00000001 a CYFLD_BLE_BLELL_LLH_IDLE__SIZE
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00000001 a CYFLD_BLE_BLELL_LPO_CLK_FREQ_SEL__SIZE
00000001 a CYFLD_BLE_BLELL_LPO_CLK_FREQ_SEL__SIZE
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00000001 a CYFLD_BLE_BLELL_LPO_SEL_EXTERNAL__SIZE
00000001 a CYFLD_BLE_BLELL_LPO_SEL_EXTERNAL__SIZE
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00000001 a CYFLD_BLE_BLELL_MAP_INDEX__CURR_INDEX__SIZE
00000001 a CYFLD_BLE_BLELL_MAP_INDEX__CURR_INDEX__SIZE
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00000001 a CYFLD_BLE_BLELL_MAP_UPDT_DONE__SIZE
00000001 a CYFLD_BLE_BLELL_MAP_UPDT_DONE__SIZE
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00000001 a CYFLD_BLE_BLELL_MAP_UPDT_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_MAP_UPDT_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_MAS_SLV__SIZE
00000001 a CYFLD_BLE_BLELL_MAS_SLV__SIZE
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00000001 a CYFLD_BLE_BLELL_MASK_SUTO_AT_UPDT__SIZE
00000001 a CYFLD_BLE_BLELL_MASK_SUTO_AT_UPDT__SIZE
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00000001 a CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE
00000001 a CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE
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00000001 a CYFLD_BLE_BLELL_MD__SIZE
00000001 a CYFLD_BLE_BLELL_MD__SIZE
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00000001 a CYFLD_BLE_BLELL_MD_BIT_CLEAR__SIZE
00000001 a CYFLD_BLE_BLELL_MD_BIT_CLEAR__SIZE
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00000001 a CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE
00000001 a CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE
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00000000 a CYFLD_BLE_BLELL_PACKET_COUNTER_MIDDLE__OFFSET
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00000001 a CYFLD_BLE_BLELL_PAUSE_DATA__SIZE
00000001 a CYFLD_BLE_BLELL_PAUSE_DATA__SIZE
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00000000 a CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_HIGHER_BITS__OFFSET
00000000 a CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_HIGHER_BITS__OFFSET
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00000000 a CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_LOWER_BITS__OFFSET
00000000 a CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_LOWER_BITS__OFFSET
00000010 a CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_LOWER_BITS__SIZE
00000010 a CYFLD_BLE_BLELL_PDU_ACCESS_ADDRESS_LOWER_BITS__SIZE
00000000 a CYFLD_BLE_BLELL_PDU_RESP_TIME_VAL__OFFSET
00000000 a CYFLD_BLE_BLELL_PDU_RESP_TIME_VAL__OFFSET
00000010 a CYFLD_BLE_BLELL_PDU_RESP_TIME_VAL__SIZE
00000010 a CYFLD_BLE_BLELL_PDU_RESP_TIME_VAL__SIZE
00000000 a CYFLD_BLE_BLELL_PEER_ADDR_H__OFFSET
00000000 a CYFLD_BLE_BLELL_PEER_ADDR_H__OFFSET
00000010 a CYFLD_BLE_BLELL_PEER_ADDR_H__SIZE
00000010 a CYFLD_BLE_BLELL_PEER_ADDR_H__SIZE
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE
00000000 a CYFLD_BLE_BLELL_PEER_ADDR_L__OFFSET
00000000 a CYFLD_BLE_BLELL_PEER_ADDR_L__OFFSET
00000010 a CYFLD_BLE_BLELL_PEER_ADDR_L__SIZE
00000010 a CYFLD_BLE_BLELL_PEER_ADDR_L__SIZE
00000000 a CYFLD_BLE_BLELL_PEER_ADDR_M__OFFSET
00000000 a CYFLD_BLE_BLELL_PEER_ADDR_M__OFFSET
00000010 a CYFLD_BLE_BLELL_PEER_ADDR_M__SIZE
00000010 a CYFLD_BLE_BLELL_PEER_ADDR_M__SIZE
00000009 a CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
00000009 a CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000005 a CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET
00000005 a CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE
00000004 a CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET
00000004 a CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE
00000001 a CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE
00000006 a CYFLD_BLE_BLELL_PHY_CLK_GATE_EN__OFFSET
00000006 a CYFLD_BLE_BLELL_PHY_CLK_GATE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_PHY_CLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_PHY_CLK_GATE_EN__SIZE
0000000f a CYFLD_BLE_BLELL_PING_NEARLY_EXPIRD_INTR__OFFSET
0000000f a CYFLD_BLE_BLELL_PING_NEARLY_EXPIRD_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_PING_NEARLY_EXPIRD_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_PING_NEARLY_EXPIRD_INTR__SIZE
0000000e a CYFLD_BLE_BLELL_PING_TIMER_EXPIRD_INTR__OFFSET
0000000e a CYFLD_BLE_BLELL_PING_TIMER_EXPIRD_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_PING_TIMER_EXPIRD_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_PING_TIMER_EXPIRD_INTR__SIZE
00000007 a CYFLD_BLE_BLELL_PKT_PAYLOAD__OFFSET
00000007 a CYFLD_BLE_BLELL_PKT_PAYLOAD__OFFSET
00000003 a CYFLD_BLE_BLELL_PKT_PAYLOAD__SIZE
00000003 a CYFLD_BLE_BLELL_PKT_PAYLOAD__SIZE
00000000 a CYFLD_BLE_BLELL_PRIV_1_2__OFFSET
00000000 a CYFLD_BLE_BLELL_PRIV_1_2__OFFSET
00000001 a CYFLD_BLE_BLELL_PRIV_1_2__SIZE
00000001 a CYFLD_BLE_BLELL_PRIV_1_2__SIZE
0000000a a CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET
0000000a a CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET
00000001 a CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE
00000001 a CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE
0000000c a CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET
0000000c a CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET
00000001 a CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE
00000001 a CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE
0000000b a CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET
0000000b a CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET
00000001 a CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE
00000001 a CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE
00000000 a CYFLD_BLE_BLELL_QUICK_TRANSMIT__OFFSET
00000000 a CYFLD_BLE_BLELL_QUICK_TRANSMIT__OFFSET
00000001 a CYFLD_BLE_BLELL_QUICK_TRANSMIT__SIZE
00000001 a CYFLD_BLE_BLELL_QUICK_TRANSMIT__SIZE
0000000f a CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET
0000000f a CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET
00000001 a CYFLD_BLE_BLELL_RCV_TX_ADDR__SIZE
00000001 a CYFLD_BLE_BLELL_RCV_TX_ADDR__SIZE
0000000c a CYFLD_BLE_BLELL_RECEIVE_PACKET_COUNT__OFFSET
0000000c a CYFLD_BLE_BLELL_RECEIVE_PACKET_COUNT__OFFSET
00000004 a CYFLD_BLE_BLELL_RECEIVE_PACKET_COUNT__SIZE
00000004 a CYFLD_BLE_BLELL_RECEIVE_PACKET_COUNT__SIZE
00000005 a CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET
00000005 a CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET
00000001 a CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE
00000001 a CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE
00000008 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET
00000008 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET
00000001 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE
00000001 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE
00000007 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET
00000007 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET
00000001 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE
00000001 a CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE
00000006 a CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET
00000006 a CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET
00000001 a CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE
00000001 a CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE
00000009 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET
00000009 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET
00000001 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE
00000001 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE
00000008 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET
00000008 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET
00000001 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE
00000001 a CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET
00000000 a CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE
00000010 a CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE
00000008 a CYFLD_BLE_BLELL_RX_ADDR__OFFSET
00000008 a CYFLD_BLE_BLELL_RX_ADDR__OFFSET
00000001 a CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__OFFSET
00000001 a CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__OFFSET
00000001 a CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__SIZE
00000001 a CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__SIZE
00000001 a CYFLD_BLE_BLELL_RX_ADDR__SIZE
00000001 a CYFLD_BLE_BLELL_RX_ADDR__SIZE
00000009 a CYFLD_BLE_BLELL_RX_BAD_PDU_INT_EN__OFFSET
00000009 a CYFLD_BLE_BLELL_RX_BAD_PDU_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_RX_BAD_PDU_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_RX_BAD_PDU_INT_EN__SIZE
00000000 a CYFLD_BLE_BLELL_RX_EN_DELAY__OFFSET
00000000 a CYFLD_BLE_BLELL_RX_EN_DELAY__OFFSET
00000008 a CYFLD_BLE_BLELL_RX_EN_DELAY__SIZE
00000008 a CYFLD_BLE_BLELL_RX_EN_DELAY__SIZE
00000008 a CYFLD_BLE_BLELL_RX_GOOD_PDU_INT_EN__OFFSET
00000008 a CYFLD_BLE_BLELL_RX_GOOD_PDU_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_RX_GOOD_PDU_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_RX_GOOD_PDU_INT_EN__SIZE
00000004 a CYFLD_BLE_BLELL_RX_INTR_THRESHOLD__OFFSET
00000004 a CYFLD_BLE_BLELL_RX_INTR_THRESHOLD__OFFSET
00000004 a CYFLD_BLE_BLELL_RX_INTR_THRESHOLD__SIZE
00000004 a CYFLD_BLE_BLELL_RX_INTR_THRESHOLD__SIZE
00000000 a CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET
00000000 a CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET
00000010 a CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE
00000010 a CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE
0000000b a CYFLD_BLE_BLELL_RX_PDU_STATUS__OFFSET
0000000b a CYFLD_BLE_BLELL_RX_PDU_STATUS__OFFSET
00000003 a CYFLD_BLE_BLELL_RX_PDU_STATUS__SIZE
00000003 a CYFLD_BLE_BLELL_RX_PDU_STATUS__SIZE
00000000 a CYFLD_BLE_BLELL_RX_PKT_LIMIT__OFFSET
00000000 a CYFLD_BLE_BLELL_RX_PKT_LIMIT__OFFSET
00000004 a CYFLD_BLE_BLELL_RX_PKT_LIMIT__SIZE
00000004 a CYFLD_BLE_BLELL_RX_PKT_LIMIT__SIZE
00000000 a CYFLD_BLE_BLELL_RXON_DELAY__OFFSET
00000000 a CYFLD_BLE_BLELL_RXON_DELAY__OFFSET
00000008 a CYFLD_BLE_BLELL_RXON_DELAY__SIZE
00000008 a CYFLD_BLE_BLELL_RXON_DELAY__SIZE
00000005 a CYFLD_BLE_BLELL_SCA_2__OFFSET
00000005 a CYFLD_BLE_BLELL_SCA_2__OFFSET
00000003 a CYFLD_BLE_BLELL_SCA_2__SIZE
00000003 a CYFLD_BLE_BLELL_SCA_2__SIZE
00000000 a CYFLD_BLE_BLELL_SCA_PARAM__OFFSET
00000000 a CYFLD_BLE_BLELL_SCA_PARAM__OFFSET
00000003 a CYFLD_BLE_BLELL_SCA_PARAM__SIZE
00000003 a CYFLD_BLE_BLELL_SCA_PARAM__SIZE
0000000c a CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
0000000c a CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
0000000d a CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__OFFSET
0000000d a CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__OFFSET
00000003 a CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__SIZE
00000003 a CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_CLK_GATE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_CLK_GATE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_CLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_CLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_CLOSE_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_CLOSE_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_CLOSE_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_CLOSE_INTR__SIZE
00000003 a CYFLD_BLE_BLELL_SCAN_FILT_POLICY__OFFSET
00000003 a CYFLD_BLE_BLELL_SCAN_FILT_POLICY__OFFSET
00000002 a CYFLD_BLE_BLELL_SCAN_FILT_POLICY__SIZE
00000002 a CYFLD_BLE_BLELL_SCAN_FILT_POLICY__SIZE
00000000 a CYFLD_BLE_BLELL_SCAN_INTERVAL__OFFSET
00000000 a CYFLD_BLE_BLELL_SCAN_INTERVAL__OFFSET
00000010 a CYFLD_BLE_BLELL_SCAN_INTERVAL__SIZE
00000010 a CYFLD_BLE_BLELL_SCAN_INTERVAL__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_INTR__SIZE
00000008 a CYFLD_BLE_BLELL_SCAN_ON__OFFSET
00000008 a CYFLD_BLE_BLELL_SCAN_ON__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_ON__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_ON__SIZE
00000008 a CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET
00000008 a CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE
00000004 a CYFLD_BLE_BLELL_SCAN_REQ_RX_INTR__OFFSET
00000004 a CYFLD_BLE_BLELL_SCAN_REQ_RX_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_REQ_RX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_REQ_RX_INTR__SIZE
0000000a a CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET
0000000a a CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE
00000009 a CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET
00000009 a CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE
00000007 a CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET
00000007 a CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE
00000000 a CYFLD_BLE_BLELL_SCAN_RSP_DATA__OFFSET
00000000 a CYFLD_BLE_BLELL_SCAN_RSP_DATA__OFFSET
00000010 a CYFLD_BLE_BLELL_SCAN_RSP_DATA__SIZE
00000010 a CYFLD_BLE_BLELL_SCAN_RSP_DATA__SIZE
00000004 a CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET
00000004 a CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE
00000003 a CYFLD_BLE_BLELL_SCAN_RSP_TX_INTR__OFFSET
00000003 a CYFLD_BLE_BLELL_SCAN_RSP_TX_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_RSP_TX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_RSP_TX_INTR__SIZE
00000000 a CYFLD_BLE_BLELL_SCAN_STRT_INTR__OFFSET
00000000 a CYFLD_BLE_BLELL_SCAN_STRT_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_STRT_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_STRT_INTR__SIZE
00000002 a CYFLD_BLE_BLELL_SCAN_TX_INTR__OFFSET
00000002 a CYFLD_BLE_BLELL_SCAN_TX_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_TX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_TX_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCAN_TYPE__OFFSET
00000001 a CYFLD_BLE_BLELL_SCAN_TYPE__OFFSET
00000002 a CYFLD_BLE_BLELL_SCAN_TYPE__SIZE
00000002 a CYFLD_BLE_BLELL_SCAN_TYPE__SIZE
00000000 a CYFLD_BLE_BLELL_SCAN_WINDOW__OFFSET
00000000 a CYFLD_BLE_BLELL_SCAN_WINDOW__OFFSET
00000010 a CYFLD_BLE_BLELL_SCAN_WINDOW__SIZE
00000010 a CYFLD_BLE_BLELL_SCAN_WINDOW__SIZE
00000007 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET
00000007 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE
00000007 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET
00000007 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE
00000005 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET
00000005 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE
00000006 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET
00000006 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_CLOSE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_CLOSE_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_CLOSE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_CLOSE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_INT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_INT_EN__SIZE
00000004 a CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET
00000004 a CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE
00000003 a CYFLD_BLE_BLELL_SCN_RSP_TX_EN__OFFSET
00000003 a CYFLD_BLE_BLELL_SCN_RSP_TX_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_RSP_TX_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_RSP_TX_EN__SIZE
00000000 a CYFLD_BLE_BLELL_SCN_STRT_EN__OFFSET
00000000 a CYFLD_BLE_BLELL_SCN_STRT_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_STRT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_STRT_EN__SIZE
00000002 a CYFLD_BLE_BLELL_SCN_TX_EN__OFFSET
00000002 a CYFLD_BLE_BLELL_SCN_TX_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SCN_TX_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SCN_TX_EN__SIZE
00000008 a CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET
00000008 a CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE
00000002 a CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET
00000002 a CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE
0000000a a CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
0000000a a CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE
00000006 a CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET
00000006 a CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE
00000007 a CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET
00000007 a CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE
00000009 a CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET
00000009 a CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE
00000001 a CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE
00000007 a CYFLD_BLE_BLELL_SET_CLEAR__OFFSET
00000007 a CYFLD_BLE_BLELL_SET_CLEAR__OFFSET
00000001 a CYFLD_BLE_BLELL_SET_CLEAR__SIZE
00000001 a CYFLD_BLE_BLELL_SET_CLEAR__SIZE
00000000 a CYFLD_BLE_BLELL_SL_CONN_INTERVAL_VAL__OFFSET
00000000 a CYFLD_BLE_BLELL_SL_CONN_INTERVAL_VAL__OFFSET
00000010 a CYFLD_BLE_BLELL_SL_CONN_INTERVAL_VAL__SIZE
00000010 a CYFLD_BLE_BLELL_SL_CONN_INTERVAL_VAL__SIZE
00000001 a CYFLD_BLE_BLELL_SL_DSM_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SL_DSM_EN__OFFSET
00000001 a CYFLD_BLE_BLELL_SL_DSM_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SL_DSM_EN__SIZE
00000000 a CYFLD_BLE_BLELL_SLAVE_LATENCY__OFFSET
00000000 a CYFLD_BLE_BLELL_SLAVE_LATENCY__OFFSET
00000010 a CYFLD_BLE_BLELL_SLAVE_LATENCY__SIZE
00000010 a CYFLD_BLE_BLELL_SLAVE_LATENCY__SIZE
00000000 a CYFLD_BLE_BLELL_SLAVE_LATENCY_VAL__OFFSET
00000000 a CYFLD_BLE_BLELL_SLAVE_LATENCY_VAL__OFFSET
00000010 a CYFLD_BLE_BLELL_SLAVE_LATENCY_VAL__SIZE
00000010 a CYFLD_BLE_BLELL_SLAVE_LATENCY_VAL__SIZE
00000008 a CYFLD_BLE_BLELL_SLAVE_TIME_ADJ_VAL__OFFSET
00000008 a CYFLD_BLE_BLELL_SLAVE_TIME_ADJ_VAL__OFFSET
00000008 a CYFLD_BLE_BLELL_SLAVE_TIME_ADJ_VAL__SIZE
00000008 a CYFLD_BLE_BLELL_SLAVE_TIME_ADJ_VAL__SIZE
00000000 a CYFLD_BLE_BLELL_SLAVE_TIME_SET_VAL__OFFSET
00000000 a CYFLD_BLE_BLELL_SLAVE_TIME_SET_VAL__OFFSET
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00000001 a CYFLD_BLE_BLELL_SLEEP_MODE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SLEEP_MODE_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE
00000001 a CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE
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00000001 a CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_SLV_CONNECTED__SIZE
00000001 a CYFLD_BLE_BLELL_SLV_CONNECTED__SIZE
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00000001 a CYFLD_BLE_BLELL_SLV_CONNECTED_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SLV_CONNECTED_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_SLV_MD_CONFIG__SIZE
00000001 a CYFLD_BLE_BLELL_SLV_MD_CONFIG__SIZE
00000000 a CYFLD_BLE_BLELL_SLV_WIN_ADJ__OFFSET
00000000 a CYFLD_BLE_BLELL_SLV_WIN_ADJ__OFFSET
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00000001 a CYFLD_BLE_BLELL_SM_AUTO_WKUP_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SM_AUTO_WKUP_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_SM_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SM_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_SM_INTR__SIZE
00000001 a CYFLD_BLE_BLELL_SM_INTR__SIZE
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00000001 a CYFLD_BLE_BLELL_SM_INTR_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_START_CE__SIZE
00000001 a CYFLD_BLE_BLELL_START_CE__SIZE
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00000001 a CYFLD_BLE_BLELL_START_CE_INT_EN__SIZE
00000001 a CYFLD_BLE_BLELL_START_CE_INT_EN__SIZE
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00000001 a CYFLD_BLE_BLELL_START_PROC__SIZE
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00000000 a CYFLD_BLE_BLELL_SUPERVISION_TIMEOUT__OFFSET
00000000 a CYFLD_BLE_BLELL_SUPERVISION_TIMEOUT__OFFSET
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00000001 a CYFLD_BLE_BLELL_SYSCLK_GATE_EN__SIZE
00000001 a CYFLD_BLE_BLELL_SYSCLK_GATE_EN__SIZE
00000000 a CYFLD_BLE_BLELL_TEST_FREQUENCY__OFFSET
00000000 a CYFLD_BLE_BLELL_TEST_FREQUENCY__OFFSET
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00000000 a CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET
00000000 a CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET
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00000001 a CYFLD_BLE_BLELL_TEST_TYPE__SIZE
00000001 a CYFLD_BLE_BLELL_TEST_TYPE__SIZE
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00000000 a CYFLD_BLE_BLELL_TIM_REF_CLOCK__OFFSET
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00000001 a CYFLD_BLE_BLELL_TX_ACK_4__SIZE
00000001 a CYFLD_BLE_BLELL_TX_ACK_4__SIZE
00000000 a CYFLD_BLE_BLELL_TX_ADDR__OFFSET
00000000 a CYFLD_BLE_BLELL_TX_ADDR__OFFSET
00000001 a CYFLD_BLE_BLELL_TX_ADDR__SIZE
00000001 a CYFLD_BLE_BLELL_TX_ADDR__SIZE
0000000c a CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET
0000000c a CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET
00000001 a CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE
00000001 a CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE
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00000001 a CYFLD_BLE_BLELL_TX_SENT_4__SIZE
00000001 a CYFLD_BLE_BLELL_TX_SENT_4__SIZE
00000000 a CYFLD_BLE_BLELL_TX_WINDOW_OFFSET__OFFSET
00000000 a CYFLD_BLE_BLELL_TX_WINDOW_OFFSET__OFFSET
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00000000 a CYFLD_BLE_BLELL_TX_WINDOW_SIZE__OFFSET
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00000000 a CYFLD_BLE_BLELL_TXEN_EXT_DELAY__OFFSET
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00000001 a CYFLD_BLE_BLELL_VALID_ENTRY__SIZE
00000001 a CYFLD_BLE_BLELL_VALID_ENTRY__SIZE
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00000001 a CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE
00000001 a CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE
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00000000 a CYFLD_BLE_BLELL_WINDOW_WIDEN_INTVL__OFFSET
00000000 a CYFLD_BLE_BLELL_WINDOW_WIDEN_INTVL__OFFSET
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00000000 a CYFLD_BLE_BLELL_WINDOW_WIDEN_WINOFF__OFFSET
00000000 a CYFLD_BLE_BLELL_WINDOW_WIDEN_WINOFF__OFFSET
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00000000 a CYFLD_BLE_BLELL_WL_ADDR_TYPE__OFFSET
00000000 a CYFLD_BLE_BLELL_WL_ADDR_TYPE__OFFSET
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00000000 a CYFLD_BLE_BLELL_WL_BASE_ADDR__OFFSET
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00000000 a CYFLD_BLE_BLELL_WL_ENABLE__OFFSET
00000000 a CYFLD_BLE_BLELL_WL_ENABLE__OFFSET
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00000001 a CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE
00000001 a CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE
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00000000 a CYFLD_BLE_BLERD_ADC_1__OFFSET
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00000000 a CYFLD_BLE_BLERD_ADC_2__OFFSET
00000000 a CYFLD_BLE_BLERD_ADC_2__OFFSET
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00000000 a CYFLD_BLE_BLERD_ADC_3__OFFSET
00000000 a CYFLD_BLE_BLERD_ADC_3__OFFSET
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00000000 a CYFLD_BLE_BLERD_ADC_4__OFFSET
00000000 a CYFLD_BLE_BLERD_ADC_4__OFFSET
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00000001 a CYFLD_BLE_BLERD_ADC_DC_CAPTURE_EN__SIZE
00000001 a CYFLD_BLE_BLERD_ADC_DC_CAPTURE_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_ADC_DFT_EN__SIZE
00000001 a CYFLD_BLE_BLERD_ADC_DFT_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_ADC_FULL_SWING_DETECT_EN__SIZE
00000001 a CYFLD_BLE_BLERD_ADC_FULL_SWING_DETECT_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_ADC_FULL_SWING_MONI_EN__SIZE
00000001 a CYFLD_BLE_BLERD_ADC_FULL_SWING_MONI_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_ADC_IQ_INVERSE__SIZE
00000001 a CYFLD_BLE_BLERD_ADC_IQ_INVERSE__SIZE
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00000001 a CYFLD_BLE_BLERD_ADC_PWR_EST_EN__SIZE
00000001 a CYFLD_BLE_BLERD_ADC_PWR_EST_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_ADCDFT_SEL__SIZE
00000001 a CYFLD_BLE_BLERD_ADCDFT_SEL__SIZE
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00000001 a CYFLD_BLE_BLERD_AGC_DISABLE__SIZE
00000001 a CYFLD_BLE_BLERD_AGC_DISABLE__SIZE
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00000001 a CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE
00000001 a CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_BALUN_CTUNE__SIZE
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00000001 a CYFLD_BLE_BLERD_BALUN_HFLDO__SIZE
00000001 a CYFLD_BLE_BLERD_BALUN_HFLDO__SIZE
00000000 a CYFLD_BLE_BLERD_BB_BYPASS__OFFSET
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00000000 a CYFLD_BLE_BLERD_BB_FPUP_XO_BUF_ALL__OFFSET
00000000 a CYFLD_BLE_BLERD_BB_FPUP_XO_BUF_ALL__OFFSET
00000001 a CYFLD_BLE_BLERD_BB_FPUP_XO_BUF_ALL__SIZE
00000001 a CYFLD_BLE_BLERD_BB_FPUP_XO_BUF_ALL__SIZE
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00000001 a CYFLD_BLE_BLERD_BB_RCCAL_BLOCK__SIZE
00000001 a CYFLD_BLE_BLERD_BB_RCCAL_BLOCK__SIZE
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00000001 a CYFLD_BLE_BLERD_BB_XO_BUF_ADC__SIZE
00000001 a CYFLD_BLE_BLERD_BB_XO_BUF_ADC__SIZE
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00000001 a CYFLD_BLE_BLERD_BB_XO_BUF_SY__SIZE
00000001 a CYFLD_BLE_BLERD_BB_XO_BUF_SY__SIZE
00000000 a CYFLD_BLE_BLERD_BUMP_BALUM_HF__OFFSET
00000000 a CYFLD_BLE_BLERD_BUMP_BALUM_HF__OFFSET
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00000000 a CYFLD_BLE_BLERD_BUMP_RX_CTUNE__OFFSET
00000000 a CYFLD_BLE_BLERD_BUMP_RX_CTUNE__OFFSET
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00000001 a CYFLD_BLE_BLERD_BURNIN_CLK_EN__SIZE
00000001 a CYFLD_BLE_BLERD_BURNIN_CLK_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_CBPF_HIZ_ENABLE__SIZE
00000001 a CYFLD_BLE_BLERD_CBPF_HIZ_ENABLE__SIZE
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00000001 a CYFLD_BLE_BLERD_CHECK_SAT_EN__OFFSET
00000001 a CYFLD_BLE_BLERD_CHECK_SAT_EN__OFFSET
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00000001 a CYFLD_BLE_BLERD_RADIO_STANDALONE__SIZE
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00000001 a CYFLD_BLE_BLERD_RCCAL_RERUN__SIZE
00000001 a CYFLD_BLE_BLERD_RCCAL_RERUN__SIZE
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00000001 a CYFLD_BLE_BLERD_RD_RCCAL_DONE__SIZE
00000001 a CYFLD_BLE_BLERD_RD_RCCAL_DONE__SIZE
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00000001 a CYFLD_BLE_BLERD_READ_DC_OFFSET_SEL__SIZE
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00000001 a CYFLD_BLE_BLERD_RESET2_EN__SIZE
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00000001 a CYFLD_BLE_BLERD_RF_PLL_DIRECT__SIZE
00000001 a CYFLD_BLE_BLERD_RF_PLL_DIRECT__SIZE
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00000001 a CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE
00000001 a CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE
00000000 a CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET
00000000 a CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET
00000002 a CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE
00000002 a CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE
00000000 a CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET
00000000 a CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET
00000004 a CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE
00000004 a CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE
00000000 a CYFLD_TCPWM_CNT_CC__OFFSET
00000000 a CYFLD_TCPWM_CNT_CC__OFFSET
00000010 a CYFLD_TCPWM_CNT_CC__SIZE
00000010 a CYFLD_TCPWM_CNT_CC__SIZE
00000001 a CYFLD_TCPWM_CNT_CC_MATCH__OFFSET
00000001 a CYFLD_TCPWM_CNT_CC_MATCH__OFFSET
00000001 a CYFLD_TCPWM_CNT_CC_MATCH__SIZE
00000001 a CYFLD_TCPWM_CNT_CC_MATCH__SIZE
00000000 a CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET
00000000 a CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET
00000002 a CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE
00000002 a CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE
00000002 a CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET
00000002 a CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET
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00000002 a CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE
00000004 a CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET
00000004 a CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET
00000004 a CYFLD_TCPWM_CNT_COUNT_SEL__SIZE
00000004 a CYFLD_TCPWM_CNT_COUNT_SEL__SIZE
00000000 a CYFLD_TCPWM_CNT_COUNTER__OFFSET
00000000 a CYFLD_TCPWM_CNT_COUNTER__OFFSET
00000010 a CYFLD_TCPWM_CNT_COUNTER__SIZE
00000010 a CYFLD_TCPWM_CNT_COUNTER__SIZE
00000000 a CYFLD_TCPWM_CNT_DOWN__OFFSET
00000000 a CYFLD_TCPWM_CNT_DOWN__OFFSET
00000001 a CYFLD_TCPWM_CNT_DOWN__SIZE
00000001 a CYFLD_TCPWM_CNT_DOWN__SIZE
00000008 a CYFLD_TCPWM_CNT_GENERIC__OFFSET
00000008 a CYFLD_TCPWM_CNT_GENERIC__OFFSET
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00000003 a CYFLD_TCPWM_CNT_MODE__SIZE
00000003 a CYFLD_TCPWM_CNT_MODE__SIZE
00000012 a CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET
00000012 a CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET
00000001 a CYFLD_TCPWM_CNT_ONE_SHOT__SIZE
00000001 a CYFLD_TCPWM_CNT_ONE_SHOT__SIZE
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00000002 a CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET
00000002 a CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE
00000002 a CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE
00000000 a CYFLD_TCPWM_CNT_PERIOD__OFFSET
00000000 a CYFLD_TCPWM_CNT_PERIOD__OFFSET
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00000003 a CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET
00000003 a CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET
00000001 a CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE
00000001 a CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE
00000002 a CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET
00000002 a CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET
00000001 a CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE
00000001 a CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE
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00000014 a CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET
00000002 a CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE
00000002 a CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE
00000004 a CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET
00000004 a CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET
00000002 a CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE
00000002 a CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE
00000008 a CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET
00000008 a CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET
00000004 a CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE
00000004 a CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE
0000001f a CYFLD_TCPWM_CNT_RUNNING__OFFSET
0000001f a CYFLD_TCPWM_CNT_RUNNING__OFFSET
00000001 a CYFLD_TCPWM_CNT_RUNNING__SIZE
00000001 a CYFLD_TCPWM_CNT_RUNNING__SIZE
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00000010 a CYFLD_TCPWM_CNT_START_SEL__OFFSET
00000004 a CYFLD_TCPWM_CNT_START_SEL__SIZE
00000004 a CYFLD_TCPWM_CNT_START_SEL__SIZE
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00000006 a CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET
00000002 a CYFLD_TCPWM_CNT_STOP_EDGE__SIZE
00000002 a CYFLD_TCPWM_CNT_STOP_EDGE__SIZE
0000000c a CYFLD_TCPWM_CNT_STOP_SEL__OFFSET
0000000c a CYFLD_TCPWM_CNT_STOP_SEL__OFFSET
00000004 a CYFLD_TCPWM_CNT_STOP_SEL__SIZE
00000004 a CYFLD_TCPWM_CNT_STOP_SEL__SIZE
00000000 a CYFLD_TCPWM_CNT_TC__OFFSET
00000000 a CYFLD_TCPWM_CNT_TC__OFFSET
00000001 a CYFLD_TCPWM_CNT_TC__SIZE
00000001 a CYFLD_TCPWM_CNT_TC__SIZE
00000004 a CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET
00000004 a CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET
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00000010 a CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET
00000002 a CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE
00000002 a CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE
00000000 a CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET
00000000 a CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET
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00000004 a CYFLD_TCPWM_COUNTER_CAPTURE__SIZE
00000000 a CYFLD_TCPWM_COUNTER_ENABLED__OFFSET
00000000 a CYFLD_TCPWM_COUNTER_ENABLED__OFFSET
00000004 a CYFLD_TCPWM_COUNTER_ENABLED__SIZE
00000004 a CYFLD_TCPWM_COUNTER_ENABLED__SIZE
00000000 a CYFLD_TCPWM_COUNTER_INT__OFFSET
00000000 a CYFLD_TCPWM_COUNTER_INT__OFFSET
00000004 a CYFLD_TCPWM_COUNTER_INT__SIZE
00000004 a CYFLD_TCPWM_COUNTER_INT__SIZE
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00000008 a CYFLD_TCPWM_COUNTER_RELOAD__OFFSET
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00000010 a CYFLD_TCPWM_COUNTER_STOP__OFFSET
00000010 a CYFLD_TCPWM_COUNTER_STOP__OFFSET
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00000004 a CYFLD_TCPWM_COUNTER_STOP__SIZE
00000000 a CYFLD_TST_ADFT_MUX_SEL_0A__OFFSET
00000000 a CYFLD_TST_ADFT_MUX_SEL_0A__OFFSET
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00000000 a CYFLD_TST_COUNTER__OFFSET
00000000 a CYFLD_TST_COUNTER__OFFSET
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0000001f a CYFLD_TST_COUNTER_DONE__OFFSET
0000001f a CYFLD_TST_COUNTER_DONE__OFFSET
00000001 a CYFLD_TST_COUNTER_DONE__SIZE
00000001 a CYFLD_TST_COUNTER_DONE__SIZE
00000000 a CYFLD_TST_DFT_SEL0__OFFSET
00000000 a CYFLD_TST_DFT_SEL0__OFFSET
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00000001 a CYFLD_TST_ENABLE__SIZE
00000001 a CYFLD_TST_ENABLE__SIZE
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00000001 a CYFLD_TST_POR_BYPASS__SIZE
00000001 a CYFLD_TST_POR_BYPASS__SIZE
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00000001 a CYFLD_TST_SCAN_MODE__SIZE
00000001 a CYFLD_TST_SCAN_MODE__SIZE
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00000001 a CYFLD_TST_SWD_CONNECTED__SIZE
00000001 a CYFLD_TST_SWD_CONNECTED__SIZE
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00000001 a CYFLD_TST_TEST_MODE__SIZE
00000001 a CYFLD_TST_TEST_MODE__SIZE
00000000 a CYFLD_UDB_BCTL0_BCEN__OFFSET
00000000 a CYFLD_UDB_BCTL0_BCEN__OFFSET
00000001 a CYFLD_UDB_BCTL0_BCEN__SIZE
00000001 a CYFLD_UDB_BCTL0_BCEN__SIZE
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00000001 a CYFLD_UDB_BCTL0_BCEN_Q__SIZE
00000001 a CYFLD_UDB_BCTL0_BCEN_Q__SIZE
00000000 a CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET
00000000 a CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET
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00000000 a CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET
00000000 a CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET
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00000000 a CYFLD_UDB_BCTL0_DCEN__OFFSET
00000000 a CYFLD_UDB_BCTL0_DCEN__OFFSET
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00000000 a CYFLD_UDB_BCTL0_DCEN_Q__OFFSET
00000000 a CYFLD_UDB_BCTL0_DCEN_Q__OFFSET
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00000001 a CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE
00000001 a CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE
00000000 a CYFLD_UDB_BCTL0_DRV__OFFSET
00000000 a CYFLD_UDB_BCTL0_DRV__OFFSET
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0000000a a CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET
00000001 a CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE
00000001 a CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE
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00000001 a CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE
00000001 a CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE
0000000c a CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET
0000000c a CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET
00000001 a CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE
00000001 a CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE
0000000e a CYFLD_UDB_BCTL0_NC0__OFFSET
0000000e a CYFLD_UDB_BCTL0_NC0__OFFSET
00000001 a CYFLD_UDB_BCTL0_NC0__SIZE
00000001 a CYFLD_UDB_BCTL0_NC0__SIZE
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00000001 a CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE
00000001 a CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE
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00000001 a CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE
00000001 a CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE
00000000 a CYFLD_UDB_CAT16_A0__OFFSET
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00000001 a CYFLD_UDB_CAT16_CNT_START__SIZE
00000001 a CYFLD_UDB_CAT16_CNT_START__SIZE
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00000001 a CYFLD_UDB_CAT16_FIFO0_CLR__SIZE
00000001 a CYFLD_UDB_CAT16_FIFO0_CLR__SIZE
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00000001 a CYFLD_UDB_CAT16_FIFO0_LVL__SIZE
00000001 a CYFLD_UDB_CAT16_FIFO0_LVL__SIZE
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00000001 a CYFLD_UDB_CAT16_FIFO1_CLR__SIZE
00000001 a CYFLD_UDB_CAT16_FIFO1_CLR__SIZE
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00000001 a CYFLD_UDB_CAT16_FIFO1_LVL__SIZE
00000001 a CYFLD_UDB_CAT16_FIFO1_LVL__SIZE
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00000001 a CYFLD_UDB_CAT16_INT_EN__SIZE
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00000000 a CYFLD_UDB_CAT16_ST__OFFSET
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00000000 a CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET
00000000 a CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE
00000000 a CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET
00000000 a CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE
00000000 a CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET
00000000 a CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE
00000003 a CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET
00000003 a CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE
00000003 a CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET
00000003 a CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE
00000004 a CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET
00000004 a CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE
00000004 a CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET
00000004 a CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE
00000005 a CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET
00000005 a CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE
00000005 a CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET
00000005 a CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE
00000004 a CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET
00000004 a CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE
00000004 a CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET
00000004 a CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE
00000006 a CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET
00000006 a CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE
00000006 a CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET
00000006 a CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE
00000007 a CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET
00000007 a CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE
00000007 a CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET
00000007 a CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE
00000006 a CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET
00000006 a CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE
00000006 a CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET
00000006 a CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE
00000000 a CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET
00000000 a CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE
00000002 a CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET
00000002 a CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE
00000003 a CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET
00000003 a CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE
00000004 a CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET
00000004 a CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE
00000005 a CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET
00000005 a CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE
00000006 a CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET
00000006 a CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE
00000007 a CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET
00000007 a CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE
00000006 a CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET
00000006 a CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD0_RES_POL__SIZE
00000001 a CYFLD_UDB_P_U_PLD0_RES_POL__SIZE
00000004 a CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET
00000004 a CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET
00000004 a CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE
00000004 a CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE
00000008 a CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET
00000008 a CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE
00000009 a CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET
00000009 a CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE
0000000a a CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET
0000000a a CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE
0000000b a CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET
0000000b a CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE
0000000c a CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET
0000000c a CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE
0000000d a CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET
0000000d a CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE
0000000e a CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET
0000000e a CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE
0000000f a CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET
0000000f a CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE
00000018 a CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET
00000018 a CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE
00000019 a CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET
00000019 a CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE
0000001a a CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET
0000001a a CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE
0000001b a CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET
0000001b a CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE
0000001c a CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET
0000001c a CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE
0000001d a CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET
0000001d a CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE
0000001e a CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET
0000001e a CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE
0000001f a CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET
0000001f a CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE
00000008 a CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET
00000008 a CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE
00000008 a CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET
00000008 a CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE
00000009 a CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET
00000009 a CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE
00000009 a CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET
00000009 a CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE
00000008 a CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET
00000008 a CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE
00000008 a CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET
00000008 a CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE
0000000a a CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET
0000000a a CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE
0000000a a CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET
0000000a a CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE
0000000b a CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET
0000000b a CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE
0000000b a CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET
0000000b a CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE
0000000a a CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET
0000000a a CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE
0000000a a CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET
0000000a a CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE
0000000c a CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET
0000000c a CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE
0000000c a CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET
0000000c a CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE
0000000d a CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET
0000000d a CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE
0000000d a CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET
0000000d a CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE
0000000c a CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET
0000000c a CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE
0000000c a CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET
0000000c a CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE
0000000e a CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET
0000000e a CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE
0000000e a CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET
0000000e a CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE
0000000f a CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET
0000000f a CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE
0000000f a CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET
0000000f a CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE
0000000e a CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET
0000000e a CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE
0000000e a CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET
0000000e a CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET
00000002 a CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE
00000002 a CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE
00000008 a CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET
00000008 a CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE
00000009 a CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET
00000009 a CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE
0000000a a CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET
0000000a a CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE
0000000b a CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET
0000000b a CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE
0000000c a CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET
0000000c a CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE
0000000d a CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET
0000000d a CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE
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00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE
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00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE
00000001 a CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE
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00000001 a CYFLD_UDB_P_U_PLD1_RES_POL__SIZE
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00000000 a CYFLD_UDB_P_U_RAD2__OFFSET
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00000001 a CYFLD_UDB_P_U_RC_EN_INV__SIZE
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00000001 a CYFLD_UDB_P_U_RC_INV__SIZE
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00000001 a CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE
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00000001 a CYFLD_UDB_P_U_RC_RES_SEL1__SIZE
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00000001 a CYFLD_UDB_P_U_ROUTE_EN__SIZE
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00000001 a CYFLD_UDB_P_U_ROUTE_LD__SIZE
00000001 a CYFLD_UDB_P_U_ROUTE_LD__SIZE
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00000001 a CYFLD_UDB_P_U_SC_EXT_RES__SIZE
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00000001 a CYFLD_UDB_P_U_SC_INT_MD__SIZE
00000001 a CYFLD_UDB_P_U_SC_INT_MD__SIZE
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00000001 a CYFLD_UDB_P_U_SC_RES_POL__SIZE
00000001 a CYFLD_UDB_P_U_SC_RES_POL__SIZE
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00000001 a CYFLD_UDB_P_U_SC_SYNC_MD__SIZE
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00000001 a CYFLD_UDB_P_U_SHIFT_SEL__SIZE
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00000000 a CYFLD_UDB_P_U_SI_MUX__OFFSET
00000000 a CYFLD_UDB_P_U_SI_MUX__OFFSET
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00000001 a CYFLD_UDB_P_U_SRC_A__SIZE
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00000001 a CYFLD_UDB_P_U_WRK16_CONCAT__SIZE
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402e1f18 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE2
402e1f18 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE2
402e1f1c a CYREG_BLE_BLELL_RSLV_LIST_ENABLE3
402e1f1c a CYREG_BLE_BLELL_RSLV_LIST_ENABLE3
402e1f20 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE4
402e1f20 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE4
402e1f24 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE5
402e1f24 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE5
402e1f28 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE6
402e1f28 a CYREG_BLE_BLELL_RSLV_LIST_ENABLE6
402e1f2c a CYREG_BLE_BLELL_RSLV_LIST_ENABLE7
402e1f2c a CYREG_BLE_BLELL_RSLV_LIST_ENABLE7
402e2000 a CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR
402e2000 a CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR
402e2060 a CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR
402e2060 a CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR
402e20c0 a CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR
402e20c0 a CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR
402e2120 a CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR
402e2120 a CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR
402e11d8 a CYREG_BLE_BLELL_SCAN_CONFIG
402e11d8 a CYREG_BLE_BLELL_SCAN_CONFIG
402e1028 a CYREG_BLE_BLELL_SCAN_INTERVAL
402e1028 a CYREG_BLE_BLELL_SCAN_INTERVAL
402e1038 a CYREG_BLE_BLELL_SCAN_INTR
402e1038 a CYREG_BLE_BLELL_SCAN_INTR
402e103c a CYREG_BLE_BLELL_SCAN_NEXT_INSTANT
402e103c a CYREG_BLE_BLELL_SCAN_NEXT_INSTANT
402e1030 a CYREG_BLE_BLELL_SCAN_PARAM
402e1030 a CYREG_BLE_BLELL_SCAN_PARAM
402e102c a CYREG_BLE_BLELL_SCAN_WINDOW
402e102c a CYREG_BLE_BLELL_SCAN_WINDOW
402e1a1c a CYREG_BLE_BLELL_SL_CONN_INTERVAL
402e1a1c a CYREG_BLE_BLELL_SL_CONN_INTERVAL
402e1108 a CYREG_BLE_BLELL_SLAVE_LATENCY
402e1108 a CYREG_BLE_BLELL_SLAVE_LATENCY
402e11f4 a CYREG_BLE_BLELL_SLAVE_TIMING_CONTROL
402e11f4 a CYREG_BLE_BLELL_SLAVE_TIMING_CONTROL
402e1a18 a CYREG_BLE_BLELL_SLV_WIN_ADJ
402e1a18 a CYREG_BLE_BLELL_SLV_WIN_ADJ
402e1104 a CYREG_BLE_BLELL_SUP_TIMEOUT
402e1104 a CYREG_BLE_BLELL_SUP_TIMEOUT
402e10c8 a CYREG_BLE_BLELL_TIM_COUNTER_L
402e10c8 a CYREG_BLE_BLELL_TIM_COUNTER_L
402e1080 a CYREG_BLE_BLELL_TRANSMIT_WINDOW_OFFSET
402e1080 a CYREG_BLE_BLELL_TRANSMIT_WINDOW_OFFSET
402e1084 a CYREG_BLE_BLELL_TRANSMIT_WINDOW_SIZE
402e1084 a CYREG_BLE_BLELL_TRANSMIT_WINDOW_SIZE
402e1e00 a CYREG_BLE_BLELL_TX_EN_EXT_DELAY
402e1e00 a CYREG_BLE_BLELL_TX_EN_EXT_DELAY
402e1190 a CYREG_BLE_BLELL_TX_RX_ON_DELAY
402e1190 a CYREG_BLE_BLELL_TX_RX_ON_DELAY
402e1e04 a CYREG_BLE_BLELL_TX_RX_SYNTH_DELAY
402e1e04 a CYREG_BLE_BLELL_TX_RX_SYNTH_DELAY
402e1188 a CYREG_BLE_BLELL_TXRX_HOP
402e1188 a CYREG_BLE_BLELL_TXRX_HOP
402e10b8 a CYREG_BLE_BLELL_WAKEUP_CONFIG
402e10b8 a CYREG_BLE_BLELL_WAKEUP_CONFIG
402e10c0 a CYREG_BLE_BLELL_WAKEUP_CONTROL
402e10c0 a CYREG_BLE_BLELL_WAKEUP_CONTROL
402e1340 a CYREG_BLE_BLELL_WHITELIST_BASE_ADDR
402e1340 a CYREG_BLE_BLELL_WHITELIST_BASE_ADDR
402e1a14 a CYREG_BLE_BLELL_WIN_MIN_STEP_SIZE
402e1a14 a CYREG_BLE_BLELL_WIN_MIN_STEP_SIZE
402e1160 a CYREG_BLE_BLELL_WINDOW_WIDEN_INTVL
402e1160 a CYREG_BLE_BLELL_WINDOW_WIDEN_INTVL
402e1164 a CYREG_BLE_BLELL_WINDOW_WIDEN_WINOFF
402e1164 a CYREG_BLE_BLELL_WINDOW_WIDEN_WINOFF
402e1078 a CYREG_BLE_BLELL_WL_ADDR_TYPE
402e1078 a CYREG_BLE_BLELL_WL_ADDR_TYPE
402e107c a CYREG_BLE_BLELL_WL_ENABLE
402e107c a CYREG_BLE_BLELL_WL_ENABLE
402e0098 a CYREG_BLE_BLERD_ADC_BUMP1
402e0098 a CYREG_BLE_BLERD_ADC_BUMP1
402e009c a CYREG_BLE_BLERD_ADC_BUMP2
402e009c a CYREG_BLE_BLERD_ADC_BUMP2
402e00a8 a CYREG_BLE_BLERD_AGC
402e00a8 a CYREG_BLE_BLERD_AGC
402e0180 a CYREG_BLE_BLERD_AGC_GAIN_COMP_1
402e0180 a CYREG_BLE_BLERD_AGC_GAIN_COMP_1
402e0184 a CYREG_BLE_BLERD_AGC_GAIN_COMP_2
402e0184 a CYREG_BLE_BLERD_AGC_GAIN_COMP_2
402e00a0 a CYREG_BLE_BLERD_BALUN
402e00a0 a CYREG_BLE_BLERD_BALUN
402e0070 a CYREG_BLE_BLERD_BB_BUMP1
402e0070 a CYREG_BLE_BLERD_BB_BUMP1
402e0074 a CYREG_BLE_BLERD_BB_BUMP2
402e0074 a CYREG_BLE_BLERD_BB_BUMP2
402e0078 a CYREG_BLE_BLERD_BB_XO
402e0078 a CYREG_BLE_BLERD_BB_XO
402e007c a CYREG_BLE_BLERD_BB_XO_CAPTRIM
402e007c a CYREG_BLE_BLERD_BB_XO_CAPTRIM
402e002c a CYREG_BLE_BLERD_CFG_1_FCAL
402e002c a CYREG_BLE_BLERD_CFG_1_FCAL
402e0030 a CYREG_BLE_BLERD_CFG_2_FCAL
402e0030 a CYREG_BLE_BLERD_CFG_2_FCAL
402e0034 a CYREG_BLE_BLERD_CFG_3_FCAL
402e0034 a CYREG_BLE_BLERD_CFG_3_FCAL
402e0038 a CYREG_BLE_BLERD_CFG_4_FCAL
402e0038 a CYREG_BLE_BLERD_CFG_4_FCAL
402e003c a CYREG_BLE_BLERD_CFG_5_FCAL
402e003c a CYREG_BLE_BLERD_CFG_5_FCAL
402e0040 a CYREG_BLE_BLERD_CFG_6_FCAL
402e0040 a CYREG_BLE_BLERD_CFG_6_FCAL
402e0000 a CYREG_BLE_BLERD_CFG1
402e0000 a CYREG_BLE_BLERD_CFG1
402e0004 a CYREG_BLE_BLERD_CFG2
402e0004 a CYREG_BLE_BLERD_CFG2
402e0014 a CYREG_BLE_BLERD_CFGCTRL
402e0014 a CYREG_BLE_BLERD_CFGCTRL
402e00a4 a CYREG_BLE_BLERD_CTR1
402e00a4 a CYREG_BLE_BLERD_CTR1
402e00f0 a CYREG_BLE_BLERD_DBG_1
402e00f0 a CYREG_BLE_BLERD_DBG_1
402e00f4 a CYREG_BLE_BLERD_DBG_2
402e00f4 a CYREG_BLE_BLERD_DBG_2
402e00f8 a CYREG_BLE_BLERD_DBG_3
402e00f8 a CYREG_BLE_BLERD_DBG_3
402e00ec a CYREG_BLE_BLERD_DBG_BB
402e00ec a CYREG_BLE_BLERD_DBG_BB
402e0010 a CYREG_BLE_BLERD_DBUS
402e0010 a CYREG_BLE_BLERD_DBUS
402e00c0 a CYREG_BLE_BLERD_DC
402e00c0 a CYREG_BLE_BLERD_DC
402e00c8 a CYREG_BLE_BLERD_DCCAL
402e00c8 a CYREG_BLE_BLERD_DCCAL
402e0060 a CYREG_BLE_BLERD_DIAG1
402e0060 a CYREG_BLE_BLERD_DIAG1
402e00d0 a CYREG_BLE_BLERD_DSM1
402e00d0 a CYREG_BLE_BLERD_DSM1
402e00d4 a CYREG_BLE_BLERD_DSM2
402e00d4 a CYREG_BLE_BLERD_DSM2
402e00d8 a CYREG_BLE_BLERD_DSM3
402e00d8 a CYREG_BLE_BLERD_DSM3
402e00dc a CYREG_BLE_BLERD_DSM4
402e00dc a CYREG_BLE_BLERD_DSM4
402e00e0 a CYREG_BLE_BLERD_DSM5
402e00e0 a CYREG_BLE_BLERD_DSM5
402e00e4 a CYREG_BLE_BLERD_DSM6
402e00e4 a CYREG_BLE_BLERD_DSM6
402e0044 a CYREG_BLE_BLERD_FCAL_TEST
402e0044 a CYREG_BLE_BLERD_FCAL_TEST
402e004c a CYREG_BLE_BLERD_FPD_TEST
402e004c a CYREG_BLE_BLERD_FPD_TEST
402e000c a CYREG_BLE_BLERD_FSM
402e000c a CYREG_BLE_BLERD_FSM
402e0064 a CYREG_BLE_BLERD_IM
402e0064 a CYREG_BLE_BLERD_IM
402e00c4 a CYREG_BLE_BLERD_IQMIS
402e00c4 a CYREG_BLE_BLERD_IQMIS
402e0028 a CYREG_BLE_BLERD_KVCAL
402e0028 a CYREG_BLE_BLERD_KVCAL
402e006c a CYREG_BLE_BLERD_LDO
402e006c a CYREG_BLE_BLERD_LDO
402e0068 a CYREG_BLE_BLERD_LDO_BYPASS
402e0068 a CYREG_BLE_BLERD_LDO_BYPASS
402e0008 a CYREG_BLE_BLERD_MODEM
402e0008 a CYREG_BLE_BLERD_MODEM
402e00e8 a CYREG_BLE_BLERD_MONI
402e00e8 a CYREG_BLE_BLERD_MONI
402e0188 a CYREG_BLE_BLERD_PA_RSSI_NEW
402e0188 a CYREG_BLE_BLERD_PA_RSSI_NEW
402e00cc a CYREG_BLE_BLERD_RCCAL
402e00cc a CYREG_BLE_BLERD_RCCAL
402e0100 a CYREG_BLE_BLERD_READ_IQ_1
402e0100 a CYREG_BLE_BLERD_READ_IQ_1
402e0104 a CYREG_BLE_BLERD_READ_IQ_2
402e0104 a CYREG_BLE_BLERD_READ_IQ_2
402e0108 a CYREG_BLE_BLERD_READ_IQ_3
402e0108 a CYREG_BLE_BLERD_READ_IQ_3
402e010c a CYREG_BLE_BLERD_READ_IQ_4
402e010c a CYREG_BLE_BLERD_READ_IQ_4
402e0024 a CYREG_BLE_BLERD_RMAP
402e0024 a CYREG_BLE_BLERD_RMAP
402e0018 a CYREG_BLE_BLERD_RSSI
402e0018 a CYREG_BLE_BLERD_RSSI
402e005c a CYREG_BLE_BLERD_RX
402e005c a CYREG_BLE_BLERD_RX
402e0090 a CYREG_BLE_BLERD_RX_BUMP1
402e0090 a CYREG_BLE_BLERD_RX_BUMP1
402e0094 a CYREG_BLE_BLERD_RX_BUMP2
402e0094 a CYREG_BLE_BLERD_RX_BUMP2
402e0050 a CYREG_BLE_BLERD_SY
402e0050 a CYREG_BLE_BLERD_SY
402e0080 a CYREG_BLE_BLERD_SY_BUMP1
402e0080 a CYREG_BLE_BLERD_SY_BUMP1
402e0084 a CYREG_BLE_BLERD_SY_BUMP2
402e0084 a CYREG_BLE_BLERD_SY_BUMP2
402e0048 a CYREG_BLE_BLERD_TEST
402e0048 a CYREG_BLE_BLERD_TEST
402e0054 a CYREG_BLE_BLERD_TEST2_SY
402e0054 a CYREG_BLE_BLERD_TEST2_SY
402e00ac a CYREG_BLE_BLERD_THRSHD1
402e00ac a CYREG_BLE_BLERD_THRSHD1
402e00b0 a CYREG_BLE_BLERD_THRSHD2
402e00b0 a CYREG_BLE_BLERD_THRSHD2
402e00b4 a CYREG_BLE_BLERD_THRSHD3
402e00b4 a CYREG_BLE_BLERD_THRSHD3
402e00b8 a CYREG_BLE_BLERD_THRSHD4
402e00b8 a CYREG_BLE_BLERD_THRSHD4
402e00bc a CYREG_BLE_BLERD_THRSHD5
402e00bc a CYREG_BLE_BLERD_THRSHD5
402e0058 a CYREG_BLE_BLERD_TX
402e0058 a CYREG_BLE_BLERD_TX
402e0088 a CYREG_BLE_BLERD_TX_BUMP1
402e0088 a CYREG_BLE_BLERD_TX_BUMP1
402e008c a CYREG_BLE_BLERD_TX_BUMP2
402e008c a CYREG_BLE_BLERD_TX_BUMP2
402ef074 a CYREG_BLE_BLESS_LF_CLK_CTRL
402ef074 a CYREG_BLE_BLESS_LF_CLK_CTRL
402ef070 a CYREG_BLE_BLESS_LL_CLK_EN
402ef070 a CYREG_BLE_BLESS_LL_CLK_EN
402ef06c a CYREG_BLE_BLESS_LL_DSM_CTRL
402ef06c a CYREG_BLE_BLESS_LL_DSM_CTRL
402ef068 a CYREG_BLE_BLESS_LL_DSM_INTR_STAT
402ef068 a CYREG_BLE_BLESS_LL_DSM_INTR_STAT
402ef060 a CYREG_BLE_BLESS_RF_CONFIG
402ef060 a CYREG_BLE_BLESS_RF_CONFIG
402ef000 a CYREG_BLE_BLESS_WCO_CONFIG
402ef000 a CYREG_BLE_BLESS_WCO_CONFIG
402ef004 a CYREG_BLE_BLESS_WCO_STATUS
402ef004 a CYREG_BLE_BLESS_WCO_STATUS
402eff00 a CYREG_BLE_BLESS_WCO_TRIM
402eff00 a CYREG_BLE_BLESS_WCO_TRIM
402ef064 a CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG
402ef064 a CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG
400b0110 a CYREG_CLK_DFT_SELECT
400b0110 a CYREG_CLK_DFT_SELECT
400b0104 a CYREG_CLK_ILO_CONFIG
400b0104 a CYREG_CLK_ILO_CONFIG
400bff24 a CYREG_CLK_ILO_TRIM
400bff24 a CYREG_CLK_ILO_TRIM
400b0108 a CYREG_CLK_IMO_CONFIG
400b0108 a CYREG_CLK_IMO_CONFIG
400b010c a CYREG_CLK_IMO_SPREAD
400b010c a CYREG_CLK_IMO_SPREAD
400bff28 a CYREG_CLK_IMO_TRIM1
400bff28 a CYREG_CLK_IMO_TRIM1
400bff2c a CYREG_CLK_IMO_TRIM2
400bff2c a CYREG_CLK_IMO_TRIM2
400bff30 a CYREG_CLK_IMO_TRIM3
400bff30 a CYREG_CLK_IMO_TRIM3
400bff34 a CYREG_CLK_IMO_TRIM4
400bff34 a CYREG_CLK_IMO_TRIM4
400b0100 a CYREG_CLK_SELECT
400b0100 a CYREG_CLK_SELECT
e000ed0c a CYREG_CM0_AIRCR
e000ed0c a CYREG_CM0_AIRCR
e0002ff0 a CYREG_CM0_BP_CID0
e0002ff0 a CYREG_CM0_BP_CID0
e0002ff4 a CYREG_CM0_BP_CID1
e0002ff4 a CYREG_CM0_BP_CID1
e0002ff8 a CYREG_CM0_BP_CID2
e0002ff8 a CYREG_CM0_BP_CID2
e0002ffc a CYREG_CM0_BP_CID3
e0002ffc a CYREG_CM0_BP_CID3
e0002fe0 a CYREG_CM0_BP_PID0
e0002fe0 a CYREG_CM0_BP_PID0
e0002fe4 a CYREG_CM0_BP_PID1
e0002fe4 a CYREG_CM0_BP_PID1
e0002fe8 a CYREG_CM0_BP_PID2
e0002fe8 a CYREG_CM0_BP_PID2
e0002fec a CYREG_CM0_BP_PID3
e0002fec a CYREG_CM0_BP_PID3
e0002fd0 a CYREG_CM0_BP_PID4
e0002fd0 a CYREG_CM0_BP_PID4
e000ed14 a CYREG_CM0_CCR
e000ed14 a CYREG_CM0_CCR
e000ed00 a CYREG_CM0_CPUID
e000ed00 a CYREG_CM0_CPUID
e0001ff0 a CYREG_CM0_DWT_CID0
e0001ff0 a CYREG_CM0_DWT_CID0
e0001ff4 a CYREG_CM0_DWT_CID1
e0001ff4 a CYREG_CM0_DWT_CID1
e0001ff8 a CYREG_CM0_DWT_CID2
e0001ff8 a CYREG_CM0_DWT_CID2
e0001ffc a CYREG_CM0_DWT_CID3
e0001ffc a CYREG_CM0_DWT_CID3
e0001fe0 a CYREG_CM0_DWT_PID0
e0001fe0 a CYREG_CM0_DWT_PID0
e0001fe4 a CYREG_CM0_DWT_PID1
e0001fe4 a CYREG_CM0_DWT_PID1
e0001fe8 a CYREG_CM0_DWT_PID2
e0001fe8 a CYREG_CM0_DWT_PID2
e0001fec a CYREG_CM0_DWT_PID3
e0001fec a CYREG_CM0_DWT_PID3
e0001fd0 a CYREG_CM0_DWT_PID4
e0001fd0 a CYREG_CM0_DWT_PID4
e000e180 a CYREG_CM0_ICER
e000e180 a CYREG_CM0_ICER
e000e280 a CYREG_CM0_ICPR
e000e280 a CYREG_CM0_ICPR
e000ed04 a CYREG_CM0_ICSR
e000ed04 a CYREG_CM0_ICSR
e000e400 a CYREG_CM0_IPR0
e000e400 a CYREG_CM0_IPR0
e000e404 a CYREG_CM0_IPR1
e000e404 a CYREG_CM0_IPR1
e000e408 a CYREG_CM0_IPR2
e000e408 a CYREG_CM0_IPR2
e000e40c a CYREG_CM0_IPR3
e000e40c a CYREG_CM0_IPR3
e000e410 a CYREG_CM0_IPR4
e000e410 a CYREG_CM0_IPR4
e000e414 a CYREG_CM0_IPR5
e000e414 a CYREG_CM0_IPR5
e000e418 a CYREG_CM0_IPR6
e000e418 a CYREG_CM0_IPR6
e000e41c a CYREG_CM0_IPR7
e000e41c a CYREG_CM0_IPR7
e000e100 a CYREG_CM0_ISER
e000e100 a CYREG_CM0_ISER
e000e200 a CYREG_CM0_ISPR
e000e200 a CYREG_CM0_ISPR
e00ff008 a CYREG_CM0_ROM_BPU
e00ff008 a CYREG_CM0_ROM_BPU
e00ffff0 a CYREG_CM0_ROM_CID0
e00ffff0 a CYREG_CM0_ROM_CID0
e00ffff4 a CYREG_CM0_ROM_CID1
e00ffff4 a CYREG_CM0_ROM_CID1
e00ffff8 a CYREG_CM0_ROM_CID2
e00ffff8 a CYREG_CM0_ROM_CID2
e00ffffc a CYREG_CM0_ROM_CID3
e00ffffc a CYREG_CM0_ROM_CID3
e00fffcc a CYREG_CM0_ROM_CSMT
e00fffcc a CYREG_CM0_ROM_CSMT
e00ff004 a CYREG_CM0_ROM_DWT
e00ff004 a CYREG_CM0_ROM_DWT
e00ff00c a CYREG_CM0_ROM_END
e00ff00c a CYREG_CM0_ROM_END
e00fffe0 a CYREG_CM0_ROM_PID0
e00fffe0 a CYREG_CM0_ROM_PID0
e00fffe4 a CYREG_CM0_ROM_PID1
e00fffe4 a CYREG_CM0_ROM_PID1
e00fffe8 a CYREG_CM0_ROM_PID2
e00fffe8 a CYREG_CM0_ROM_PID2
e00fffec a CYREG_CM0_ROM_PID3
e00fffec a CYREG_CM0_ROM_PID3
e00fffd0 a CYREG_CM0_ROM_PID4
e00fffd0 a CYREG_CM0_ROM_PID4
e00ff000 a CYREG_CM0_ROM_SCS
e00ff000 a CYREG_CM0_ROM_SCS
e000ed10 a CYREG_CM0_SCR
e000ed10 a CYREG_CM0_SCR
e000eff0 a CYREG_CM0_SCS_CID0
e000eff0 a CYREG_CM0_SCS_CID0
e000eff4 a CYREG_CM0_SCS_CID1
e000eff4 a CYREG_CM0_SCS_CID1
e000eff8 a CYREG_CM0_SCS_CID2
e000eff8 a CYREG_CM0_SCS_CID2
e000effc a CYREG_CM0_SCS_CID3
e000effc a CYREG_CM0_SCS_CID3
e000efe0 a CYREG_CM0_SCS_PID0
e000efe0 a CYREG_CM0_SCS_PID0
e000efe4 a CYREG_CM0_SCS_PID1
e000efe4 a CYREG_CM0_SCS_PID1
e000efe8 a CYREG_CM0_SCS_PID2
e000efe8 a CYREG_CM0_SCS_PID2
e000efec a CYREG_CM0_SCS_PID3
e000efec a CYREG_CM0_SCS_PID3
e000efd0 a CYREG_CM0_SCS_PID4
e000efd0 a CYREG_CM0_SCS_PID4
e000ed24 a CYREG_CM0_SHCSR
e000ed24 a CYREG_CM0_SHCSR
e000ed1c a CYREG_CM0_SHPR2
e000ed1c a CYREG_CM0_SHPR2
e000ed20 a CYREG_CM0_SHPR3
e000ed20 a CYREG_CM0_SHPR3
e000e01c a CYREG_CM0_SYST_CALIB
e000e01c a CYREG_CM0_SYST_CALIB
e000e010 a CYREG_CM0_SYST_CSR
e000e010 a CYREG_CM0_SYST_CSR
e000e018 a CYREG_CM0_SYST_CVR
e000e018 a CYREG_CM0_SYST_CVR
e000e014 a CYREG_CM0_SYST_RVR
e000e014 a CYREG_CM0_SYST_RVR
40100000 a CYREG_CPUSS_CONFIG
40100000 a CYREG_CPUSS_CONFIG
4010003c a CYREG_CPUSS_DMAC_CTL
4010003c a CYREG_CPUSS_DMAC_CTL
40100030 a CYREG_CPUSS_FLASH_CTL
40100030 a CYREG_CPUSS_FLASH_CTL
40100024 a CYREG_CPUSS_INT_MODE
40100024 a CYREG_CPUSS_INT_MODE
40100020 a CYREG_CPUSS_INT_SEL
40100020 a CYREG_CPUSS_INT_SEL
40100028 a CYREG_CPUSS_NMI_MODE
40100028 a CYREG_CPUSS_NMI_MODE
40100018 a CYREG_CPUSS_PRIV_FLASH
40100018 a CYREG_CPUSS_PRIV_FLASH
40100014 a CYREG_CPUSS_PRIV_RAM
40100014 a CYREG_CPUSS_PRIV_RAM
40100010 a CYREG_CPUSS_PRIV_ROM
40100010 a CYREG_CPUSS_PRIV_ROM
4010000c a CYREG_CPUSS_PROTECTION
4010000c a CYREG_CPUSS_PROTECTION
40100038 a CYREG_CPUSS_RAM_CTL
40100038 a CYREG_CPUSS_RAM_CTL
40100034 a CYREG_CPUSS_ROM_CTL
40100034 a CYREG_CPUSS_ROM_CTL
40100100 a CYREG_CPUSS_SL_CTL0
40100100 a CYREG_CPUSS_SL_CTL0
40100104 a CYREG_CPUSS_SL_CTL1
40100104 a CYREG_CPUSS_SL_CTL1
40100108 a CYREG_CPUSS_SL_CTL2
40100108 a CYREG_CPUSS_SL_CTL2
40100008 a CYREG_CPUSS_SYSARG
40100008 a CYREG_CPUSS_SYSARG
40100004 a CYREG_CPUSS_SYSREQ
40100004 a CYREG_CPUSS_SYSREQ
4010001c a CYREG_CPUSS_WOUNDING
4010001c a CYREG_CPUSS_WOUNDING
40280004 a CYREG_CSD_CONFIG
40280004 a CYREG_CSD_CONFIG
4028000c a CYREG_CSD_COUNTER
4028000c a CYREG_CSD_COUNTER
40280000 a CYREG_CSD_ID
40280000 a CYREG_CSD_ID
40280008 a CYREG_CSD_IDAC
40280008 a CYREG_CSD_IDAC
40280014 a CYREG_CSD_INTR
40280014 a CYREG_CSD_INTR
40280018 a CYREG_CSD_INTR_SET
40280018 a CYREG_CSD_INTR_SET
4028001c a CYREG_CSD_PWM
4028001c a CYREG_CSD_PWM
40280010 a CYREG_CSD_STATUS
40280010 a CYREG_CSD_STATUS
4028ff00 a CYREG_CSD_TRIM1
4028ff00 a CYREG_CSD_TRIM1
4028ff04 a CYREG_CSD_TRIM2
4028ff04 a CYREG_CSD_TRIM2
4030000c a CYREG_CTBM0_COMP_STAT
4030000c a CYREG_CTBM0_COMP_STAT
40300000 a CYREG_CTBM0_CTB_CTRL
40300000 a CYREG_CTBM0_CTB_CTRL
403000c0 a CYREG_CTBM0_CTB_SW_HW_CTRL
403000c0 a CYREG_CTBM0_CTB_SW_HW_CTRL
403000c4 a CYREG_CTBM0_CTB_SW_STATUS
403000c4 a CYREG_CTBM0_CTB_SW_STATUS
40300030 a CYREG_CTBM0_DFT_CTRL
40300030 a CYREG_CTBM0_DFT_CTRL
40300020 a CYREG_CTBM0_INTR
40300020 a CYREG_CTBM0_INTR
40300028 a CYREG_CTBM0_INTR_MASK
40300028 a CYREG_CTBM0_INTR_MASK
4030002c a CYREG_CTBM0_INTR_MASKED
4030002c a CYREG_CTBM0_INTR_MASKED
40300024 a CYREG_CTBM0_INTR_SET
40300024 a CYREG_CTBM0_INTR_SET
40300004 a CYREG_CTBM0_OA_RES0_CTRL
40300004 a CYREG_CTBM0_OA_RES0_CTRL
40300008 a CYREG_CTBM0_OA_RES1_CTRL
40300008 a CYREG_CTBM0_OA_RES1_CTRL
40300f08 a CYREG_CTBM0_OA0_COMP_TRIM
40300f08 a CYREG_CTBM0_OA0_COMP_TRIM
40300f00 a CYREG_CTBM0_OA0_OFFSET_TRIM
40300f00 a CYREG_CTBM0_OA0_OFFSET_TRIM
40300f04 a CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM
40300f04 a CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM
40300080 a CYREG_CTBM0_OA0_SW
40300080 a CYREG_CTBM0_OA0_SW
40300084 a CYREG_CTBM0_OA0_SW_CLEAR
40300084 a CYREG_CTBM0_OA0_SW_CLEAR
40300f14 a CYREG_CTBM0_OA1_COMP_TRIM
40300f14 a CYREG_CTBM0_OA1_COMP_TRIM
40300f0c a CYREG_CTBM0_OA1_OFFSET_TRIM
40300f0c a CYREG_CTBM0_OA1_OFFSET_TRIM
40300f10 a CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM
40300f10 a CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM
40300088 a CYREG_CTBM0_OA1_SW
40300088 a CYREG_CTBM0_OA1_SW
4030008c a CYREG_CTBM0_OA1_SW_CLEAR
4030008c a CYREG_CTBM0_OA1_SW_CLEAR
4031000c a CYREG_CTBM1_COMP_STAT
4031000c a CYREG_CTBM1_COMP_STAT
40310000 a CYREG_CTBM1_CTB_CTRL
40310000 a CYREG_CTBM1_CTB_CTRL
403100c0 a CYREG_CTBM1_CTB_SW_HW_CTRL
403100c0 a CYREG_CTBM1_CTB_SW_HW_CTRL
403100c4 a CYREG_CTBM1_CTB_SW_STATUS
403100c4 a CYREG_CTBM1_CTB_SW_STATUS
40310030 a CYREG_CTBM1_DFT_CTRL
40310030 a CYREG_CTBM1_DFT_CTRL
40310020 a CYREG_CTBM1_INTR
40310020 a CYREG_CTBM1_INTR
40310028 a CYREG_CTBM1_INTR_MASK
40310028 a CYREG_CTBM1_INTR_MASK
4031002c a CYREG_CTBM1_INTR_MASKED
4031002c a CYREG_CTBM1_INTR_MASKED
40310024 a CYREG_CTBM1_INTR_SET
40310024 a CYREG_CTBM1_INTR_SET
40310004 a CYREG_CTBM1_OA_RES0_CTRL
40310004 a CYREG_CTBM1_OA_RES0_CTRL
40310008 a CYREG_CTBM1_OA_RES1_CTRL
40310008 a CYREG_CTBM1_OA_RES1_CTRL
40310f08 a CYREG_CTBM1_OA0_COMP_TRIM
40310f08 a CYREG_CTBM1_OA0_COMP_TRIM
40310f00 a CYREG_CTBM1_OA0_OFFSET_TRIM
40310f00 a CYREG_CTBM1_OA0_OFFSET_TRIM
40310f04 a CYREG_CTBM1_OA0_SLOPE_OFFSET_TRIM
40310f04 a CYREG_CTBM1_OA0_SLOPE_OFFSET_TRIM
40310080 a CYREG_CTBM1_OA0_SW
40310080 a CYREG_CTBM1_OA0_SW
40310084 a CYREG_CTBM1_OA0_SW_CLEAR
40310084 a CYREG_CTBM1_OA0_SW_CLEAR
40310f14 a CYREG_CTBM1_OA1_COMP_TRIM
40310f14 a CYREG_CTBM1_OA1_COMP_TRIM
40310f0c a CYREG_CTBM1_OA1_OFFSET_TRIM
40310f0c a CYREG_CTBM1_OA1_OFFSET_TRIM
40310f10 a CYREG_CTBM1_OA1_SLOPE_OFFSET_TRIM
40310f10 a CYREG_CTBM1_OA1_SLOPE_OFFSET_TRIM
40310088 a CYREG_CTBM1_OA1_SW
40310088 a CYREG_CTBM1_OA1_SW
4031008c a CYREG_CTBM1_OA1_SW_CLEAR
4031008c a CYREG_CTBM1_OA1_SW_CLEAR
40101080 a CYREG_DMAC_CH_CTL0
40101080 a CYREG_DMAC_CH_CTL0
40101084 a CYREG_DMAC_CH_CTL1
40101084 a CYREG_DMAC_CH_CTL1
40101088 a CYREG_DMAC_CH_CTL2
40101088 a CYREG_DMAC_CH_CTL2
4010108c a CYREG_DMAC_CH_CTL3
4010108c a CYREG_DMAC_CH_CTL3
40101090 a CYREG_DMAC_CH_CTL4
40101090 a CYREG_DMAC_CH_CTL4
40101094 a CYREG_DMAC_CH_CTL5
40101094 a CYREG_DMAC_CH_CTL5
40101098 a CYREG_DMAC_CH_CTL6
40101098 a CYREG_DMAC_CH_CTL6
4010109c a CYREG_DMAC_CH_CTL7
4010109c a CYREG_DMAC_CH_CTL7
40101000 a CYREG_DMAC_CTL
40101000 a CYREG_DMAC_CTL
40101808 a CYREG_DMAC_DESCR0_PING_CTL
40101808 a CYREG_DMAC_DESCR0_PING_CTL
40101804 a CYREG_DMAC_DESCR0_PING_DST
40101804 a CYREG_DMAC_DESCR0_PING_DST
40101800 a CYREG_DMAC_DESCR0_PING_SRC
40101800 a CYREG_DMAC_DESCR0_PING_SRC
4010180c a CYREG_DMAC_DESCR0_PING_STATUS
4010180c a CYREG_DMAC_DESCR0_PING_STATUS
40101818 a CYREG_DMAC_DESCR0_PONG_CTL
40101818 a CYREG_DMAC_DESCR0_PONG_CTL
40101814 a CYREG_DMAC_DESCR0_PONG_DST
40101814 a CYREG_DMAC_DESCR0_PONG_DST
40101810 a CYREG_DMAC_DESCR0_PONG_SRC
40101810 a CYREG_DMAC_DESCR0_PONG_SRC
4010181c a CYREG_DMAC_DESCR0_PONG_STATUS
4010181c a CYREG_DMAC_DESCR0_PONG_STATUS
40101828 a CYREG_DMAC_DESCR1_PING_CTL
40101828 a CYREG_DMAC_DESCR1_PING_CTL
40101824 a CYREG_DMAC_DESCR1_PING_DST
40101824 a CYREG_DMAC_DESCR1_PING_DST
40101820 a CYREG_DMAC_DESCR1_PING_SRC
40101820 a CYREG_DMAC_DESCR1_PING_SRC
4010182c a CYREG_DMAC_DESCR1_PING_STATUS
4010182c a CYREG_DMAC_DESCR1_PING_STATUS
40101838 a CYREG_DMAC_DESCR1_PONG_CTL
40101838 a CYREG_DMAC_DESCR1_PONG_CTL
40101834 a CYREG_DMAC_DESCR1_PONG_DST
40101834 a CYREG_DMAC_DESCR1_PONG_DST
40101830 a CYREG_DMAC_DESCR1_PONG_SRC
40101830 a CYREG_DMAC_DESCR1_PONG_SRC
4010183c a CYREG_DMAC_DESCR1_PONG_STATUS
4010183c a CYREG_DMAC_DESCR1_PONG_STATUS
40101848 a CYREG_DMAC_DESCR2_PING_CTL
40101848 a CYREG_DMAC_DESCR2_PING_CTL
40101844 a CYREG_DMAC_DESCR2_PING_DST
40101844 a CYREG_DMAC_DESCR2_PING_DST
40101840 a CYREG_DMAC_DESCR2_PING_SRC
40101840 a CYREG_DMAC_DESCR2_PING_SRC
4010184c a CYREG_DMAC_DESCR2_PING_STATUS
4010184c a CYREG_DMAC_DESCR2_PING_STATUS
40101858 a CYREG_DMAC_DESCR2_PONG_CTL
40101858 a CYREG_DMAC_DESCR2_PONG_CTL
40101854 a CYREG_DMAC_DESCR2_PONG_DST
40101854 a CYREG_DMAC_DESCR2_PONG_DST
40101850 a CYREG_DMAC_DESCR2_PONG_SRC
40101850 a CYREG_DMAC_DESCR2_PONG_SRC
4010185c a CYREG_DMAC_DESCR2_PONG_STATUS
4010185c a CYREG_DMAC_DESCR2_PONG_STATUS
40101868 a CYREG_DMAC_DESCR3_PING_CTL
40101868 a CYREG_DMAC_DESCR3_PING_CTL
40101864 a CYREG_DMAC_DESCR3_PING_DST
40101864 a CYREG_DMAC_DESCR3_PING_DST
40101860 a CYREG_DMAC_DESCR3_PING_SRC
40101860 a CYREG_DMAC_DESCR3_PING_SRC
4010186c a CYREG_DMAC_DESCR3_PING_STATUS
4010186c a CYREG_DMAC_DESCR3_PING_STATUS
40101878 a CYREG_DMAC_DESCR3_PONG_CTL
40101878 a CYREG_DMAC_DESCR3_PONG_CTL
40101874 a CYREG_DMAC_DESCR3_PONG_DST
40101874 a CYREG_DMAC_DESCR3_PONG_DST
40101870 a CYREG_DMAC_DESCR3_PONG_SRC
40101870 a CYREG_DMAC_DESCR3_PONG_SRC
4010187c a CYREG_DMAC_DESCR3_PONG_STATUS
4010187c a CYREG_DMAC_DESCR3_PONG_STATUS
40101888 a CYREG_DMAC_DESCR4_PING_CTL
40101888 a CYREG_DMAC_DESCR4_PING_CTL
40101884 a CYREG_DMAC_DESCR4_PING_DST
40101884 a CYREG_DMAC_DESCR4_PING_DST
40101880 a CYREG_DMAC_DESCR4_PING_SRC
40101880 a CYREG_DMAC_DESCR4_PING_SRC
4010188c a CYREG_DMAC_DESCR4_PING_STATUS
4010188c a CYREG_DMAC_DESCR4_PING_STATUS
40101898 a CYREG_DMAC_DESCR4_PONG_CTL
40101898 a CYREG_DMAC_DESCR4_PONG_CTL
40101894 a CYREG_DMAC_DESCR4_PONG_DST
40101894 a CYREG_DMAC_DESCR4_PONG_DST
40101890 a CYREG_DMAC_DESCR4_PONG_SRC
40101890 a CYREG_DMAC_DESCR4_PONG_SRC
4010189c a CYREG_DMAC_DESCR4_PONG_STATUS
4010189c a CYREG_DMAC_DESCR4_PONG_STATUS
401018a8 a CYREG_DMAC_DESCR5_PING_CTL
401018a8 a CYREG_DMAC_DESCR5_PING_CTL
401018a4 a CYREG_DMAC_DESCR5_PING_DST
401018a4 a CYREG_DMAC_DESCR5_PING_DST
401018a0 a CYREG_DMAC_DESCR5_PING_SRC
401018a0 a CYREG_DMAC_DESCR5_PING_SRC
401018ac a CYREG_DMAC_DESCR5_PING_STATUS
401018ac a CYREG_DMAC_DESCR5_PING_STATUS
401018b8 a CYREG_DMAC_DESCR5_PONG_CTL
401018b8 a CYREG_DMAC_DESCR5_PONG_CTL
401018b4 a CYREG_DMAC_DESCR5_PONG_DST
401018b4 a CYREG_DMAC_DESCR5_PONG_DST
401018b0 a CYREG_DMAC_DESCR5_PONG_SRC
401018b0 a CYREG_DMAC_DESCR5_PONG_SRC
401018bc a CYREG_DMAC_DESCR5_PONG_STATUS
401018bc a CYREG_DMAC_DESCR5_PONG_STATUS
401018c8 a CYREG_DMAC_DESCR6_PING_CTL
401018c8 a CYREG_DMAC_DESCR6_PING_CTL
401018c4 a CYREG_DMAC_DESCR6_PING_DST
401018c4 a CYREG_DMAC_DESCR6_PING_DST
401018c0 a CYREG_DMAC_DESCR6_PING_SRC
401018c0 a CYREG_DMAC_DESCR6_PING_SRC
401018cc a CYREG_DMAC_DESCR6_PING_STATUS
401018cc a CYREG_DMAC_DESCR6_PING_STATUS
401018d8 a CYREG_DMAC_DESCR6_PONG_CTL
401018d8 a CYREG_DMAC_DESCR6_PONG_CTL
401018d4 a CYREG_DMAC_DESCR6_PONG_DST
401018d4 a CYREG_DMAC_DESCR6_PONG_DST
401018d0 a CYREG_DMAC_DESCR6_PONG_SRC
401018d0 a CYREG_DMAC_DESCR6_PONG_SRC
401018dc a CYREG_DMAC_DESCR6_PONG_STATUS
401018dc a CYREG_DMAC_DESCR6_PONG_STATUS
401018e8 a CYREG_DMAC_DESCR7_PING_CTL
401018e8 a CYREG_DMAC_DESCR7_PING_CTL
401018e4 a CYREG_DMAC_DESCR7_PING_DST
401018e4 a CYREG_DMAC_DESCR7_PING_DST
401018e0 a CYREG_DMAC_DESCR7_PING_SRC
401018e0 a CYREG_DMAC_DESCR7_PING_SRC
401018ec a CYREG_DMAC_DESCR7_PING_STATUS
401018ec a CYREG_DMAC_DESCR7_PING_STATUS
401018f8 a CYREG_DMAC_DESCR7_PONG_CTL
401018f8 a CYREG_DMAC_DESCR7_PONG_CTL
401018f4 a CYREG_DMAC_DESCR7_PONG_DST
401018f4 a CYREG_DMAC_DESCR7_PONG_DST
401018f0 a CYREG_DMAC_DESCR7_PONG_SRC
401018f0 a CYREG_DMAC_DESCR7_PONG_SRC
401018fc a CYREG_DMAC_DESCR7_PONG_STATUS
401018fc a CYREG_DMAC_DESCR7_PONG_STATUS
401017f0 a CYREG_DMAC_INTR
401017f0 a CYREG_DMAC_INTR
401017f8 a CYREG_DMAC_INTR_MASK
401017f8 a CYREG_DMAC_INTR_MASK
401017fc a CYREG_DMAC_INTR_MASKED
401017fc a CYREG_DMAC_INTR_MASKED
401017f4 a CYREG_DMAC_INTR_SET
401017f4 a CYREG_DMAC_INTR_SET
40101010 a CYREG_DMAC_STATUS
40101010 a CYREG_DMAC_STATUS
4010101c a CYREG_DMAC_STATUS_CH_ACT
4010101c a CYREG_DMAC_STATUS_CH_ACT
40101018 a CYREG_DMAC_STATUS_DST_ADDR
40101018 a CYREG_DMAC_STATUS_DST_ADDR
40101014 a CYREG_DMAC_STATUS_SRC_ADDR
40101014 a CYREG_DMAC_STATUS_SRC_ADDR
00000000 a CYREG_FLASH_DATA_MBASE
00000000 a CYREG_FLASH_DATA_MBASE
00040000 a CYREG_FLASH_DATA_MSIZE
00040000 a CYREG_FLASH_DATA_MSIZE
40041000 a CYREG_GPIO_INTR_CAUSE
40041000 a CYREG_GPIO_INTR_CAUSE
40040000 a CYREG_GPIO_PRT0_DR
40040000 a CYREG_GPIO_PRT0_DR
40040044 a CYREG_GPIO_PRT0_DR_CLR
40040044 a CYREG_GPIO_PRT0_DR_CLR
40040048 a CYREG_GPIO_PRT0_DR_INV
40040048 a CYREG_GPIO_PRT0_DR_INV
40040040 a CYREG_GPIO_PRT0_DR_SET
40040040 a CYREG_GPIO_PRT0_DR_SET
40040010 a CYREG_GPIO_PRT0_INTR
40040010 a CYREG_GPIO_PRT0_INTR
4004000c a CYREG_GPIO_PRT0_INTR_CFG
4004000c a CYREG_GPIO_PRT0_INTR_CFG
40040008 a CYREG_GPIO_PRT0_PC
40040008 a CYREG_GPIO_PRT0_PC
40040018 a CYREG_GPIO_PRT0_PC2
40040018 a CYREG_GPIO_PRT0_PC2
40040004 a CYREG_GPIO_PRT0_PS
40040004 a CYREG_GPIO_PRT0_PS
40040100 a CYREG_GPIO_PRT1_DR
40040100 a CYREG_GPIO_PRT1_DR
40040144 a CYREG_GPIO_PRT1_DR_CLR
40040144 a CYREG_GPIO_PRT1_DR_CLR
40040148 a CYREG_GPIO_PRT1_DR_INV
40040148 a CYREG_GPIO_PRT1_DR_INV
40040140 a CYREG_GPIO_PRT1_DR_SET
40040140 a CYREG_GPIO_PRT1_DR_SET
40040110 a CYREG_GPIO_PRT1_INTR
40040110 a CYREG_GPIO_PRT1_INTR
4004010c a CYREG_GPIO_PRT1_INTR_CFG
4004010c a CYREG_GPIO_PRT1_INTR_CFG
40040108 a CYREG_GPIO_PRT1_PC
40040108 a CYREG_GPIO_PRT1_PC
40040118 a CYREG_GPIO_PRT1_PC2
40040118 a CYREG_GPIO_PRT1_PC2
40040104 a CYREG_GPIO_PRT1_PS
40040104 a CYREG_GPIO_PRT1_PS
40040200 a CYREG_GPIO_PRT2_DR
40040200 a CYREG_GPIO_PRT2_DR
40040244 a CYREG_GPIO_PRT2_DR_CLR
40040244 a CYREG_GPIO_PRT2_DR_CLR
40040248 a CYREG_GPIO_PRT2_DR_INV
40040248 a CYREG_GPIO_PRT2_DR_INV
40040240 a CYREG_GPIO_PRT2_DR_SET
40040240 a CYREG_GPIO_PRT2_DR_SET
40040210 a CYREG_GPIO_PRT2_INTR
40040210 a CYREG_GPIO_PRT2_INTR
4004020c a CYREG_GPIO_PRT2_INTR_CFG
4004020c a CYREG_GPIO_PRT2_INTR_CFG
40040208 a CYREG_GPIO_PRT2_PC
40040208 a CYREG_GPIO_PRT2_PC
40040218 a CYREG_GPIO_PRT2_PC2
40040218 a CYREG_GPIO_PRT2_PC2
40040204 a CYREG_GPIO_PRT2_PS
40040204 a CYREG_GPIO_PRT2_PS
40040300 a CYREG_GPIO_PRT3_DR
40040300 a CYREG_GPIO_PRT3_DR
40040344 a CYREG_GPIO_PRT3_DR_CLR
40040344 a CYREG_GPIO_PRT3_DR_CLR
40040348 a CYREG_GPIO_PRT3_DR_INV
40040348 a CYREG_GPIO_PRT3_DR_INV
40040340 a CYREG_GPIO_PRT3_DR_SET
40040340 a CYREG_GPIO_PRT3_DR_SET
40040310 a CYREG_GPIO_PRT3_INTR
40040310 a CYREG_GPIO_PRT3_INTR
4004030c a CYREG_GPIO_PRT3_INTR_CFG
4004030c a CYREG_GPIO_PRT3_INTR_CFG
40040308 a CYREG_GPIO_PRT3_PC
40040308 a CYREG_GPIO_PRT3_PC
40040318 a CYREG_GPIO_PRT3_PC2
40040318 a CYREG_GPIO_PRT3_PC2
40040304 a CYREG_GPIO_PRT3_PS
40040304 a CYREG_GPIO_PRT3_PS
40040400 a CYREG_GPIO_PRT4_DR
40040400 a CYREG_GPIO_PRT4_DR
40040444 a CYREG_GPIO_PRT4_DR_CLR
40040444 a CYREG_GPIO_PRT4_DR_CLR
40040448 a CYREG_GPIO_PRT4_DR_INV
40040448 a CYREG_GPIO_PRT4_DR_INV
40040440 a CYREG_GPIO_PRT4_DR_SET
40040440 a CYREG_GPIO_PRT4_DR_SET
40040410 a CYREG_GPIO_PRT4_INTR
40040410 a CYREG_GPIO_PRT4_INTR
4004040c a CYREG_GPIO_PRT4_INTR_CFG
4004040c a CYREG_GPIO_PRT4_INTR_CFG
40040408 a CYREG_GPIO_PRT4_PC
40040408 a CYREG_GPIO_PRT4_PC
40040418 a CYREG_GPIO_PRT4_PC2
40040418 a CYREG_GPIO_PRT4_PC2
40040404 a CYREG_GPIO_PRT4_PS
40040404 a CYREG_GPIO_PRT4_PS
40040500 a CYREG_GPIO_PRT5_DR
40040500 a CYREG_GPIO_PRT5_DR
40040544 a CYREG_GPIO_PRT5_DR_CLR
40040544 a CYREG_GPIO_PRT5_DR_CLR
40040548 a CYREG_GPIO_PRT5_DR_INV
40040548 a CYREG_GPIO_PRT5_DR_INV
40040540 a CYREG_GPIO_PRT5_DR_SET
40040540 a CYREG_GPIO_PRT5_DR_SET
40040510 a CYREG_GPIO_PRT5_INTR
40040510 a CYREG_GPIO_PRT5_INTR
4004050c a CYREG_GPIO_PRT5_INTR_CFG
4004050c a CYREG_GPIO_PRT5_INTR_CFG
40040508 a CYREG_GPIO_PRT5_PC
40040508 a CYREG_GPIO_PRT5_PC
40040518 a CYREG_GPIO_PRT5_PC2
40040518 a CYREG_GPIO_PRT5_PC2
40040504 a CYREG_GPIO_PRT5_PS
40040504 a CYREG_GPIO_PRT5_PS
40040600 a CYREG_GPIO_PRT6_DR
40040600 a CYREG_GPIO_PRT6_DR
40040644 a CYREG_GPIO_PRT6_DR_CLR
40040644 a CYREG_GPIO_PRT6_DR_CLR
40040648 a CYREG_GPIO_PRT6_DR_INV
40040648 a CYREG_GPIO_PRT6_DR_INV
40040640 a CYREG_GPIO_PRT6_DR_SET
40040640 a CYREG_GPIO_PRT6_DR_SET
40040610 a CYREG_GPIO_PRT6_INTR
40040610 a CYREG_GPIO_PRT6_INTR
4004060c a CYREG_GPIO_PRT6_INTR_CFG
4004060c a CYREG_GPIO_PRT6_INTR_CFG
40040608 a CYREG_GPIO_PRT6_PC
40040608 a CYREG_GPIO_PRT6_PC
40040618 a CYREG_GPIO_PRT6_PC2
40040618 a CYREG_GPIO_PRT6_PC2
40040604 a CYREG_GPIO_PRT6_PS
40040604 a CYREG_GPIO_PRT6_PS
40022100 a CYREG_HSIOM_AMUX_SPLIT_CTL0
40022100 a CYREG_HSIOM_AMUX_SPLIT_CTL0
40022104 a CYREG_HSIOM_AMUX_SPLIT_CTL1
40022104 a CYREG_HSIOM_AMUX_SPLIT_CTL1
40022108 a CYREG_HSIOM_AMUX_SPLIT_CTL2
40022108 a CYREG_HSIOM_AMUX_SPLIT_CTL2
40020000 a CYREG_HSIOM_PORT_SEL0
40020000 a CYREG_HSIOM_PORT_SEL0
40020100 a CYREG_HSIOM_PORT_SEL1
40020100 a CYREG_HSIOM_PORT_SEL1
40020200 a CYREG_HSIOM_PORT_SEL2
40020200 a CYREG_HSIOM_PORT_SEL2
40020300 a CYREG_HSIOM_PORT_SEL3
40020300 a CYREG_HSIOM_PORT_SEL3
40020400 a CYREG_HSIOM_PORT_SEL4
40020400 a CYREG_HSIOM_PORT_SEL4
40020500 a CYREG_HSIOM_PORT_SEL5
40020500 a CYREG_HSIOM_PORT_SEL5
40020600 a CYREG_HSIOM_PORT_SEL6
40020600 a CYREG_HSIOM_PORT_SEL6
402a0008 a CYREG_LCD_CONTROL
402a0008 a CYREG_LCD_CONTROL
402a0100 a CYREG_LCD_DATA00
402a0100 a CYREG_LCD_DATA00
402a0104 a CYREG_LCD_DATA01
402a0104 a CYREG_LCD_DATA01
402a0108 a CYREG_LCD_DATA02
402a0108 a CYREG_LCD_DATA02
402a010c a CYREG_LCD_DATA03
402a010c a CYREG_LCD_DATA03
402a0110 a CYREG_LCD_DATA04
402a0110 a CYREG_LCD_DATA04
402a0004 a CYREG_LCD_DIVIDER
402a0004 a CYREG_LCD_DIVIDER
402a0000 a CYREG_LCD_ID
402a0000 a CYREG_LCD_ID
402b0004 a CYREG_LPCOMP_CONFIG
402b0004 a CYREG_LPCOMP_CONFIG
402b0008 a CYREG_LPCOMP_DFT
402b0008 a CYREG_LPCOMP_DFT
402b0000 a CYREG_LPCOMP_ID
402b0000 a CYREG_LPCOMP_ID
402b0010 a CYREG_LPCOMP_INTR
402b0010 a CYREG_LPCOMP_INTR
402b0018 a CYREG_LPCOMP_INTR_MASK
402b0018 a CYREG_LPCOMP_INTR_MASK
402b001c a CYREG_LPCOMP_INTR_MASKED
402b001c a CYREG_LPCOMP_INTR_MASKED
402b0014 a CYREG_LPCOMP_INTR_SET
402b0014 a CYREG_LPCOMP_INTR_SET
402bff00 a CYREG_LPCOMP_TRIM1
402bff00 a CYREG_LPCOMP_TRIM1
402bff04 a CYREG_LPCOMP_TRIM2
402bff04 a CYREG_LPCOMP_TRIM2
402bff08 a CYREG_LPCOMP_TRIM3
402bff08 a CYREG_LPCOMP_TRIM3
402bff0c a CYREG_LPCOMP_TRIM4
402bff0c a CYREG_LPCOMP_TRIM4
403f0030 a CYREG_PASS_DFT_CTRL
403f0030 a CYREG_PASS_DFT_CTRL
403f0e00 a CYREG_PASS_DSAB_DSAB_CTRL
403f0e00 a CYREG_PASS_DSAB_DSAB_CTRL
403f0e04 a CYREG_PASS_DSAB_DSAB_DFT
403f0e04 a CYREG_PASS_DSAB_DSAB_DFT
403f0f00 a CYREG_PASS_DSAB_TRIM
403f0f00 a CYREG_PASS_DSAB_TRIM
403f0000 a CYREG_PASS_INTR_CAUSE
403f0000 a CYREG_PASS_INTR_CAUSE
40010400 a CYREG_PERI_DIV_16_5_CTL0
40010400 a CYREG_PERI_DIV_16_5_CTL0
40010400 a CYREG_PERI_DIV_16_5_CTL00
40010400 a CYREG_PERI_DIV_16_5_CTL00
40010404 a CYREG_PERI_DIV_16_5_CTL01
40010404 a CYREG_PERI_DIV_16_5_CTL01
40010404 a CYREG_PERI_DIV_16_5_CTL1
40010404 a CYREG_PERI_DIV_16_5_CTL1
40010300 a CYREG_PERI_DIV_16_CTL0
40010300 a CYREG_PERI_DIV_16_CTL0
40010300 a CYREG_PERI_DIV_16_CTL00
40010300 a CYREG_PERI_DIV_16_CTL00
40010304 a CYREG_PERI_DIV_16_CTL01
40010304 a CYREG_PERI_DIV_16_CTL01
40010308 a CYREG_PERI_DIV_16_CTL02
40010308 a CYREG_PERI_DIV_16_CTL02
4001030c a CYREG_PERI_DIV_16_CTL03
4001030c a CYREG_PERI_DIV_16_CTL03
40010310 a CYREG_PERI_DIV_16_CTL04
40010310 a CYREG_PERI_DIV_16_CTL04
40010314 a CYREG_PERI_DIV_16_CTL05
40010314 a CYREG_PERI_DIV_16_CTL05
40010318 a CYREG_PERI_DIV_16_CTL06
40010318 a CYREG_PERI_DIV_16_CTL06
4001031c a CYREG_PERI_DIV_16_CTL07
4001031c a CYREG_PERI_DIV_16_CTL07
40010320 a CYREG_PERI_DIV_16_CTL08
40010320 a CYREG_PERI_DIV_16_CTL08
40010324 a CYREG_PERI_DIV_16_CTL09
40010324 a CYREG_PERI_DIV_16_CTL09
40010304 a CYREG_PERI_DIV_16_CTL1
40010304 a CYREG_PERI_DIV_16_CTL1
40010308 a CYREG_PERI_DIV_16_CTL2
40010308 a CYREG_PERI_DIV_16_CTL2
4001030c a CYREG_PERI_DIV_16_CTL3
4001030c a CYREG_PERI_DIV_16_CTL3
40010310 a CYREG_PERI_DIV_16_CTL4
40010310 a CYREG_PERI_DIV_16_CTL4
40010314 a CYREG_PERI_DIV_16_CTL5
40010314 a CYREG_PERI_DIV_16_CTL5
40010318 a CYREG_PERI_DIV_16_CTL6
40010318 a CYREG_PERI_DIV_16_CTL6
4001031c a CYREG_PERI_DIV_16_CTL7
4001031c a CYREG_PERI_DIV_16_CTL7
40010320 a CYREG_PERI_DIV_16_CTL8
40010320 a CYREG_PERI_DIV_16_CTL8
40010324 a CYREG_PERI_DIV_16_CTL9
40010324 a CYREG_PERI_DIV_16_CTL9
40010000 a CYREG_PERI_DIV_CMD
40010000 a CYREG_PERI_DIV_CMD
40010100 a CYREG_PERI_PCLK_CTL0
40010100 a CYREG_PERI_PCLK_CTL0
40010100 a CYREG_PERI_PCLK_CTL00
40010100 a CYREG_PERI_PCLK_CTL00
40010104 a CYREG_PERI_PCLK_CTL01
40010104 a CYREG_PERI_PCLK_CTL01
40010108 a CYREG_PERI_PCLK_CTL02
40010108 a CYREG_PERI_PCLK_CTL02
4001010c a CYREG_PERI_PCLK_CTL03
4001010c a CYREG_PERI_PCLK_CTL03
40010110 a CYREG_PERI_PCLK_CTL04
40010110 a CYREG_PERI_PCLK_CTL04
40010114 a CYREG_PERI_PCLK_CTL05
40010114 a CYREG_PERI_PCLK_CTL05
40010118 a CYREG_PERI_PCLK_CTL06
40010118 a CYREG_PERI_PCLK_CTL06
4001011c a CYREG_PERI_PCLK_CTL07
4001011c a CYREG_PERI_PCLK_CTL07
40010120 a CYREG_PERI_PCLK_CTL08
40010120 a CYREG_PERI_PCLK_CTL08
40010124 a CYREG_PERI_PCLK_CTL09
40010124 a CYREG_PERI_PCLK_CTL09
40010104 a CYREG_PERI_PCLK_CTL1
40010104 a CYREG_PERI_PCLK_CTL1
40010128 a CYREG_PERI_PCLK_CTL10
40010128 a CYREG_PERI_PCLK_CTL10
4001012c a CYREG_PERI_PCLK_CTL11
4001012c a CYREG_PERI_PCLK_CTL11
40010130 a CYREG_PERI_PCLK_CTL12
40010130 a CYREG_PERI_PCLK_CTL12
40010134 a CYREG_PERI_PCLK_CTL13
40010134 a CYREG_PERI_PCLK_CTL13
40010138 a CYREG_PERI_PCLK_CTL14
40010138 a CYREG_PERI_PCLK_CTL14
4001013c a CYREG_PERI_PCLK_CTL15
4001013c a CYREG_PERI_PCLK_CTL15
40010108 a CYREG_PERI_PCLK_CTL2
40010108 a CYREG_PERI_PCLK_CTL2
4001010c a CYREG_PERI_PCLK_CTL3
4001010c a CYREG_PERI_PCLK_CTL3
40010110 a CYREG_PERI_PCLK_CTL4
40010110 a CYREG_PERI_PCLK_CTL4
40010114 a CYREG_PERI_PCLK_CTL5
40010114 a CYREG_PERI_PCLK_CTL5
40010118 a CYREG_PERI_PCLK_CTL6
40010118 a CYREG_PERI_PCLK_CTL6
4001011c a CYREG_PERI_PCLK_CTL7
4001011c a CYREG_PERI_PCLK_CTL7
40010120 a CYREG_PERI_PCLK_CTL8
40010120 a CYREG_PERI_PCLK_CTL8
40010124 a CYREG_PERI_PCLK_CTL9
40010124 a CYREG_PERI_PCLK_CTL9
40010600 a CYREG_PERI_TR_CTL
40010600 a CYREG_PERI_TR_CTL
40012000 a CYREG_PERI_TR_GROUP_TR_OUT_CTL0
40012000 a CYREG_PERI_TR_GROUP_TR_OUT_CTL0
40012004 a CYREG_PERI_TR_GROUP_TR_OUT_CTL1
40012004 a CYREG_PERI_TR_GROUP_TR_OUT_CTL1
40012008 a CYREG_PERI_TR_GROUP_TR_OUT_CTL2
40012008 a CYREG_PERI_TR_GROUP_TR_OUT_CTL2
4001200c a CYREG_PERI_TR_GROUP_TR_OUT_CTL3
4001200c a CYREG_PERI_TR_GROUP_TR_OUT_CTL3
40012010 a CYREG_PERI_TR_GROUP_TR_OUT_CTL4
40012010 a CYREG_PERI_TR_GROUP_TR_OUT_CTL4
40012014 a CYREG_PERI_TR_GROUP_TR_OUT_CTL5
40012014 a CYREG_PERI_TR_GROUP_TR_OUT_CTL5
40012018 a CYREG_PERI_TR_GROUP_TR_OUT_CTL6
40012018 a CYREG_PERI_TR_GROUP_TR_OUT_CTL6
4001201c a CYREG_PERI_TR_GROUP_TR_OUT_CTL7
4001201c a CYREG_PERI_TR_GROUP_TR_OUT_CTL7
400b0014 a CYREG_PWR_BG_CONFIG
400b0014 a CYREG_PWR_BG_CONFIG
400bff10 a CYREG_PWR_BG_TRIM1
400bff10 a CYREG_PWR_BG_TRIM1
400bff14 a CYREG_PWR_BG_TRIM2
400bff14 a CYREG_PWR_BG_TRIM2
400bff18 a CYREG_PWR_BG_TRIM3
400bff18 a CYREG_PWR_BG_TRIM3
400bff1c a CYREG_PWR_BG_TRIM4
400bff1c a CYREG_PWR_BG_TRIM4
400bff20 a CYREG_PWR_BG_TRIM5
400bff20 a CYREG_PWR_BG_TRIM5
400b0028 a CYREG_PWR_BOD_KEY
400b0028 a CYREG_PWR_BOD_KEY
400b0000 a CYREG_PWR_CONTROL
400b0000 a CYREG_PWR_CONTROL
400b0020 a CYREG_PWR_DDFT_SELECT
400b0020 a CYREG_PWR_DDFT_SELECT
400b0024 a CYREG_PWR_DFT_KEY
400b0024 a CYREG_PWR_DFT_KEY
400b001c a CYREG_PWR_DFT_SELECT
400b001c a CYREG_PWR_DFT_SELECT
400b0004 a CYREG_PWR_INTR
400b0004 a CYREG_PWR_INTR
400b0008 a CYREG_PWR_INTR_MASK
400b0008 a CYREG_PWR_INTR_MASK
400b000c a CYREG_PWR_KEY_DELAY
400b000c a CYREG_PWR_KEY_DELAY
400b0010 a CYREG_PWR_PWRSYS_CONFIG
400b0010 a CYREG_PWR_PWRSYS_CONFIG
400bff00 a CYREG_PWR_PWRSYS_TRIM1
400bff00 a CYREG_PWR_PWRSYS_TRIM1
400bff04 a CYREG_PWR_PWRSYS_TRIM2
400bff04 a CYREG_PWR_PWRSYS_TRIM2
400bff08 a CYREG_PWR_PWRSYS_TRIM3
400bff08 a CYREG_PWR_PWRSYS_TRIM3
400bff0c a CYREG_PWR_PWRSYS_TRIM4
400bff0c a CYREG_PWR_PWRSYS_TRIM4
400bff38 a CYREG_PWR_RSVD_TRIM
400bff38 a CYREG_PWR_RSVD_TRIM
400b002c a CYREG_PWR_STOP
400b002c a CYREG_PWR_STOP
400b0018 a CYREG_PWR_VMON_CONFIG
400b0018 a CYREG_PWR_VMON_CONFIG
400b0300 a CYREG_RES_CAUSE
400b0300 a CYREG_RES_CAUSE
10000000 a CYREG_ROM_DATA_MBASE
10000000 a CYREG_ROM_DATA_MBASE
00002000 a CYREG_ROM_DATA_MSIZE
00002000 a CYREG_ROM_DATA_MSIZE
f0000000 a CYREG_ROMTABLE_ADDR
f0000000 a CYREG_ROMTABLE_ADDR
f0000ff0 a CYREG_ROMTABLE_CID0
f0000ff0 a CYREG_ROMTABLE_CID0
f0000ff4 a CYREG_ROMTABLE_CID1
f0000ff4 a CYREG_ROMTABLE_CID1
f0000ff8 a CYREG_ROMTABLE_CID2
f0000ff8 a CYREG_ROMTABLE_CID2
f0000ffc a CYREG_ROMTABLE_CID3
f0000ffc a CYREG_ROMTABLE_CID3
f0000fcc a CYREG_ROMTABLE_DID
f0000fcc a CYREG_ROMTABLE_DID
f0000fe0 a CYREG_ROMTABLE_PID0
f0000fe0 a CYREG_ROMTABLE_PID0
f0000fe4 a CYREG_ROMTABLE_PID1
f0000fe4 a CYREG_ROMTABLE_PID1
f0000fe8 a CYREG_ROMTABLE_PID2
f0000fe8 a CYREG_ROMTABLE_PID2
f0000fec a CYREG_ROMTABLE_PID3
f0000fec a CYREG_ROMTABLE_PID3
f0000fd0 a CYREG_ROMTABLE_PID4
f0000fd0 a CYREG_ROMTABLE_PID4
f0000fd4 a CYREG_ROMTABLE_PID5
f0000fd4 a CYREG_ROMTABLE_PID5
f0000fd8 a CYREG_ROMTABLE_PID6
f0000fd8 a CYREG_ROMTABLE_PID6
f0000fdc a CYREG_ROMTABLE_PID7
f0000fdc a CYREG_ROMTABLE_PID7
403a0f00 a CYREG_SAR_ANA_TRIM
403a0f00 a CYREG_SAR_ANA_TRIM
403a020c a CYREG_SAR_AVG_STAT
403a020c a CYREG_SAR_AVG_STAT
403a0080 a CYREG_SAR_CHAN_CONFIG0
403a0080 a CYREG_SAR_CHAN_CONFIG0
403a0080 a CYREG_SAR_CHAN_CONFIG00
403a0080 a CYREG_SAR_CHAN_CONFIG00
403a0084 a CYREG_SAR_CHAN_CONFIG01
403a0084 a CYREG_SAR_CHAN_CONFIG01
403a0088 a CYREG_SAR_CHAN_CONFIG02
403a0088 a CYREG_SAR_CHAN_CONFIG02
403a008c a CYREG_SAR_CHAN_CONFIG03
403a008c a CYREG_SAR_CHAN_CONFIG03
403a0090 a CYREG_SAR_CHAN_CONFIG04
403a0090 a CYREG_SAR_CHAN_CONFIG04
403a0094 a CYREG_SAR_CHAN_CONFIG05
403a0094 a CYREG_SAR_CHAN_CONFIG05
403a0098 a CYREG_SAR_CHAN_CONFIG06
403a0098 a CYREG_SAR_CHAN_CONFIG06
403a009c a CYREG_SAR_CHAN_CONFIG07
403a009c a CYREG_SAR_CHAN_CONFIG07
403a00a0 a CYREG_SAR_CHAN_CONFIG08
403a00a0 a CYREG_SAR_CHAN_CONFIG08
403a00a4 a CYREG_SAR_CHAN_CONFIG09
403a00a4 a CYREG_SAR_CHAN_CONFIG09
403a0084 a CYREG_SAR_CHAN_CONFIG1
403a0084 a CYREG_SAR_CHAN_CONFIG1
403a00a8 a CYREG_SAR_CHAN_CONFIG10
403a00a8 a CYREG_SAR_CHAN_CONFIG10
403a00ac a CYREG_SAR_CHAN_CONFIG11
403a00ac a CYREG_SAR_CHAN_CONFIG11
403a00b0 a CYREG_SAR_CHAN_CONFIG12
403a00b0 a CYREG_SAR_CHAN_CONFIG12
403a00b4 a CYREG_SAR_CHAN_CONFIG13
403a00b4 a CYREG_SAR_CHAN_CONFIG13
403a00b8 a CYREG_SAR_CHAN_CONFIG14
403a00b8 a CYREG_SAR_CHAN_CONFIG14
403a00bc a CYREG_SAR_CHAN_CONFIG15
403a00bc a CYREG_SAR_CHAN_CONFIG15
403a0088 a CYREG_SAR_CHAN_CONFIG2
403a0088 a CYREG_SAR_CHAN_CONFIG2
403a008c a CYREG_SAR_CHAN_CONFIG3
403a008c a CYREG_SAR_CHAN_CONFIG3
403a0090 a CYREG_SAR_CHAN_CONFIG4
403a0090 a CYREG_SAR_CHAN_CONFIG4
403a0094 a CYREG_SAR_CHAN_CONFIG5
403a0094 a CYREG_SAR_CHAN_CONFIG5
403a0098 a CYREG_SAR_CHAN_CONFIG6
403a0098 a CYREG_SAR_CHAN_CONFIG6
403a009c a CYREG_SAR_CHAN_CONFIG7
403a009c a CYREG_SAR_CHAN_CONFIG7
403a00a0 a CYREG_SAR_CHAN_CONFIG8
403a00a0 a CYREG_SAR_CHAN_CONFIG8
403a00a4 a CYREG_SAR_CHAN_CONFIG9
403a00a4 a CYREG_SAR_CHAN_CONFIG9
403a0020 a CYREG_SAR_CHAN_EN
403a0020 a CYREG_SAR_CHAN_EN
403a0204 a CYREG_SAR_CHAN_RESULT_VALID
403a0204 a CYREG_SAR_CHAN_RESULT_VALID
403a0180 a CYREG_SAR_CHAN_RESULT0
403a0180 a CYREG_SAR_CHAN_RESULT0
403a0180 a CYREG_SAR_CHAN_RESULT00
403a0180 a CYREG_SAR_CHAN_RESULT00
403a0184 a CYREG_SAR_CHAN_RESULT01
403a0184 a CYREG_SAR_CHAN_RESULT01
403a0188 a CYREG_SAR_CHAN_RESULT02
403a0188 a CYREG_SAR_CHAN_RESULT02
403a018c a CYREG_SAR_CHAN_RESULT03
403a018c a CYREG_SAR_CHAN_RESULT03
403a0190 a CYREG_SAR_CHAN_RESULT04
403a0190 a CYREG_SAR_CHAN_RESULT04
403a0194 a CYREG_SAR_CHAN_RESULT05
403a0194 a CYREG_SAR_CHAN_RESULT05
403a0198 a CYREG_SAR_CHAN_RESULT06
403a0198 a CYREG_SAR_CHAN_RESULT06
403a019c a CYREG_SAR_CHAN_RESULT07
403a019c a CYREG_SAR_CHAN_RESULT07
403a01a0 a CYREG_SAR_CHAN_RESULT08
403a01a0 a CYREG_SAR_CHAN_RESULT08
403a01a4 a CYREG_SAR_CHAN_RESULT09
403a01a4 a CYREG_SAR_CHAN_RESULT09
403a0184 a CYREG_SAR_CHAN_RESULT1
403a0184 a CYREG_SAR_CHAN_RESULT1
403a01a8 a CYREG_SAR_CHAN_RESULT10
403a01a8 a CYREG_SAR_CHAN_RESULT10
403a01ac a CYREG_SAR_CHAN_RESULT11
403a01ac a CYREG_SAR_CHAN_RESULT11
403a01b0 a CYREG_SAR_CHAN_RESULT12
403a01b0 a CYREG_SAR_CHAN_RESULT12
403a01b4 a CYREG_SAR_CHAN_RESULT13
403a01b4 a CYREG_SAR_CHAN_RESULT13
403a01b8 a CYREG_SAR_CHAN_RESULT14
403a01b8 a CYREG_SAR_CHAN_RESULT14
403a01bc a CYREG_SAR_CHAN_RESULT15
403a01bc a CYREG_SAR_CHAN_RESULT15
403a0188 a CYREG_SAR_CHAN_RESULT2
403a0188 a CYREG_SAR_CHAN_RESULT2
403a018c a CYREG_SAR_CHAN_RESULT3
403a018c a CYREG_SAR_CHAN_RESULT3
403a0190 a CYREG_SAR_CHAN_RESULT4
403a0190 a CYREG_SAR_CHAN_RESULT4
403a0194 a CYREG_SAR_CHAN_RESULT5
403a0194 a CYREG_SAR_CHAN_RESULT5
403a0198 a CYREG_SAR_CHAN_RESULT6
403a0198 a CYREG_SAR_CHAN_RESULT6
403a019c a CYREG_SAR_CHAN_RESULT7
403a019c a CYREG_SAR_CHAN_RESULT7
403a01a0 a CYREG_SAR_CHAN_RESULT8
403a01a0 a CYREG_SAR_CHAN_RESULT8
403a01a4 a CYREG_SAR_CHAN_RESULT9
403a01a4 a CYREG_SAR_CHAN_RESULT9
403a0200 a CYREG_SAR_CHAN_WORK_VALID
403a0200 a CYREG_SAR_CHAN_WORK_VALID
403a0100 a CYREG_SAR_CHAN_WORK0
403a0100 a CYREG_SAR_CHAN_WORK0
403a0100 a CYREG_SAR_CHAN_WORK00
403a0100 a CYREG_SAR_CHAN_WORK00
403a0104 a CYREG_SAR_CHAN_WORK01
403a0104 a CYREG_SAR_CHAN_WORK01
403a0108 a CYREG_SAR_CHAN_WORK02
403a0108 a CYREG_SAR_CHAN_WORK02
403a010c a CYREG_SAR_CHAN_WORK03
403a010c a CYREG_SAR_CHAN_WORK03
403a0110 a CYREG_SAR_CHAN_WORK04
403a0110 a CYREG_SAR_CHAN_WORK04
403a0114 a CYREG_SAR_CHAN_WORK05
403a0114 a CYREG_SAR_CHAN_WORK05
403a0118 a CYREG_SAR_CHAN_WORK06
403a0118 a CYREG_SAR_CHAN_WORK06
403a011c a CYREG_SAR_CHAN_WORK07
403a011c a CYREG_SAR_CHAN_WORK07
403a0120 a CYREG_SAR_CHAN_WORK08
403a0120 a CYREG_SAR_CHAN_WORK08
403a0124 a CYREG_SAR_CHAN_WORK09
403a0124 a CYREG_SAR_CHAN_WORK09
403a0104 a CYREG_SAR_CHAN_WORK1
403a0104 a CYREG_SAR_CHAN_WORK1
403a0128 a CYREG_SAR_CHAN_WORK10
403a0128 a CYREG_SAR_CHAN_WORK10
403a012c a CYREG_SAR_CHAN_WORK11
403a012c a CYREG_SAR_CHAN_WORK11
403a0130 a CYREG_SAR_CHAN_WORK12
403a0130 a CYREG_SAR_CHAN_WORK12
403a0134 a CYREG_SAR_CHAN_WORK13
403a0134 a CYREG_SAR_CHAN_WORK13
403a0138 a CYREG_SAR_CHAN_WORK14
403a0138 a CYREG_SAR_CHAN_WORK14
403a013c a CYREG_SAR_CHAN_WORK15
403a013c a CYREG_SAR_CHAN_WORK15
403a0108 a CYREG_SAR_CHAN_WORK2
403a0108 a CYREG_SAR_CHAN_WORK2
403a010c a CYREG_SAR_CHAN_WORK3
403a010c a CYREG_SAR_CHAN_WORK3
403a0110 a CYREG_SAR_CHAN_WORK4
403a0110 a CYREG_SAR_CHAN_WORK4
403a0114 a CYREG_SAR_CHAN_WORK5
403a0114 a CYREG_SAR_CHAN_WORK5
403a0118 a CYREG_SAR_CHAN_WORK6
403a0118 a CYREG_SAR_CHAN_WORK6
403a011c a CYREG_SAR_CHAN_WORK7
403a011c a CYREG_SAR_CHAN_WORK7
403a0120 a CYREG_SAR_CHAN_WORK8
403a0120 a CYREG_SAR_CHAN_WORK8
403a0124 a CYREG_SAR_CHAN_WORK9
403a0124 a CYREG_SAR_CHAN_WORK9
403a0000 a CYREG_SAR_CTRL
403a0000 a CYREG_SAR_CTRL
403a0030 a CYREG_SAR_DFT_CTRL
403a0030 a CYREG_SAR_DFT_CTRL
403a0280 a CYREG_SAR_INJ_CHAN_CONFIG
403a0280 a CYREG_SAR_INJ_CHAN_CONFIG
403a0290 a CYREG_SAR_INJ_RESULT
403a0290 a CYREG_SAR_INJ_RESULT
403a0210 a CYREG_SAR_INTR
403a0210 a CYREG_SAR_INTR
403a0240 a CYREG_SAR_INTR_CAUSE
403a0240 a CYREG_SAR_INTR_CAUSE
403a0218 a CYREG_SAR_INTR_MASK
403a0218 a CYREG_SAR_INTR_MASK
403a021c a CYREG_SAR_INTR_MASKED
403a021c a CYREG_SAR_INTR_MASKED
403a0214 a CYREG_SAR_INTR_SET
403a0214 a CYREG_SAR_INTR_SET
403a0304 a CYREG_SAR_MUX_SWITCH_CLEAR0
403a0304 a CYREG_SAR_MUX_SWITCH_CLEAR0
403a030c a CYREG_SAR_MUX_SWITCH_CLEAR1
403a030c a CYREG_SAR_MUX_SWITCH_CLEAR1
403a0340 a CYREG_SAR_MUX_SWITCH_HW_CTRL
403a0340 a CYREG_SAR_MUX_SWITCH_HW_CTRL
403a0348 a CYREG_SAR_MUX_SWITCH_STATUS
403a0348 a CYREG_SAR_MUX_SWITCH_STATUS
403a0300 a CYREG_SAR_MUX_SWITCH0
403a0300 a CYREG_SAR_MUX_SWITCH0
403a0308 a CYREG_SAR_MUX_SWITCH1
403a0308 a CYREG_SAR_MUX_SWITCH1
403a0380 a CYREG_SAR_PUMP_CTRL
403a0380 a CYREG_SAR_PUMP_CTRL
403a001c a CYREG_SAR_RANGE_COND
403a001c a CYREG_SAR_RANGE_COND
403a0230 a CYREG_SAR_RANGE_INTR
403a0230 a CYREG_SAR_RANGE_INTR
403a0238 a CYREG_SAR_RANGE_INTR_MASK
403a0238 a CYREG_SAR_RANGE_INTR_MASK
403a023c a CYREG_SAR_RANGE_INTR_MASKED
403a023c a CYREG_SAR_RANGE_INTR_MASKED
403a0234 a CYREG_SAR_RANGE_INTR_SET
403a0234 a CYREG_SAR_RANGE_INTR_SET
403a0018 a CYREG_SAR_RANGE_THRES
403a0018 a CYREG_SAR_RANGE_THRES
403a0004 a CYREG_SAR_SAMPLE_CTRL
403a0004 a CYREG_SAR_SAMPLE_CTRL
403a0010 a CYREG_SAR_SAMPLE_TIME01
403a0010 a CYREG_SAR_SAMPLE_TIME01
403a0014 a CYREG_SAR_SAMPLE_TIME23
403a0014 a CYREG_SAR_SAMPLE_TIME23
403a0220 a CYREG_SAR_SATURATE_INTR
403a0220 a CYREG_SAR_SATURATE_INTR
403a0228 a CYREG_SAR_SATURATE_INTR_MASK
403a0228 a CYREG_SAR_SATURATE_INTR_MASK
403a022c a CYREG_SAR_SATURATE_INTR_MASKED
403a022c a CYREG_SAR_SATURATE_INTR_MASKED
403a0224 a CYREG_SAR_SATURATE_INTR_SET
403a0224 a CYREG_SAR_SATURATE_INTR_SET
403a0024 a CYREG_SAR_START_CTRL
403a0024 a CYREG_SAR_START_CTRL
403a0208 a CYREG_SAR_STATUS
403a0208 a CYREG_SAR_STATUS
403a0f04 a CYREG_SAR_WOUNDING
403a0f04 a CYREG_SAR_WOUNDING
40240000 a CYREG_SCB0_CTRL
40240000 a CYREG_SCB0_CTRL
40240400 a CYREG_SCB0_EZ_DATA0
40240400 a CYREG_SCB0_EZ_DATA0
40240400 a CYREG_SCB0_EZ_DATA000
40240400 a CYREG_SCB0_EZ_DATA000
40240404 a CYREG_SCB0_EZ_DATA001
40240404 a CYREG_SCB0_EZ_DATA001
40240408 a CYREG_SCB0_EZ_DATA002
40240408 a CYREG_SCB0_EZ_DATA002
4024040c a CYREG_SCB0_EZ_DATA003
4024040c a CYREG_SCB0_EZ_DATA003
40240410 a CYREG_SCB0_EZ_DATA004
40240410 a CYREG_SCB0_EZ_DATA004
40240414 a CYREG_SCB0_EZ_DATA005
40240414 a CYREG_SCB0_EZ_DATA005
40240418 a CYREG_SCB0_EZ_DATA006
40240418 a CYREG_SCB0_EZ_DATA006
4024041c a CYREG_SCB0_EZ_DATA007
4024041c a CYREG_SCB0_EZ_DATA007
40240420 a CYREG_SCB0_EZ_DATA008
40240420 a CYREG_SCB0_EZ_DATA008
40240424 a CYREG_SCB0_EZ_DATA009
40240424 a CYREG_SCB0_EZ_DATA009
40240428 a CYREG_SCB0_EZ_DATA010
40240428 a CYREG_SCB0_EZ_DATA010
4024042c a CYREG_SCB0_EZ_DATA011
4024042c a CYREG_SCB0_EZ_DATA011
40240430 a CYREG_SCB0_EZ_DATA012
40240430 a CYREG_SCB0_EZ_DATA012
40240434 a CYREG_SCB0_EZ_DATA013
40240434 a CYREG_SCB0_EZ_DATA013
40240438 a CYREG_SCB0_EZ_DATA014
40240438 a CYREG_SCB0_EZ_DATA014
4024043c a CYREG_SCB0_EZ_DATA015
4024043c a CYREG_SCB0_EZ_DATA015
40240440 a CYREG_SCB0_EZ_DATA016
40240440 a CYREG_SCB0_EZ_DATA016
40240444 a CYREG_SCB0_EZ_DATA017
40240444 a CYREG_SCB0_EZ_DATA017
40240448 a CYREG_SCB0_EZ_DATA018
40240448 a CYREG_SCB0_EZ_DATA018
4024044c a CYREG_SCB0_EZ_DATA019
4024044c a CYREG_SCB0_EZ_DATA019
40240450 a CYREG_SCB0_EZ_DATA020
40240450 a CYREG_SCB0_EZ_DATA020
40240454 a CYREG_SCB0_EZ_DATA021
40240454 a CYREG_SCB0_EZ_DATA021
40240458 a CYREG_SCB0_EZ_DATA022
40240458 a CYREG_SCB0_EZ_DATA022
4024045c a CYREG_SCB0_EZ_DATA023
4024045c a CYREG_SCB0_EZ_DATA023
40240460 a CYREG_SCB0_EZ_DATA024
40240460 a CYREG_SCB0_EZ_DATA024
40240464 a CYREG_SCB0_EZ_DATA025
40240464 a CYREG_SCB0_EZ_DATA025
40240468 a CYREG_SCB0_EZ_DATA026
40240468 a CYREG_SCB0_EZ_DATA026
4024046c a CYREG_SCB0_EZ_DATA027
4024046c a CYREG_SCB0_EZ_DATA027
40240470 a CYREG_SCB0_EZ_DATA028
40240470 a CYREG_SCB0_EZ_DATA028
40240474 a CYREG_SCB0_EZ_DATA029
40240474 a CYREG_SCB0_EZ_DATA029
40240478 a CYREG_SCB0_EZ_DATA030
40240478 a CYREG_SCB0_EZ_DATA030
4024047c a CYREG_SCB0_EZ_DATA031
4024047c a CYREG_SCB0_EZ_DATA031
40240404 a CYREG_SCB0_EZ_DATA1
40240404 a CYREG_SCB0_EZ_DATA1
40240428 a CYREG_SCB0_EZ_DATA10
40240428 a CYREG_SCB0_EZ_DATA10
4024042c a CYREG_SCB0_EZ_DATA11
4024042c a CYREG_SCB0_EZ_DATA11
40240430 a CYREG_SCB0_EZ_DATA12
40240430 a CYREG_SCB0_EZ_DATA12
40240434 a CYREG_SCB0_EZ_DATA13
40240434 a CYREG_SCB0_EZ_DATA13
40240438 a CYREG_SCB0_EZ_DATA14
40240438 a CYREG_SCB0_EZ_DATA14
4024043c a CYREG_SCB0_EZ_DATA15
4024043c a CYREG_SCB0_EZ_DATA15
40240440 a CYREG_SCB0_EZ_DATA16
40240440 a CYREG_SCB0_EZ_DATA16
40240444 a CYREG_SCB0_EZ_DATA17
40240444 a CYREG_SCB0_EZ_DATA17
40240448 a CYREG_SCB0_EZ_DATA18
40240448 a CYREG_SCB0_EZ_DATA18
4024044c a CYREG_SCB0_EZ_DATA19
4024044c a CYREG_SCB0_EZ_DATA19
40240408 a CYREG_SCB0_EZ_DATA2
40240408 a CYREG_SCB0_EZ_DATA2
40240450 a CYREG_SCB0_EZ_DATA20
40240450 a CYREG_SCB0_EZ_DATA20
40240454 a CYREG_SCB0_EZ_DATA21
40240454 a CYREG_SCB0_EZ_DATA21
40240458 a CYREG_SCB0_EZ_DATA22
40240458 a CYREG_SCB0_EZ_DATA22
4024045c a CYREG_SCB0_EZ_DATA23
4024045c a CYREG_SCB0_EZ_DATA23
40240460 a CYREG_SCB0_EZ_DATA24
40240460 a CYREG_SCB0_EZ_DATA24
40240464 a CYREG_SCB0_EZ_DATA25
40240464 a CYREG_SCB0_EZ_DATA25
40240468 a CYREG_SCB0_EZ_DATA26
40240468 a CYREG_SCB0_EZ_DATA26
4024046c a CYREG_SCB0_EZ_DATA27
4024046c a CYREG_SCB0_EZ_DATA27
40240470 a CYREG_SCB0_EZ_DATA28
40240470 a CYREG_SCB0_EZ_DATA28
40240474 a CYREG_SCB0_EZ_DATA29
40240474 a CYREG_SCB0_EZ_DATA29
4024040c a CYREG_SCB0_EZ_DATA3
4024040c a CYREG_SCB0_EZ_DATA3
40240478 a CYREG_SCB0_EZ_DATA30
40240478 a CYREG_SCB0_EZ_DATA30
4024047c a CYREG_SCB0_EZ_DATA31
4024047c a CYREG_SCB0_EZ_DATA31
40240410 a CYREG_SCB0_EZ_DATA4
40240410 a CYREG_SCB0_EZ_DATA4
40240414 a CYREG_SCB0_EZ_DATA5
40240414 a CYREG_SCB0_EZ_DATA5
40240418 a CYREG_SCB0_EZ_DATA6
40240418 a CYREG_SCB0_EZ_DATA6
4024041c a CYREG_SCB0_EZ_DATA7
4024041c a CYREG_SCB0_EZ_DATA7
40240420 a CYREG_SCB0_EZ_DATA8
40240420 a CYREG_SCB0_EZ_DATA8
40240424 a CYREG_SCB0_EZ_DATA9
40240424 a CYREG_SCB0_EZ_DATA9
40240070 a CYREG_SCB0_I2C_CFG
40240070 a CYREG_SCB0_I2C_CFG
40240060 a CYREG_SCB0_I2C_CTRL
40240060 a CYREG_SCB0_I2C_CTRL
40240068 a CYREG_SCB0_I2C_M_CMD
40240068 a CYREG_SCB0_I2C_M_CMD
4024006c a CYREG_SCB0_I2C_S_CMD
4024006c a CYREG_SCB0_I2C_S_CMD
40240064 a CYREG_SCB0_I2C_STATUS
40240064 a CYREG_SCB0_I2C_STATUS
40240e00 a CYREG_SCB0_INTR_CAUSE
40240e00 a CYREG_SCB0_INTR_CAUSE
40240e80 a CYREG_SCB0_INTR_I2C_EC
40240e80 a CYREG_SCB0_INTR_I2C_EC
40240e88 a CYREG_SCB0_INTR_I2C_EC_MASK
40240e88 a CYREG_SCB0_INTR_I2C_EC_MASK
40240e8c a CYREG_SCB0_INTR_I2C_EC_MASKED
40240e8c a CYREG_SCB0_INTR_I2C_EC_MASKED
40240f00 a CYREG_SCB0_INTR_M
40240f00 a CYREG_SCB0_INTR_M
40240f08 a CYREG_SCB0_INTR_M_MASK
40240f08 a CYREG_SCB0_INTR_M_MASK
40240f0c a CYREG_SCB0_INTR_M_MASKED
40240f0c a CYREG_SCB0_INTR_M_MASKED
40240f04 a CYREG_SCB0_INTR_M_SET
40240f04 a CYREG_SCB0_INTR_M_SET
40240fc0 a CYREG_SCB0_INTR_RX
40240fc0 a CYREG_SCB0_INTR_RX
40240fc8 a CYREG_SCB0_INTR_RX_MASK
40240fc8 a CYREG_SCB0_INTR_RX_MASK
40240fcc a CYREG_SCB0_INTR_RX_MASKED
40240fcc a CYREG_SCB0_INTR_RX_MASKED
40240fc4 a CYREG_SCB0_INTR_RX_SET
40240fc4 a CYREG_SCB0_INTR_RX_SET
40240f40 a CYREG_SCB0_INTR_S
40240f40 a CYREG_SCB0_INTR_S
40240f48 a CYREG_SCB0_INTR_S_MASK
40240f48 a CYREG_SCB0_INTR_S_MASK
40240f4c a CYREG_SCB0_INTR_S_MASKED
40240f4c a CYREG_SCB0_INTR_S_MASKED
40240f44 a CYREG_SCB0_INTR_S_SET
40240f44 a CYREG_SCB0_INTR_S_SET
40240ec0 a CYREG_SCB0_INTR_SPI_EC
40240ec0 a CYREG_SCB0_INTR_SPI_EC
40240ec8 a CYREG_SCB0_INTR_SPI_EC_MASK
40240ec8 a CYREG_SCB0_INTR_SPI_EC_MASK
40240ecc a CYREG_SCB0_INTR_SPI_EC_MASKED
40240ecc a CYREG_SCB0_INTR_SPI_EC_MASKED
40240f80 a CYREG_SCB0_INTR_TX
40240f80 a CYREG_SCB0_INTR_TX
40240f88 a CYREG_SCB0_INTR_TX_MASK
40240f88 a CYREG_SCB0_INTR_TX_MASK
40240f8c a CYREG_SCB0_INTR_TX_MASKED
40240f8c a CYREG_SCB0_INTR_TX_MASKED
40240f84 a CYREG_SCB0_INTR_TX_SET
40240f84 a CYREG_SCB0_INTR_TX_SET
40240300 a CYREG_SCB0_RX_CTRL
40240300 a CYREG_SCB0_RX_CTRL
40240304 a CYREG_SCB0_RX_FIFO_CTRL
40240304 a CYREG_SCB0_RX_FIFO_CTRL
40240340 a CYREG_SCB0_RX_FIFO_RD
40240340 a CYREG_SCB0_RX_FIFO_RD
40240344 a CYREG_SCB0_RX_FIFO_RD_SILENT
40240344 a CYREG_SCB0_RX_FIFO_RD_SILENT
40240308 a CYREG_SCB0_RX_FIFO_STATUS
40240308 a CYREG_SCB0_RX_FIFO_STATUS
40240310 a CYREG_SCB0_RX_MATCH
40240310 a CYREG_SCB0_RX_MATCH
40240020 a CYREG_SCB0_SPI_CTRL
40240020 a CYREG_SCB0_SPI_CTRL
40240024 a CYREG_SCB0_SPI_STATUS
40240024 a CYREG_SCB0_SPI_STATUS
40240004 a CYREG_SCB0_STATUS
40240004 a CYREG_SCB0_STATUS
40240200 a CYREG_SCB0_TX_CTRL
40240200 a CYREG_SCB0_TX_CTRL
40240204 a CYREG_SCB0_TX_FIFO_CTRL
40240204 a CYREG_SCB0_TX_FIFO_CTRL
40240208 a CYREG_SCB0_TX_FIFO_STATUS
40240208 a CYREG_SCB0_TX_FIFO_STATUS
40240240 a CYREG_SCB0_TX_FIFO_WR
40240240 a CYREG_SCB0_TX_FIFO_WR
40240040 a CYREG_SCB0_UART_CTRL
40240040 a CYREG_SCB0_UART_CTRL
40240050 a CYREG_SCB0_UART_FLOW_CTRL
40240050 a CYREG_SCB0_UART_FLOW_CTRL
40240048 a CYREG_SCB0_UART_RX_CTRL
40240048 a CYREG_SCB0_UART_RX_CTRL
4024004c a CYREG_SCB0_UART_RX_STATUS
4024004c a CYREG_SCB0_UART_RX_STATUS
40240044 a CYREG_SCB0_UART_TX_CTRL
40240044 a CYREG_SCB0_UART_TX_CTRL
40250000 a CYREG_SCB1_CTRL
40250000 a CYREG_SCB1_CTRL
40250400 a CYREG_SCB1_EZ_DATA0
40250400 a CYREG_SCB1_EZ_DATA0
40250400 a CYREG_SCB1_EZ_DATA000
40250400 a CYREG_SCB1_EZ_DATA000
40250404 a CYREG_SCB1_EZ_DATA001
40250404 a CYREG_SCB1_EZ_DATA001
40250408 a CYREG_SCB1_EZ_DATA002
40250408 a CYREG_SCB1_EZ_DATA002
4025040c a CYREG_SCB1_EZ_DATA003
4025040c a CYREG_SCB1_EZ_DATA003
40250410 a CYREG_SCB1_EZ_DATA004
40250410 a CYREG_SCB1_EZ_DATA004
40250414 a CYREG_SCB1_EZ_DATA005
40250414 a CYREG_SCB1_EZ_DATA005
40250418 a CYREG_SCB1_EZ_DATA006
40250418 a CYREG_SCB1_EZ_DATA006
4025041c a CYREG_SCB1_EZ_DATA007
4025041c a CYREG_SCB1_EZ_DATA007
40250420 a CYREG_SCB1_EZ_DATA008
40250420 a CYREG_SCB1_EZ_DATA008
40250424 a CYREG_SCB1_EZ_DATA009
40250424 a CYREG_SCB1_EZ_DATA009
40250428 a CYREG_SCB1_EZ_DATA010
40250428 a CYREG_SCB1_EZ_DATA010
4025042c a CYREG_SCB1_EZ_DATA011
4025042c a CYREG_SCB1_EZ_DATA011
40250430 a CYREG_SCB1_EZ_DATA012
40250430 a CYREG_SCB1_EZ_DATA012
40250434 a CYREG_SCB1_EZ_DATA013
40250434 a CYREG_SCB1_EZ_DATA013
40250438 a CYREG_SCB1_EZ_DATA014
40250438 a CYREG_SCB1_EZ_DATA014
4025043c a CYREG_SCB1_EZ_DATA015
4025043c a CYREG_SCB1_EZ_DATA015
40250440 a CYREG_SCB1_EZ_DATA016
40250440 a CYREG_SCB1_EZ_DATA016
40250444 a CYREG_SCB1_EZ_DATA017
40250444 a CYREG_SCB1_EZ_DATA017
40250448 a CYREG_SCB1_EZ_DATA018
40250448 a CYREG_SCB1_EZ_DATA018
4025044c a CYREG_SCB1_EZ_DATA019
4025044c a CYREG_SCB1_EZ_DATA019
40250450 a CYREG_SCB1_EZ_DATA020
40250450 a CYREG_SCB1_EZ_DATA020
40250454 a CYREG_SCB1_EZ_DATA021
40250454 a CYREG_SCB1_EZ_DATA021
40250458 a CYREG_SCB1_EZ_DATA022
40250458 a CYREG_SCB1_EZ_DATA022
4025045c a CYREG_SCB1_EZ_DATA023
4025045c a CYREG_SCB1_EZ_DATA023
40250460 a CYREG_SCB1_EZ_DATA024
40250460 a CYREG_SCB1_EZ_DATA024
40250464 a CYREG_SCB1_EZ_DATA025
40250464 a CYREG_SCB1_EZ_DATA025
40250468 a CYREG_SCB1_EZ_DATA026
40250468 a CYREG_SCB1_EZ_DATA026
4025046c a CYREG_SCB1_EZ_DATA027
4025046c a CYREG_SCB1_EZ_DATA027
40250470 a CYREG_SCB1_EZ_DATA028
40250470 a CYREG_SCB1_EZ_DATA028
40250474 a CYREG_SCB1_EZ_DATA029
40250474 a CYREG_SCB1_EZ_DATA029
40250478 a CYREG_SCB1_EZ_DATA030
40250478 a CYREG_SCB1_EZ_DATA030
4025047c a CYREG_SCB1_EZ_DATA031
4025047c a CYREG_SCB1_EZ_DATA031
40250404 a CYREG_SCB1_EZ_DATA1
40250404 a CYREG_SCB1_EZ_DATA1
40250428 a CYREG_SCB1_EZ_DATA10
40250428 a CYREG_SCB1_EZ_DATA10
4025042c a CYREG_SCB1_EZ_DATA11
4025042c a CYREG_SCB1_EZ_DATA11
40250430 a CYREG_SCB1_EZ_DATA12
40250430 a CYREG_SCB1_EZ_DATA12
40250434 a CYREG_SCB1_EZ_DATA13
40250434 a CYREG_SCB1_EZ_DATA13
40250438 a CYREG_SCB1_EZ_DATA14
40250438 a CYREG_SCB1_EZ_DATA14
4025043c a CYREG_SCB1_EZ_DATA15
4025043c a CYREG_SCB1_EZ_DATA15
40250440 a CYREG_SCB1_EZ_DATA16
40250440 a CYREG_SCB1_EZ_DATA16
40250444 a CYREG_SCB1_EZ_DATA17
40250444 a CYREG_SCB1_EZ_DATA17
40250448 a CYREG_SCB1_EZ_DATA18
40250448 a CYREG_SCB1_EZ_DATA18
4025044c a CYREG_SCB1_EZ_DATA19
4025044c a CYREG_SCB1_EZ_DATA19
40250408 a CYREG_SCB1_EZ_DATA2
40250408 a CYREG_SCB1_EZ_DATA2
40250450 a CYREG_SCB1_EZ_DATA20
40250450 a CYREG_SCB1_EZ_DATA20
40250454 a CYREG_SCB1_EZ_DATA21
40250454 a CYREG_SCB1_EZ_DATA21
40250458 a CYREG_SCB1_EZ_DATA22
40250458 a CYREG_SCB1_EZ_DATA22
4025045c a CYREG_SCB1_EZ_DATA23
4025045c a CYREG_SCB1_EZ_DATA23
40250460 a CYREG_SCB1_EZ_DATA24
40250460 a CYREG_SCB1_EZ_DATA24
40250464 a CYREG_SCB1_EZ_DATA25
40250464 a CYREG_SCB1_EZ_DATA25
40250468 a CYREG_SCB1_EZ_DATA26
40250468 a CYREG_SCB1_EZ_DATA26
4025046c a CYREG_SCB1_EZ_DATA27
4025046c a CYREG_SCB1_EZ_DATA27
40250470 a CYREG_SCB1_EZ_DATA28
40250470 a CYREG_SCB1_EZ_DATA28
40250474 a CYREG_SCB1_EZ_DATA29
40250474 a CYREG_SCB1_EZ_DATA29
4025040c a CYREG_SCB1_EZ_DATA3
4025040c a CYREG_SCB1_EZ_DATA3
40250478 a CYREG_SCB1_EZ_DATA30
40250478 a CYREG_SCB1_EZ_DATA30
4025047c a CYREG_SCB1_EZ_DATA31
4025047c a CYREG_SCB1_EZ_DATA31
40250410 a CYREG_SCB1_EZ_DATA4
40250410 a CYREG_SCB1_EZ_DATA4
40250414 a CYREG_SCB1_EZ_DATA5
40250414 a CYREG_SCB1_EZ_DATA5
40250418 a CYREG_SCB1_EZ_DATA6
40250418 a CYREG_SCB1_EZ_DATA6
4025041c a CYREG_SCB1_EZ_DATA7
4025041c a CYREG_SCB1_EZ_DATA7
40250420 a CYREG_SCB1_EZ_DATA8
40250420 a CYREG_SCB1_EZ_DATA8
40250424 a CYREG_SCB1_EZ_DATA9
40250424 a CYREG_SCB1_EZ_DATA9
40250070 a CYREG_SCB1_I2C_CFG
40250070 a CYREG_SCB1_I2C_CFG
40250060 a CYREG_SCB1_I2C_CTRL
40250060 a CYREG_SCB1_I2C_CTRL
40250068 a CYREG_SCB1_I2C_M_CMD
40250068 a CYREG_SCB1_I2C_M_CMD
4025006c a CYREG_SCB1_I2C_S_CMD
4025006c a CYREG_SCB1_I2C_S_CMD
40250064 a CYREG_SCB1_I2C_STATUS
40250064 a CYREG_SCB1_I2C_STATUS
40250e00 a CYREG_SCB1_INTR_CAUSE
40250e00 a CYREG_SCB1_INTR_CAUSE
40250e80 a CYREG_SCB1_INTR_I2C_EC
40250e80 a CYREG_SCB1_INTR_I2C_EC
40250e88 a CYREG_SCB1_INTR_I2C_EC_MASK
40250e88 a CYREG_SCB1_INTR_I2C_EC_MASK
40250e8c a CYREG_SCB1_INTR_I2C_EC_MASKED
40250e8c a CYREG_SCB1_INTR_I2C_EC_MASKED
40250f00 a CYREG_SCB1_INTR_M
40250f00 a CYREG_SCB1_INTR_M
40250f08 a CYREG_SCB1_INTR_M_MASK
40250f08 a CYREG_SCB1_INTR_M_MASK
40250f0c a CYREG_SCB1_INTR_M_MASKED
40250f0c a CYREG_SCB1_INTR_M_MASKED
40250f04 a CYREG_SCB1_INTR_M_SET
40250f04 a CYREG_SCB1_INTR_M_SET
40250fc0 a CYREG_SCB1_INTR_RX
40250fc0 a CYREG_SCB1_INTR_RX
40250fc8 a CYREG_SCB1_INTR_RX_MASK
40250fc8 a CYREG_SCB1_INTR_RX_MASK
40250fcc a CYREG_SCB1_INTR_RX_MASKED
40250fcc a CYREG_SCB1_INTR_RX_MASKED
40250fc4 a CYREG_SCB1_INTR_RX_SET
40250fc4 a CYREG_SCB1_INTR_RX_SET
40250f40 a CYREG_SCB1_INTR_S
40250f40 a CYREG_SCB1_INTR_S
40250f48 a CYREG_SCB1_INTR_S_MASK
40250f48 a CYREG_SCB1_INTR_S_MASK
40250f4c a CYREG_SCB1_INTR_S_MASKED
40250f4c a CYREG_SCB1_INTR_S_MASKED
40250f44 a CYREG_SCB1_INTR_S_SET
40250f44 a CYREG_SCB1_INTR_S_SET
40250ec0 a CYREG_SCB1_INTR_SPI_EC
40250ec0 a CYREG_SCB1_INTR_SPI_EC
40250ec8 a CYREG_SCB1_INTR_SPI_EC_MASK
40250ec8 a CYREG_SCB1_INTR_SPI_EC_MASK
40250ecc a CYREG_SCB1_INTR_SPI_EC_MASKED
40250ecc a CYREG_SCB1_INTR_SPI_EC_MASKED
40250f80 a CYREG_SCB1_INTR_TX
40250f80 a CYREG_SCB1_INTR_TX
40250f88 a CYREG_SCB1_INTR_TX_MASK
40250f88 a CYREG_SCB1_INTR_TX_MASK
40250f8c a CYREG_SCB1_INTR_TX_MASKED
40250f8c a CYREG_SCB1_INTR_TX_MASKED
40250f84 a CYREG_SCB1_INTR_TX_SET
40250f84 a CYREG_SCB1_INTR_TX_SET
40250300 a CYREG_SCB1_RX_CTRL
40250300 a CYREG_SCB1_RX_CTRL
40250304 a CYREG_SCB1_RX_FIFO_CTRL
40250304 a CYREG_SCB1_RX_FIFO_CTRL
40250340 a CYREG_SCB1_RX_FIFO_RD
40250340 a CYREG_SCB1_RX_FIFO_RD
40250344 a CYREG_SCB1_RX_FIFO_RD_SILENT
40250344 a CYREG_SCB1_RX_FIFO_RD_SILENT
40250308 a CYREG_SCB1_RX_FIFO_STATUS
40250308 a CYREG_SCB1_RX_FIFO_STATUS
40250310 a CYREG_SCB1_RX_MATCH
40250310 a CYREG_SCB1_RX_MATCH
40250020 a CYREG_SCB1_SPI_CTRL
40250020 a CYREG_SCB1_SPI_CTRL
40250024 a CYREG_SCB1_SPI_STATUS
40250024 a CYREG_SCB1_SPI_STATUS
40250004 a CYREG_SCB1_STATUS
40250004 a CYREG_SCB1_STATUS
40250200 a CYREG_SCB1_TX_CTRL
40250200 a CYREG_SCB1_TX_CTRL
40250204 a CYREG_SCB1_TX_FIFO_CTRL
40250204 a CYREG_SCB1_TX_FIFO_CTRL
40250208 a CYREG_SCB1_TX_FIFO_STATUS
40250208 a CYREG_SCB1_TX_FIFO_STATUS
40250240 a CYREG_SCB1_TX_FIFO_WR
40250240 a CYREG_SCB1_TX_FIFO_WR
40250040 a CYREG_SCB1_UART_CTRL
40250040 a CYREG_SCB1_UART_CTRL
40250050 a CYREG_SCB1_UART_FLOW_CTRL
40250050 a CYREG_SCB1_UART_FLOW_CTRL
40250048 a CYREG_SCB1_UART_RX_CTRL
40250048 a CYREG_SCB1_UART_RX_CTRL
4025004c a CYREG_SCB1_UART_RX_STATUS
4025004c a CYREG_SCB1_UART_RX_STATUS
40250044 a CYREG_SCB1_UART_TX_CTRL
40250044 a CYREG_SCB1_UART_TX_CTRL
0ffffb24 a CYREG_SFLASH_ALT_E
0ffffb24 a CYREG_SFLASH_ALT_E
0ffffb3c a CYREG_SFLASH_ALT_E_VCTAT
0ffffb3c a CYREG_SFLASH_ALT_E_VCTAT
0ffffb2c a CYREG_SFLASH_ALT_EA_E
0ffffb2c a CYREG_SFLASH_ALT_EA_E
0ffffb30 a CYREG_SFLASH_ALT_EA_P
0ffffb30 a CYREG_SFLASH_ALT_EA_P
0ffffb34 a CYREG_SFLASH_ALT_ES_E
0ffffb34 a CYREG_SFLASH_ALT_ES_E
0ffffb38 a CYREG_SFLASH_ALT_ES_P_EO
0ffffb38 a CYREG_SFLASH_ALT_ES_P_EO
0ffffb28 a CYREG_SFLASH_ALT_P
0ffffb28 a CYREG_SFLASH_ALT_P
0ffffb3d a CYREG_SFLASH_ALT_P_VCTAT
0ffffb3d a CYREG_SFLASH_ALT_P_VCTAT
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0ffff116 a CYREG_SFLASH_AV_PAIRS_8B022
0ffff116 a CYREG_SFLASH_AV_PAIRS_8B022
0ffff117 a CYREG_SFLASH_AV_PAIRS_8B023
0ffff117 a CYREG_SFLASH_AV_PAIRS_8B023
0ffff118 a CYREG_SFLASH_AV_PAIRS_8B024
0ffff118 a CYREG_SFLASH_AV_PAIRS_8B024
0ffff119 a CYREG_SFLASH_AV_PAIRS_8B025
0ffff119 a CYREG_SFLASH_AV_PAIRS_8B025
0ffff11a a CYREG_SFLASH_AV_PAIRS_8B026
0ffff11a a CYREG_SFLASH_AV_PAIRS_8B026
0ffff11b a CYREG_SFLASH_AV_PAIRS_8B027
0ffff11b a CYREG_SFLASH_AV_PAIRS_8B027
0ffff11c a CYREG_SFLASH_AV_PAIRS_8B028
0ffff11c a CYREG_SFLASH_AV_PAIRS_8B028
0ffff11d a CYREG_SFLASH_AV_PAIRS_8B029
0ffff11d a CYREG_SFLASH_AV_PAIRS_8B029
0ffff11e a CYREG_SFLASH_AV_PAIRS_8B030
0ffff11e a CYREG_SFLASH_AV_PAIRS_8B030
0ffff11f a CYREG_SFLASH_AV_PAIRS_8B031
0ffff11f a CYREG_SFLASH_AV_PAIRS_8B031
0ffff120 a CYREG_SFLASH_AV_PAIRS_8B032
0ffff120 a CYREG_SFLASH_AV_PAIRS_8B032
0ffff121 a CYREG_SFLASH_AV_PAIRS_8B033
0ffff121 a CYREG_SFLASH_AV_PAIRS_8B033
0ffff122 a CYREG_SFLASH_AV_PAIRS_8B034
0ffff122 a CYREG_SFLASH_AV_PAIRS_8B034
0ffff123 a CYREG_SFLASH_AV_PAIRS_8B035
0ffff123 a CYREG_SFLASH_AV_PAIRS_8B035
0ffff124 a CYREG_SFLASH_AV_PAIRS_8B036
0ffff124 a CYREG_SFLASH_AV_PAIRS_8B036
0ffff125 a CYREG_SFLASH_AV_PAIRS_8B037
0ffff125 a CYREG_SFLASH_AV_PAIRS_8B037
0ffff126 a CYREG_SFLASH_AV_PAIRS_8B038
0ffff126 a CYREG_SFLASH_AV_PAIRS_8B038
0ffff127 a CYREG_SFLASH_AV_PAIRS_8B039
0ffff127 a CYREG_SFLASH_AV_PAIRS_8B039
0ffff128 a CYREG_SFLASH_AV_PAIRS_8B040
0ffff128 a CYREG_SFLASH_AV_PAIRS_8B040
0ffff129 a CYREG_SFLASH_AV_PAIRS_8B041
0ffff129 a CYREG_SFLASH_AV_PAIRS_8B041
0ffff12a a CYREG_SFLASH_AV_PAIRS_8B042
0ffff12a a CYREG_SFLASH_AV_PAIRS_8B042
0ffff12b a CYREG_SFLASH_AV_PAIRS_8B043
0ffff12b a CYREG_SFLASH_AV_PAIRS_8B043
0ffff12c a CYREG_SFLASH_AV_PAIRS_8B044
0ffff12c a CYREG_SFLASH_AV_PAIRS_8B044
0ffff12d a CYREG_SFLASH_AV_PAIRS_8B045
0ffff12d a CYREG_SFLASH_AV_PAIRS_8B045
0ffff12e a CYREG_SFLASH_AV_PAIRS_8B046
0ffff12e a CYREG_SFLASH_AV_PAIRS_8B046
0ffff12f a CYREG_SFLASH_AV_PAIRS_8B047
0ffff12f a CYREG_SFLASH_AV_PAIRS_8B047
0ffff130 a CYREG_SFLASH_AV_PAIRS_8B048
0ffff130 a CYREG_SFLASH_AV_PAIRS_8B048
0ffff131 a CYREG_SFLASH_AV_PAIRS_8B049
0ffff131 a CYREG_SFLASH_AV_PAIRS_8B049
0ffff132 a CYREG_SFLASH_AV_PAIRS_8B050
0ffff132 a CYREG_SFLASH_AV_PAIRS_8B050
0ffff133 a CYREG_SFLASH_AV_PAIRS_8B051
0ffff133 a CYREG_SFLASH_AV_PAIRS_8B051
0ffff134 a CYREG_SFLASH_AV_PAIRS_8B052
0ffff134 a CYREG_SFLASH_AV_PAIRS_8B052
0ffff135 a CYREG_SFLASH_AV_PAIRS_8B053
0ffff135 a CYREG_SFLASH_AV_PAIRS_8B053
0ffff136 a CYREG_SFLASH_AV_PAIRS_8B054
0ffff136 a CYREG_SFLASH_AV_PAIRS_8B054
0ffff137 a CYREG_SFLASH_AV_PAIRS_8B055
0ffff137 a CYREG_SFLASH_AV_PAIRS_8B055
0ffff138 a CYREG_SFLASH_AV_PAIRS_8B056
0ffff138 a CYREG_SFLASH_AV_PAIRS_8B056
0ffff139 a CYREG_SFLASH_AV_PAIRS_8B057
0ffff139 a CYREG_SFLASH_AV_PAIRS_8B057
0ffff13a a CYREG_SFLASH_AV_PAIRS_8B058
0ffff13a a CYREG_SFLASH_AV_PAIRS_8B058
0ffff13b a CYREG_SFLASH_AV_PAIRS_8B059
0ffff13b a CYREG_SFLASH_AV_PAIRS_8B059
0ffff13c a CYREG_SFLASH_AV_PAIRS_8B060
0ffff13c a CYREG_SFLASH_AV_PAIRS_8B060
0ffff13d a CYREG_SFLASH_AV_PAIRS_8B061
0ffff13d a CYREG_SFLASH_AV_PAIRS_8B061
0ffff13e a CYREG_SFLASH_AV_PAIRS_8B062
0ffff13e a CYREG_SFLASH_AV_PAIRS_8B062
0ffff13f a CYREG_SFLASH_AV_PAIRS_8B063
0ffff13f a CYREG_SFLASH_AV_PAIRS_8B063
0ffff140 a CYREG_SFLASH_AV_PAIRS_8B064
0ffff140 a CYREG_SFLASH_AV_PAIRS_8B064
0ffff141 a CYREG_SFLASH_AV_PAIRS_8B065
0ffff141 a CYREG_SFLASH_AV_PAIRS_8B065
0ffff142 a CYREG_SFLASH_AV_PAIRS_8B066
0ffff142 a CYREG_SFLASH_AV_PAIRS_8B066
0ffff143 a CYREG_SFLASH_AV_PAIRS_8B067
0ffff143 a CYREG_SFLASH_AV_PAIRS_8B067
0ffff144 a CYREG_SFLASH_AV_PAIRS_8B068
0ffff144 a CYREG_SFLASH_AV_PAIRS_8B068
0ffff145 a CYREG_SFLASH_AV_PAIRS_8B069
0ffff145 a CYREG_SFLASH_AV_PAIRS_8B069
0ffff146 a CYREG_SFLASH_AV_PAIRS_8B070
0ffff146 a CYREG_SFLASH_AV_PAIRS_8B070
0ffff147 a CYREG_SFLASH_AV_PAIRS_8B071
0ffff147 a CYREG_SFLASH_AV_PAIRS_8B071
0ffff148 a CYREG_SFLASH_AV_PAIRS_8B072
0ffff148 a CYREG_SFLASH_AV_PAIRS_8B072
0ffff149 a CYREG_SFLASH_AV_PAIRS_8B073
0ffff149 a CYREG_SFLASH_AV_PAIRS_8B073
0ffff14a a CYREG_SFLASH_AV_PAIRS_8B074
0ffff14a a CYREG_SFLASH_AV_PAIRS_8B074
0ffff14b a CYREG_SFLASH_AV_PAIRS_8B075
0ffff14b a CYREG_SFLASH_AV_PAIRS_8B075
0ffff14c a CYREG_SFLASH_AV_PAIRS_8B076
0ffff14c a CYREG_SFLASH_AV_PAIRS_8B076
0ffff14d a CYREG_SFLASH_AV_PAIRS_8B077
0ffff14d a CYREG_SFLASH_AV_PAIRS_8B077
0ffff14e a CYREG_SFLASH_AV_PAIRS_8B078
0ffff14e a CYREG_SFLASH_AV_PAIRS_8B078
0ffff14f a CYREG_SFLASH_AV_PAIRS_8B079
0ffff14f a CYREG_SFLASH_AV_PAIRS_8B079
0ffff150 a CYREG_SFLASH_AV_PAIRS_8B080
0ffff150 a CYREG_SFLASH_AV_PAIRS_8B080
0ffff151 a CYREG_SFLASH_AV_PAIRS_8B081
0ffff151 a CYREG_SFLASH_AV_PAIRS_8B081
0ffff152 a CYREG_SFLASH_AV_PAIRS_8B082
0ffff152 a CYREG_SFLASH_AV_PAIRS_8B082
0ffff153 a CYREG_SFLASH_AV_PAIRS_8B083
0ffff153 a CYREG_SFLASH_AV_PAIRS_8B083
0ffff154 a CYREG_SFLASH_AV_PAIRS_8B084
0ffff154 a CYREG_SFLASH_AV_PAIRS_8B084
0ffff155 a CYREG_SFLASH_AV_PAIRS_8B085
0ffff155 a CYREG_SFLASH_AV_PAIRS_8B085
0ffff156 a CYREG_SFLASH_AV_PAIRS_8B086
0ffff156 a CYREG_SFLASH_AV_PAIRS_8B086
0ffff157 a CYREG_SFLASH_AV_PAIRS_8B087
0ffff157 a CYREG_SFLASH_AV_PAIRS_8B087
0ffff158 a CYREG_SFLASH_AV_PAIRS_8B088
0ffff158 a CYREG_SFLASH_AV_PAIRS_8B088
0ffff159 a CYREG_SFLASH_AV_PAIRS_8B089
0ffff159 a CYREG_SFLASH_AV_PAIRS_8B089
0ffff15a a CYREG_SFLASH_AV_PAIRS_8B090
0ffff15a a CYREG_SFLASH_AV_PAIRS_8B090
0ffff15b a CYREG_SFLASH_AV_PAIRS_8B091
0ffff15b a CYREG_SFLASH_AV_PAIRS_8B091
0ffff15c a CYREG_SFLASH_AV_PAIRS_8B092
0ffff15c a CYREG_SFLASH_AV_PAIRS_8B092
0ffff15d a CYREG_SFLASH_AV_PAIRS_8B093
0ffff15d a CYREG_SFLASH_AV_PAIRS_8B093
0ffff15e a CYREG_SFLASH_AV_PAIRS_8B094
0ffff15e a CYREG_SFLASH_AV_PAIRS_8B094
0ffff15f a CYREG_SFLASH_AV_PAIRS_8B095
0ffff15f a CYREG_SFLASH_AV_PAIRS_8B095
0ffff160 a CYREG_SFLASH_AV_PAIRS_8B096
0ffff160 a CYREG_SFLASH_AV_PAIRS_8B096
0ffff161 a CYREG_SFLASH_AV_PAIRS_8B097
0ffff161 a CYREG_SFLASH_AV_PAIRS_8B097
0ffff162 a CYREG_SFLASH_AV_PAIRS_8B098
0ffff162 a CYREG_SFLASH_AV_PAIRS_8B098
0ffff163 a CYREG_SFLASH_AV_PAIRS_8B099
0ffff163 a CYREG_SFLASH_AV_PAIRS_8B099
0ffff101 a CYREG_SFLASH_AV_PAIRS_8B1
0ffff101 a CYREG_SFLASH_AV_PAIRS_8B1
0ffff10a a CYREG_SFLASH_AV_PAIRS_8B10
0ffff10a a CYREG_SFLASH_AV_PAIRS_8B10
0ffff164 a CYREG_SFLASH_AV_PAIRS_8B100
0ffff164 a CYREG_SFLASH_AV_PAIRS_8B100
0ffff165 a CYREG_SFLASH_AV_PAIRS_8B101
0ffff165 a CYREG_SFLASH_AV_PAIRS_8B101
0ffff166 a CYREG_SFLASH_AV_PAIRS_8B102
0ffff166 a CYREG_SFLASH_AV_PAIRS_8B102
0ffff167 a CYREG_SFLASH_AV_PAIRS_8B103
0ffff167 a CYREG_SFLASH_AV_PAIRS_8B103
0ffff168 a CYREG_SFLASH_AV_PAIRS_8B104
0ffff168 a CYREG_SFLASH_AV_PAIRS_8B104
0ffff169 a CYREG_SFLASH_AV_PAIRS_8B105
0ffff169 a CYREG_SFLASH_AV_PAIRS_8B105
0ffff16a a CYREG_SFLASH_AV_PAIRS_8B106
0ffff16a a CYREG_SFLASH_AV_PAIRS_8B106
0ffff16b a CYREG_SFLASH_AV_PAIRS_8B107
0ffff16b a CYREG_SFLASH_AV_PAIRS_8B107
0ffff16c a CYREG_SFLASH_AV_PAIRS_8B108
0ffff16c a CYREG_SFLASH_AV_PAIRS_8B108
0ffff16d a CYREG_SFLASH_AV_PAIRS_8B109
0ffff16d a CYREG_SFLASH_AV_PAIRS_8B109
0ffff10b a CYREG_SFLASH_AV_PAIRS_8B11
0ffff10b a CYREG_SFLASH_AV_PAIRS_8B11
0ffff16e a CYREG_SFLASH_AV_PAIRS_8B110
0ffff16e a CYREG_SFLASH_AV_PAIRS_8B110
0ffff16f a CYREG_SFLASH_AV_PAIRS_8B111
0ffff16f a CYREG_SFLASH_AV_PAIRS_8B111
0ffff170 a CYREG_SFLASH_AV_PAIRS_8B112
0ffff170 a CYREG_SFLASH_AV_PAIRS_8B112
0ffff171 a CYREG_SFLASH_AV_PAIRS_8B113
0ffff171 a CYREG_SFLASH_AV_PAIRS_8B113
0ffff172 a CYREG_SFLASH_AV_PAIRS_8B114
0ffff172 a CYREG_SFLASH_AV_PAIRS_8B114
0ffff173 a CYREG_SFLASH_AV_PAIRS_8B115
0ffff173 a CYREG_SFLASH_AV_PAIRS_8B115
0ffff174 a CYREG_SFLASH_AV_PAIRS_8B116
0ffff174 a CYREG_SFLASH_AV_PAIRS_8B116
0ffff175 a CYREG_SFLASH_AV_PAIRS_8B117
0ffff175 a CYREG_SFLASH_AV_PAIRS_8B117
0ffff176 a CYREG_SFLASH_AV_PAIRS_8B118
0ffff176 a CYREG_SFLASH_AV_PAIRS_8B118
0ffff177 a CYREG_SFLASH_AV_PAIRS_8B119
0ffff177 a CYREG_SFLASH_AV_PAIRS_8B119
0ffff10c a CYREG_SFLASH_AV_PAIRS_8B12
0ffff10c a CYREG_SFLASH_AV_PAIRS_8B12
0ffff178 a CYREG_SFLASH_AV_PAIRS_8B120
0ffff178 a CYREG_SFLASH_AV_PAIRS_8B120
0ffff179 a CYREG_SFLASH_AV_PAIRS_8B121
0ffff179 a CYREG_SFLASH_AV_PAIRS_8B121
0ffff17a a CYREG_SFLASH_AV_PAIRS_8B122
0ffff17a a CYREG_SFLASH_AV_PAIRS_8B122
0ffff17b a CYREG_SFLASH_AV_PAIRS_8B123
0ffff17b a CYREG_SFLASH_AV_PAIRS_8B123
0ffff17c a CYREG_SFLASH_AV_PAIRS_8B124
0ffff17c a CYREG_SFLASH_AV_PAIRS_8B124
0ffff17d a CYREG_SFLASH_AV_PAIRS_8B125
0ffff17d a CYREG_SFLASH_AV_PAIRS_8B125
0ffff17e a CYREG_SFLASH_AV_PAIRS_8B126
0ffff17e a CYREG_SFLASH_AV_PAIRS_8B126
0ffff17f a CYREG_SFLASH_AV_PAIRS_8B127
0ffff17f a CYREG_SFLASH_AV_PAIRS_8B127
0ffff10d a CYREG_SFLASH_AV_PAIRS_8B13
0ffff10d a CYREG_SFLASH_AV_PAIRS_8B13
0ffff10e a CYREG_SFLASH_AV_PAIRS_8B14
0ffff10e a CYREG_SFLASH_AV_PAIRS_8B14
0ffff10f a CYREG_SFLASH_AV_PAIRS_8B15
0ffff10f a CYREG_SFLASH_AV_PAIRS_8B15
0ffff110 a CYREG_SFLASH_AV_PAIRS_8B16
0ffff110 a CYREG_SFLASH_AV_PAIRS_8B16
0ffff111 a CYREG_SFLASH_AV_PAIRS_8B17
0ffff111 a CYREG_SFLASH_AV_PAIRS_8B17
0ffff112 a CYREG_SFLASH_AV_PAIRS_8B18
0ffff112 a CYREG_SFLASH_AV_PAIRS_8B18
0ffff113 a CYREG_SFLASH_AV_PAIRS_8B19
0ffff113 a CYREG_SFLASH_AV_PAIRS_8B19
0ffff102 a CYREG_SFLASH_AV_PAIRS_8B2
0ffff102 a CYREG_SFLASH_AV_PAIRS_8B2
0ffff114 a CYREG_SFLASH_AV_PAIRS_8B20
0ffff114 a CYREG_SFLASH_AV_PAIRS_8B20
0ffff115 a CYREG_SFLASH_AV_PAIRS_8B21
0ffff115 a CYREG_SFLASH_AV_PAIRS_8B21
0ffff116 a CYREG_SFLASH_AV_PAIRS_8B22
0ffff116 a CYREG_SFLASH_AV_PAIRS_8B22
0ffff117 a CYREG_SFLASH_AV_PAIRS_8B23
0ffff117 a CYREG_SFLASH_AV_PAIRS_8B23
0ffff118 a CYREG_SFLASH_AV_PAIRS_8B24
0ffff118 a CYREG_SFLASH_AV_PAIRS_8B24
0ffff119 a CYREG_SFLASH_AV_PAIRS_8B25
0ffff119 a CYREG_SFLASH_AV_PAIRS_8B25
0ffff11a a CYREG_SFLASH_AV_PAIRS_8B26
0ffff11a a CYREG_SFLASH_AV_PAIRS_8B26
0ffff11b a CYREG_SFLASH_AV_PAIRS_8B27
0ffff11b a CYREG_SFLASH_AV_PAIRS_8B27
0ffff11c a CYREG_SFLASH_AV_PAIRS_8B28
0ffff11c a CYREG_SFLASH_AV_PAIRS_8B28
0ffff11d a CYREG_SFLASH_AV_PAIRS_8B29
0ffff11d a CYREG_SFLASH_AV_PAIRS_8B29
0ffff103 a CYREG_SFLASH_AV_PAIRS_8B3
0ffff103 a CYREG_SFLASH_AV_PAIRS_8B3
0ffff11e a CYREG_SFLASH_AV_PAIRS_8B30
0ffff11e a CYREG_SFLASH_AV_PAIRS_8B30
0ffff11f a CYREG_SFLASH_AV_PAIRS_8B31
0ffff11f a CYREG_SFLASH_AV_PAIRS_8B31
0ffff120 a CYREG_SFLASH_AV_PAIRS_8B32
0ffff120 a CYREG_SFLASH_AV_PAIRS_8B32
0ffff121 a CYREG_SFLASH_AV_PAIRS_8B33
0ffff121 a CYREG_SFLASH_AV_PAIRS_8B33
0ffff122 a CYREG_SFLASH_AV_PAIRS_8B34
0ffff122 a CYREG_SFLASH_AV_PAIRS_8B34
0ffff123 a CYREG_SFLASH_AV_PAIRS_8B35
0ffff123 a CYREG_SFLASH_AV_PAIRS_8B35
0ffff124 a CYREG_SFLASH_AV_PAIRS_8B36
0ffff124 a CYREG_SFLASH_AV_PAIRS_8B36
0ffff125 a CYREG_SFLASH_AV_PAIRS_8B37
0ffff125 a CYREG_SFLASH_AV_PAIRS_8B37
0ffff126 a CYREG_SFLASH_AV_PAIRS_8B38
0ffff126 a CYREG_SFLASH_AV_PAIRS_8B38
0ffff127 a CYREG_SFLASH_AV_PAIRS_8B39
0ffff127 a CYREG_SFLASH_AV_PAIRS_8B39
0ffff104 a CYREG_SFLASH_AV_PAIRS_8B4
0ffff104 a CYREG_SFLASH_AV_PAIRS_8B4
0ffff128 a CYREG_SFLASH_AV_PAIRS_8B40
0ffff128 a CYREG_SFLASH_AV_PAIRS_8B40
0ffff129 a CYREG_SFLASH_AV_PAIRS_8B41
0ffff129 a CYREG_SFLASH_AV_PAIRS_8B41
0ffff12a a CYREG_SFLASH_AV_PAIRS_8B42
0ffff12a a CYREG_SFLASH_AV_PAIRS_8B42
0ffff12b a CYREG_SFLASH_AV_PAIRS_8B43
0ffff12b a CYREG_SFLASH_AV_PAIRS_8B43
0ffff12c a CYREG_SFLASH_AV_PAIRS_8B44
0ffff12c a CYREG_SFLASH_AV_PAIRS_8B44
0ffff12d a CYREG_SFLASH_AV_PAIRS_8B45
0ffff12d a CYREG_SFLASH_AV_PAIRS_8B45
0ffff12e a CYREG_SFLASH_AV_PAIRS_8B46
0ffff12e a CYREG_SFLASH_AV_PAIRS_8B46
0ffff12f a CYREG_SFLASH_AV_PAIRS_8B47
0ffff12f a CYREG_SFLASH_AV_PAIRS_8B47
0ffff130 a CYREG_SFLASH_AV_PAIRS_8B48
0ffff130 a CYREG_SFLASH_AV_PAIRS_8B48
0ffff131 a CYREG_SFLASH_AV_PAIRS_8B49
0ffff131 a CYREG_SFLASH_AV_PAIRS_8B49
0ffff105 a CYREG_SFLASH_AV_PAIRS_8B5
0ffff105 a CYREG_SFLASH_AV_PAIRS_8B5
0ffff132 a CYREG_SFLASH_AV_PAIRS_8B50
0ffff132 a CYREG_SFLASH_AV_PAIRS_8B50
0ffff133 a CYREG_SFLASH_AV_PAIRS_8B51
0ffff133 a CYREG_SFLASH_AV_PAIRS_8B51
0ffff134 a CYREG_SFLASH_AV_PAIRS_8B52
0ffff134 a CYREG_SFLASH_AV_PAIRS_8B52
0ffff135 a CYREG_SFLASH_AV_PAIRS_8B53
0ffff135 a CYREG_SFLASH_AV_PAIRS_8B53
0ffff136 a CYREG_SFLASH_AV_PAIRS_8B54
0ffff136 a CYREG_SFLASH_AV_PAIRS_8B54
0ffff137 a CYREG_SFLASH_AV_PAIRS_8B55
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0ffff138 a CYREG_SFLASH_AV_PAIRS_8B56
0ffff138 a CYREG_SFLASH_AV_PAIRS_8B56
0ffff139 a CYREG_SFLASH_AV_PAIRS_8B57
0ffff139 a CYREG_SFLASH_AV_PAIRS_8B57
0ffff13a a CYREG_SFLASH_AV_PAIRS_8B58
0ffff13a a CYREG_SFLASH_AV_PAIRS_8B58
0ffff13b a CYREG_SFLASH_AV_PAIRS_8B59
0ffff13b a CYREG_SFLASH_AV_PAIRS_8B59
0ffff106 a CYREG_SFLASH_AV_PAIRS_8B6
0ffff106 a CYREG_SFLASH_AV_PAIRS_8B6
0ffff13c a CYREG_SFLASH_AV_PAIRS_8B60
0ffff13c a CYREG_SFLASH_AV_PAIRS_8B60
0ffff13d a CYREG_SFLASH_AV_PAIRS_8B61
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0ffff13e a CYREG_SFLASH_AV_PAIRS_8B62
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0ffff13f a CYREG_SFLASH_AV_PAIRS_8B63
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0ffff140 a CYREG_SFLASH_AV_PAIRS_8B64
0ffff140 a CYREG_SFLASH_AV_PAIRS_8B64
0ffff141 a CYREG_SFLASH_AV_PAIRS_8B65
0ffff141 a CYREG_SFLASH_AV_PAIRS_8B65
0ffff142 a CYREG_SFLASH_AV_PAIRS_8B66
0ffff142 a CYREG_SFLASH_AV_PAIRS_8B66
0ffff143 a CYREG_SFLASH_AV_PAIRS_8B67
0ffff143 a CYREG_SFLASH_AV_PAIRS_8B67
0ffff144 a CYREG_SFLASH_AV_PAIRS_8B68
0ffff144 a CYREG_SFLASH_AV_PAIRS_8B68
0ffff145 a CYREG_SFLASH_AV_PAIRS_8B69
0ffff145 a CYREG_SFLASH_AV_PAIRS_8B69
0ffff107 a CYREG_SFLASH_AV_PAIRS_8B7
0ffff107 a CYREG_SFLASH_AV_PAIRS_8B7
0ffff146 a CYREG_SFLASH_AV_PAIRS_8B70
0ffff146 a CYREG_SFLASH_AV_PAIRS_8B70
0ffff147 a CYREG_SFLASH_AV_PAIRS_8B71
0ffff147 a CYREG_SFLASH_AV_PAIRS_8B71
0ffff148 a CYREG_SFLASH_AV_PAIRS_8B72
0ffff148 a CYREG_SFLASH_AV_PAIRS_8B72
0ffff149 a CYREG_SFLASH_AV_PAIRS_8B73
0ffff149 a CYREG_SFLASH_AV_PAIRS_8B73
0ffff14a a CYREG_SFLASH_AV_PAIRS_8B74
0ffff14a a CYREG_SFLASH_AV_PAIRS_8B74
0ffff14b a CYREG_SFLASH_AV_PAIRS_8B75
0ffff14b a CYREG_SFLASH_AV_PAIRS_8B75
0ffff14c a CYREG_SFLASH_AV_PAIRS_8B76
0ffff14c a CYREG_SFLASH_AV_PAIRS_8B76
0ffff14d a CYREG_SFLASH_AV_PAIRS_8B77
0ffff14d a CYREG_SFLASH_AV_PAIRS_8B77
0ffff14e a CYREG_SFLASH_AV_PAIRS_8B78
0ffff14e a CYREG_SFLASH_AV_PAIRS_8B78
0ffff14f a CYREG_SFLASH_AV_PAIRS_8B79
0ffff14f a CYREG_SFLASH_AV_PAIRS_8B79
0ffff108 a CYREG_SFLASH_AV_PAIRS_8B8
0ffff108 a CYREG_SFLASH_AV_PAIRS_8B8
0ffff150 a CYREG_SFLASH_AV_PAIRS_8B80
0ffff150 a CYREG_SFLASH_AV_PAIRS_8B80
0ffff151 a CYREG_SFLASH_AV_PAIRS_8B81
0ffff151 a CYREG_SFLASH_AV_PAIRS_8B81
0ffff152 a CYREG_SFLASH_AV_PAIRS_8B82
0ffff152 a CYREG_SFLASH_AV_PAIRS_8B82
0ffff153 a CYREG_SFLASH_AV_PAIRS_8B83
0ffff153 a CYREG_SFLASH_AV_PAIRS_8B83
0ffff154 a CYREG_SFLASH_AV_PAIRS_8B84
0ffff154 a CYREG_SFLASH_AV_PAIRS_8B84
0ffff155 a CYREG_SFLASH_AV_PAIRS_8B85
0ffff155 a CYREG_SFLASH_AV_PAIRS_8B85
0ffff156 a CYREG_SFLASH_AV_PAIRS_8B86
0ffff156 a CYREG_SFLASH_AV_PAIRS_8B86
0ffff157 a CYREG_SFLASH_AV_PAIRS_8B87
0ffff157 a CYREG_SFLASH_AV_PAIRS_8B87
0ffff158 a CYREG_SFLASH_AV_PAIRS_8B88
0ffff158 a CYREG_SFLASH_AV_PAIRS_8B88
0ffff159 a CYREG_SFLASH_AV_PAIRS_8B89
0ffff159 a CYREG_SFLASH_AV_PAIRS_8B89
0ffff109 a CYREG_SFLASH_AV_PAIRS_8B9
0ffff109 a CYREG_SFLASH_AV_PAIRS_8B9
0ffff15a a CYREG_SFLASH_AV_PAIRS_8B90
0ffff15a a CYREG_SFLASH_AV_PAIRS_8B90
0ffff15b a CYREG_SFLASH_AV_PAIRS_8B91
0ffff15b a CYREG_SFLASH_AV_PAIRS_8B91
0ffff15c a CYREG_SFLASH_AV_PAIRS_8B92
0ffff15c a CYREG_SFLASH_AV_PAIRS_8B92
0ffff15d a CYREG_SFLASH_AV_PAIRS_8B93
0ffff15d a CYREG_SFLASH_AV_PAIRS_8B93
0ffff15e a CYREG_SFLASH_AV_PAIRS_8B94
0ffff15e a CYREG_SFLASH_AV_PAIRS_8B94
0ffff15f a CYREG_SFLASH_AV_PAIRS_8B95
0ffff15f a CYREG_SFLASH_AV_PAIRS_8B95
0ffff160 a CYREG_SFLASH_AV_PAIRS_8B96
0ffff160 a CYREG_SFLASH_AV_PAIRS_8B96
0ffff161 a CYREG_SFLASH_AV_PAIRS_8B97
0ffff161 a CYREG_SFLASH_AV_PAIRS_8B97
0ffff162 a CYREG_SFLASH_AV_PAIRS_8B98
0ffff162 a CYREG_SFLASH_AV_PAIRS_8B98
0ffff163 a CYREG_SFLASH_AV_PAIRS_8B99
0ffff163 a CYREG_SFLASH_AV_PAIRS_8B99
0ffff26c a CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0
0ffff26c a CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0
0ffff26d a CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1
0ffff26d a CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1
0ffff26e a CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0
0ffff26e a CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0
0ffff26f a CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1
0ffff26f a CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1
0ffff158 a CYREG_SFLASH_BLESS_BB_BUMP2
0ffff158 a CYREG_SFLASH_BLESS_BB_BUMP2
0ffff15a a CYREG_SFLASH_BLESS_BB_XO
0ffff15a a CYREG_SFLASH_BLESS_BB_XO
0ffff15e a CYREG_SFLASH_BLESS_LDO
0ffff15e a CYREG_SFLASH_BLESS_LDO
0ffff15c a CYREG_SFLASH_BLESS_SY_BUMP1
0ffff15c a CYREG_SFLASH_BLESS_SY_BUMP1
0ffff262 a CYREG_SFLASH_CSD_TRIM1_CSD
0ffff262 a CYREG_SFLASH_CSD_TRIM1_CSD
0ffff260 a CYREG_SFLASH_CSD_TRIM1_HVIDAC
0ffff260 a CYREG_SFLASH_CSD_TRIM1_HVIDAC
0ffff263 a CYREG_SFLASH_CSD_TRIM2_CSD
0ffff263 a CYREG_SFLASH_CSD_TRIM2_CSD
0ffff261 a CYREG_SFLASH_CSD_TRIM2_HVIDAC
0ffff261 a CYREG_SFLASH_CSD_TRIM2_HVIDAC
0ffff278 a CYREG_SFLASH_DIE_LOT0
0ffff278 a CYREG_SFLASH_DIE_LOT0
0ffff279 a CYREG_SFLASH_DIE_LOT1
0ffff279 a CYREG_SFLASH_DIE_LOT1
0ffff27a a CYREG_SFLASH_DIE_LOT2
0ffff27a a CYREG_SFLASH_DIE_LOT2
0ffff27f a CYREG_SFLASH_DIE_MINOR
0ffff27f a CYREG_SFLASH_DIE_MINOR
0ffff27e a CYREG_SFLASH_DIE_SORT
0ffff27e a CYREG_SFLASH_DIE_SORT
0ffff27b a CYREG_SFLASH_DIE_WAFER
0ffff27b a CYREG_SFLASH_DIE_WAFER
0ffff27c a CYREG_SFLASH_DIE_X
0ffff27c a CYREG_SFLASH_DIE_X
0ffff27d a CYREG_SFLASH_DIE_Y
0ffff27d a CYREG_SFLASH_DIE_Y
0ffff252 a CYREG_SFLASH_DPSLP_KEY_DELAY
0ffff252 a CYREG_SFLASH_DPSLP_KEY_DELAY
0ffff25c a CYREG_SFLASH_FLASH_START
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0ffff250 a CYREG_SFLASH_HIB_KEY_DELAY
0ffff250 a CYREG_SFLASH_HIB_KEY_DELAY
0ffff341 a CYREG_SFLASH_IMO_ABS0
0ffff341 a CYREG_SFLASH_IMO_ABS0
0ffff344 a CYREG_SFLASH_IMO_ABS1
0ffff344 a CYREG_SFLASH_IMO_ABS1
0ffff347 a CYREG_SFLASH_IMO_ABS2
0ffff347 a CYREG_SFLASH_IMO_ABS2
0ffff34a a CYREG_SFLASH_IMO_ABS3
0ffff34a a CYREG_SFLASH_IMO_ABS3
0ffff34c a CYREG_SFLASH_IMO_ABS4
0ffff34c a CYREG_SFLASH_IMO_ABS4
0ffff340 a CYREG_SFLASH_IMO_MAXF0
0ffff340 a CYREG_SFLASH_IMO_MAXF0
0ffff343 a CYREG_SFLASH_IMO_MAXF1
0ffff343 a CYREG_SFLASH_IMO_MAXF1
0ffff346 a CYREG_SFLASH_IMO_MAXF2
0ffff346 a CYREG_SFLASH_IMO_MAXF2
0ffff349 a CYREG_SFLASH_IMO_MAXF3
0ffff349 a CYREG_SFLASH_IMO_MAXF3
0ffff342 a CYREG_SFLASH_IMO_TMPCO0
0ffff342 a CYREG_SFLASH_IMO_TMPCO0
0ffff345 a CYREG_SFLASH_IMO_TMPCO1
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0ffff348 a CYREG_SFLASH_IMO_TMPCO2
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0ffff34b a CYREG_SFLASH_IMO_TMPCO3
0ffff34b a CYREG_SFLASH_IMO_TMPCO3
0ffff34d a CYREG_SFLASH_IMO_TMPCO4
0ffff34d a CYREG_SFLASH_IMO_TMPCO4
0ffff33e a CYREG_SFLASH_IMO_TRIM_USBMODE_24
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0ffff33f a CYREG_SFLASH_IMO_TRIM_USBMODE_48
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0ffff350 a CYREG_SFLASH_IMO_TRIM0
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0ffff350 a CYREG_SFLASH_IMO_TRIM00
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0ffff351 a CYREG_SFLASH_IMO_TRIM01
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0ffff352 a CYREG_SFLASH_IMO_TRIM02
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0ffff355 a CYREG_SFLASH_IMO_TRIM05
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0ffff356 a CYREG_SFLASH_IMO_TRIM06
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0ffff357 a CYREG_SFLASH_IMO_TRIM07
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0ffff358 a CYREG_SFLASH_IMO_TRIM08
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0ffff359 a CYREG_SFLASH_IMO_TRIM09
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0ffff351 a CYREG_SFLASH_IMO_TRIM1
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0ffff35a a CYREG_SFLASH_IMO_TRIM10
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0ffff35b a CYREG_SFLASH_IMO_TRIM11
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0ffff35f a CYREG_SFLASH_IMO_TRIM15
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0ffff360 a CYREG_SFLASH_IMO_TRIM16
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0ffff361 a CYREG_SFLASH_IMO_TRIM17
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0ffff362 a CYREG_SFLASH_IMO_TRIM18
0ffff362 a CYREG_SFLASH_IMO_TRIM18
0ffff363 a CYREG_SFLASH_IMO_TRIM19
0ffff363 a CYREG_SFLASH_IMO_TRIM19
0ffff352 a CYREG_SFLASH_IMO_TRIM2
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0ffff364 a CYREG_SFLASH_IMO_TRIM20
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0ffff365 a CYREG_SFLASH_IMO_TRIM21
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0ffff366 a CYREG_SFLASH_IMO_TRIM22
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0ffff367 a CYREG_SFLASH_IMO_TRIM23
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0ffff368 a CYREG_SFLASH_IMO_TRIM24
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0ffff369 a CYREG_SFLASH_IMO_TRIM25
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0ffff36a a CYREG_SFLASH_IMO_TRIM26
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0ffff36b a CYREG_SFLASH_IMO_TRIM27
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0ffff36c a CYREG_SFLASH_IMO_TRIM28
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0ffff36d a CYREG_SFLASH_IMO_TRIM29
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0ffff353 a CYREG_SFLASH_IMO_TRIM3
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0ffff36e a CYREG_SFLASH_IMO_TRIM30
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0ffff36f a CYREG_SFLASH_IMO_TRIM31
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0ffff370 a CYREG_SFLASH_IMO_TRIM32
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0ffff371 a CYREG_SFLASH_IMO_TRIM33
0ffff371 a CYREG_SFLASH_IMO_TRIM33
0ffff372 a CYREG_SFLASH_IMO_TRIM34
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0ffff373 a CYREG_SFLASH_IMO_TRIM35
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0ffff374 a CYREG_SFLASH_IMO_TRIM36
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0ffff375 a CYREG_SFLASH_IMO_TRIM37
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0ffff376 a CYREG_SFLASH_IMO_TRIM38
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0ffff377 a CYREG_SFLASH_IMO_TRIM39
0ffff377 a CYREG_SFLASH_IMO_TRIM39
0ffff354 a CYREG_SFLASH_IMO_TRIM4
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0ffff378 a CYREG_SFLASH_IMO_TRIM40
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0ffff379 a CYREG_SFLASH_IMO_TRIM41
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0ffff355 a CYREG_SFLASH_IMO_TRIM5
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0ffff356 a CYREG_SFLASH_IMO_TRIM6
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0ffff357 a CYREG_SFLASH_IMO_TRIM7
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0ffff358 a CYREG_SFLASH_IMO_TRIM8
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0ffff359 a CYREG_SFLASH_IMO_TRIM9
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0ffff255 a CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0
0ffff255 a CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0
0ffff400 a CYREG_SFLASH_MACRO_0_FREE_SFLASH0
0ffff400 a CYREG_SFLASH_MACRO_0_FREE_SFLASH0
0ffff401 a CYREG_SFLASH_MACRO_0_FREE_SFLASH1
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0ffff40a a CYREG_SFLASH_MACRO_0_FREE_SFLASH10
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0ffff464 a CYREG_SFLASH_MACRO_0_FREE_SFLASH100
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0ffff7eb a CYREG_SFLASH_MACRO_0_FREE_SFLASH1003
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0ffff7ed a CYREG_SFLASH_MACRO_0_FREE_SFLASH1005
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0ffff7f0 a CYREG_SFLASH_MACRO_0_FREE_SFLASH1008
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0ffff465 a CYREG_SFLASH_MACRO_0_FREE_SFLASH101
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         U CYREG_SFLASH_PE_TE_DATA0
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         U CYREG_SFLASH_PE_TE_DATA6
         U CYREG_SFLASH_PE_TE_DATA7
         U CYREG_SFLASH_PE_TE_DATA8
         U CYREG_SFLASH_PE_TE_DATA9
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0ffff01e a CYREG_SFLASH_PROT_ROW30
0ffff01f a CYREG_SFLASH_PROT_ROW31
0ffff01f a CYREG_SFLASH_PROT_ROW31
0ffff020 a CYREG_SFLASH_PROT_ROW32
0ffff020 a CYREG_SFLASH_PROT_ROW32
0ffff021 a CYREG_SFLASH_PROT_ROW33
0ffff021 a CYREG_SFLASH_PROT_ROW33
0ffff022 a CYREG_SFLASH_PROT_ROW34
0ffff022 a CYREG_SFLASH_PROT_ROW34
0ffff023 a CYREG_SFLASH_PROT_ROW35
0ffff023 a CYREG_SFLASH_PROT_ROW35
0ffff024 a CYREG_SFLASH_PROT_ROW36
0ffff024 a CYREG_SFLASH_PROT_ROW36
0ffff025 a CYREG_SFLASH_PROT_ROW37
0ffff025 a CYREG_SFLASH_PROT_ROW37
0ffff026 a CYREG_SFLASH_PROT_ROW38
0ffff026 a CYREG_SFLASH_PROT_ROW38
0ffff027 a CYREG_SFLASH_PROT_ROW39
0ffff027 a CYREG_SFLASH_PROT_ROW39
0ffff004 a CYREG_SFLASH_PROT_ROW4
0ffff004 a CYREG_SFLASH_PROT_ROW4
0ffff028 a CYREG_SFLASH_PROT_ROW40
0ffff028 a CYREG_SFLASH_PROT_ROW40
0ffff029 a CYREG_SFLASH_PROT_ROW41
0ffff029 a CYREG_SFLASH_PROT_ROW41
0ffff02a a CYREG_SFLASH_PROT_ROW42
0ffff02a a CYREG_SFLASH_PROT_ROW42
0ffff02b a CYREG_SFLASH_PROT_ROW43
0ffff02b a CYREG_SFLASH_PROT_ROW43
0ffff02c a CYREG_SFLASH_PROT_ROW44
0ffff02c a CYREG_SFLASH_PROT_ROW44
0ffff02d a CYREG_SFLASH_PROT_ROW45
0ffff02d a CYREG_SFLASH_PROT_ROW45
0ffff02e a CYREG_SFLASH_PROT_ROW46
0ffff02e a CYREG_SFLASH_PROT_ROW46
0ffff02f a CYREG_SFLASH_PROT_ROW47
0ffff02f a CYREG_SFLASH_PROT_ROW47
0ffff030 a CYREG_SFLASH_PROT_ROW48
0ffff030 a CYREG_SFLASH_PROT_ROW48
0ffff031 a CYREG_SFLASH_PROT_ROW49
0ffff031 a CYREG_SFLASH_PROT_ROW49
0ffff005 a CYREG_SFLASH_PROT_ROW5
0ffff005 a CYREG_SFLASH_PROT_ROW5
0ffff032 a CYREG_SFLASH_PROT_ROW50
0ffff032 a CYREG_SFLASH_PROT_ROW50
0ffff033 a CYREG_SFLASH_PROT_ROW51
0ffff033 a CYREG_SFLASH_PROT_ROW51
0ffff034 a CYREG_SFLASH_PROT_ROW52
0ffff034 a CYREG_SFLASH_PROT_ROW52
0ffff035 a CYREG_SFLASH_PROT_ROW53
0ffff035 a CYREG_SFLASH_PROT_ROW53
0ffff036 a CYREG_SFLASH_PROT_ROW54
0ffff036 a CYREG_SFLASH_PROT_ROW54
0ffff037 a CYREG_SFLASH_PROT_ROW55
0ffff037 a CYREG_SFLASH_PROT_ROW55
0ffff038 a CYREG_SFLASH_PROT_ROW56
0ffff038 a CYREG_SFLASH_PROT_ROW56
0ffff039 a CYREG_SFLASH_PROT_ROW57
0ffff039 a CYREG_SFLASH_PROT_ROW57
0ffff03a a CYREG_SFLASH_PROT_ROW58
0ffff03a a CYREG_SFLASH_PROT_ROW58
0ffff03b a CYREG_SFLASH_PROT_ROW59
0ffff03b a CYREG_SFLASH_PROT_ROW59
0ffff006 a CYREG_SFLASH_PROT_ROW6
0ffff006 a CYREG_SFLASH_PROT_ROW6
0ffff03c a CYREG_SFLASH_PROT_ROW60
0ffff03c a CYREG_SFLASH_PROT_ROW60
0ffff03d a CYREG_SFLASH_PROT_ROW61
0ffff03d a CYREG_SFLASH_PROT_ROW61
0ffff03e a CYREG_SFLASH_PROT_ROW62
0ffff03e a CYREG_SFLASH_PROT_ROW62
0ffff03f a CYREG_SFLASH_PROT_ROW63
0ffff03f a CYREG_SFLASH_PROT_ROW63
0ffff007 a CYREG_SFLASH_PROT_ROW7
0ffff007 a CYREG_SFLASH_PROT_ROW7
0ffff008 a CYREG_SFLASH_PROT_ROW8
0ffff008 a CYREG_SFLASH_PROT_ROW8
0ffff009 a CYREG_SFLASH_PROT_ROW9
0ffff009 a CYREG_SFLASH_PROT_ROW9
0ffff270 a CYREG_SFLASH_PROT_VIRGINKEY0
0ffff270 a CYREG_SFLASH_PROT_VIRGINKEY0
0ffff271 a CYREG_SFLASH_PROT_VIRGINKEY1
0ffff271 a CYREG_SFLASH_PROT_VIRGINKEY1
0ffff272 a CYREG_SFLASH_PROT_VIRGINKEY2
0ffff272 a CYREG_SFLASH_PROT_VIRGINKEY2
0ffff273 a CYREG_SFLASH_PROT_VIRGINKEY3
0ffff273 a CYREG_SFLASH_PROT_VIRGINKEY3
0ffff274 a CYREG_SFLASH_PROT_VIRGINKEY4
0ffff274 a CYREG_SFLASH_PROT_VIRGINKEY4
0ffff275 a CYREG_SFLASH_PROT_VIRGINKEY5
0ffff275 a CYREG_SFLASH_PROT_VIRGINKEY5
0ffff276 a CYREG_SFLASH_PROT_VIRGINKEY6
0ffff276 a CYREG_SFLASH_PROT_VIRGINKEY6
0ffff277 a CYREG_SFLASH_PROT_VIRGINKEY7
0ffff277 a CYREG_SFLASH_PROT_VIRGINKEY7
0ffff264 a CYREG_SFLASH_SAR_TEMP_MULTIPLIER
0ffff264 a CYREG_SFLASH_SAR_TEMP_MULTIPLIER
0ffff266 a CYREG_SFLASH_SAR_TEMP_OFFSET
0ffff266 a CYREG_SFLASH_SAR_TEMP_OFFSET
0ffff244 a CYREG_SFLASH_SILICON_ID
0ffff244 a CYREG_SFLASH_SILICON_ID
0ffff254 a CYREG_SFLASH_SWD_CONFIG
0ffff254 a CYREG_SFLASH_SWD_CONFIG
0ffff258 a CYREG_SFLASH_SWD_LISTEN
0ffff258 a CYREG_SFLASH_SWD_LISTEN
40110000 a CYREG_SPCIF_GEOMETRY
40110000 a CYREG_SPCIF_GEOMETRY
401107f0 a CYREG_SPCIF_INTR
401107f0 a CYREG_SPCIF_INTR
401107f8 a CYREG_SPCIF_INTR_MASK
401107f8 a CYREG_SPCIF_INTR_MASK
401107fc a CYREG_SPCIF_INTR_MASKED
401107fc a CYREG_SPCIF_INTR_MASKED
401107f4 a CYREG_SPCIF_INTR_SET
401107f4 a CYREG_SPCIF_INTR_SET
4011001c a CYREG_SPCIF_NVL_WR_DATA
4011001c a CYREG_SPCIF_NVL_WR_DATA
20000000 a CYREG_SRAM_DATA_MBASE
20000000 a CYREG_SRAM_DATA_MBASE
00008000 a CYREG_SRAM_DATA_MSIZE
00008000 a CYREG_SRAM_DATA_MSIZE
40200008 a CYREG_TCPWM_CMD
40200008 a CYREG_TCPWM_CMD
4020010c a CYREG_TCPWM_CNT0_CC
4020010c a CYREG_TCPWM_CNT0_CC
40200110 a CYREG_TCPWM_CNT0_CC_BUFF
40200110 a CYREG_TCPWM_CNT0_CC_BUFF
40200108 a CYREG_TCPWM_CNT0_COUNTER
40200108 a CYREG_TCPWM_CNT0_COUNTER
40200100 a CYREG_TCPWM_CNT0_CTRL
40200100 a CYREG_TCPWM_CNT0_CTRL
40200130 a CYREG_TCPWM_CNT0_INTR
40200130 a CYREG_TCPWM_CNT0_INTR
40200138 a CYREG_TCPWM_CNT0_INTR_MASK
40200138 a CYREG_TCPWM_CNT0_INTR_MASK
4020013c a CYREG_TCPWM_CNT0_INTR_MASKED
4020013c a CYREG_TCPWM_CNT0_INTR_MASKED
40200134 a CYREG_TCPWM_CNT0_INTR_SET
40200134 a CYREG_TCPWM_CNT0_INTR_SET
40200114 a CYREG_TCPWM_CNT0_PERIOD
40200114 a CYREG_TCPWM_CNT0_PERIOD
40200118 a CYREG_TCPWM_CNT0_PERIOD_BUFF
40200118 a CYREG_TCPWM_CNT0_PERIOD_BUFF
40200104 a CYREG_TCPWM_CNT0_STATUS
40200104 a CYREG_TCPWM_CNT0_STATUS
40200120 a CYREG_TCPWM_CNT0_TR_CTRL0
40200120 a CYREG_TCPWM_CNT0_TR_CTRL0
40200124 a CYREG_TCPWM_CNT0_TR_CTRL1
40200124 a CYREG_TCPWM_CNT0_TR_CTRL1
40200128 a CYREG_TCPWM_CNT0_TR_CTRL2
40200128 a CYREG_TCPWM_CNT0_TR_CTRL2
4020014c a CYREG_TCPWM_CNT1_CC
4020014c a CYREG_TCPWM_CNT1_CC
40200150 a CYREG_TCPWM_CNT1_CC_BUFF
40200150 a CYREG_TCPWM_CNT1_CC_BUFF
40200148 a CYREG_TCPWM_CNT1_COUNTER
40200148 a CYREG_TCPWM_CNT1_COUNTER
40200140 a CYREG_TCPWM_CNT1_CTRL
40200140 a CYREG_TCPWM_CNT1_CTRL
40200170 a CYREG_TCPWM_CNT1_INTR
40200170 a CYREG_TCPWM_CNT1_INTR
40200178 a CYREG_TCPWM_CNT1_INTR_MASK
40200178 a CYREG_TCPWM_CNT1_INTR_MASK
4020017c a CYREG_TCPWM_CNT1_INTR_MASKED
4020017c a CYREG_TCPWM_CNT1_INTR_MASKED
40200174 a CYREG_TCPWM_CNT1_INTR_SET
40200174 a CYREG_TCPWM_CNT1_INTR_SET
40200154 a CYREG_TCPWM_CNT1_PERIOD
40200154 a CYREG_TCPWM_CNT1_PERIOD
40200158 a CYREG_TCPWM_CNT1_PERIOD_BUFF
40200158 a CYREG_TCPWM_CNT1_PERIOD_BUFF
40200144 a CYREG_TCPWM_CNT1_STATUS
40200144 a CYREG_TCPWM_CNT1_STATUS
40200160 a CYREG_TCPWM_CNT1_TR_CTRL0
40200160 a CYREG_TCPWM_CNT1_TR_CTRL0
40200164 a CYREG_TCPWM_CNT1_TR_CTRL1
40200164 a CYREG_TCPWM_CNT1_TR_CTRL1
40200168 a CYREG_TCPWM_CNT1_TR_CTRL2
40200168 a CYREG_TCPWM_CNT1_TR_CTRL2
4020018c a CYREG_TCPWM_CNT2_CC
4020018c a CYREG_TCPWM_CNT2_CC
40200190 a CYREG_TCPWM_CNT2_CC_BUFF
40200190 a CYREG_TCPWM_CNT2_CC_BUFF
40200188 a CYREG_TCPWM_CNT2_COUNTER
40200188 a CYREG_TCPWM_CNT2_COUNTER
40200180 a CYREG_TCPWM_CNT2_CTRL
40200180 a CYREG_TCPWM_CNT2_CTRL
402001b0 a CYREG_TCPWM_CNT2_INTR
402001b0 a CYREG_TCPWM_CNT2_INTR
402001b8 a CYREG_TCPWM_CNT2_INTR_MASK
402001b8 a CYREG_TCPWM_CNT2_INTR_MASK
402001bc a CYREG_TCPWM_CNT2_INTR_MASKED
402001bc a CYREG_TCPWM_CNT2_INTR_MASKED
402001b4 a CYREG_TCPWM_CNT2_INTR_SET
402001b4 a CYREG_TCPWM_CNT2_INTR_SET
40200194 a CYREG_TCPWM_CNT2_PERIOD
40200194 a CYREG_TCPWM_CNT2_PERIOD
40200198 a CYREG_TCPWM_CNT2_PERIOD_BUFF
40200198 a CYREG_TCPWM_CNT2_PERIOD_BUFF
40200184 a CYREG_TCPWM_CNT2_STATUS
40200184 a CYREG_TCPWM_CNT2_STATUS
402001a0 a CYREG_TCPWM_CNT2_TR_CTRL0
402001a0 a CYREG_TCPWM_CNT2_TR_CTRL0
402001a4 a CYREG_TCPWM_CNT2_TR_CTRL1
402001a4 a CYREG_TCPWM_CNT2_TR_CTRL1
402001a8 a CYREG_TCPWM_CNT2_TR_CTRL2
402001a8 a CYREG_TCPWM_CNT2_TR_CTRL2
402001cc a CYREG_TCPWM_CNT3_CC
402001cc a CYREG_TCPWM_CNT3_CC
402001d0 a CYREG_TCPWM_CNT3_CC_BUFF
402001d0 a CYREG_TCPWM_CNT3_CC_BUFF
402001c8 a CYREG_TCPWM_CNT3_COUNTER
402001c8 a CYREG_TCPWM_CNT3_COUNTER
402001c0 a CYREG_TCPWM_CNT3_CTRL
402001c0 a CYREG_TCPWM_CNT3_CTRL
402001f0 a CYREG_TCPWM_CNT3_INTR
402001f0 a CYREG_TCPWM_CNT3_INTR
402001f8 a CYREG_TCPWM_CNT3_INTR_MASK
402001f8 a CYREG_TCPWM_CNT3_INTR_MASK
402001fc a CYREG_TCPWM_CNT3_INTR_MASKED
402001fc a CYREG_TCPWM_CNT3_INTR_MASKED
402001f4 a CYREG_TCPWM_CNT3_INTR_SET
402001f4 a CYREG_TCPWM_CNT3_INTR_SET
402001d4 a CYREG_TCPWM_CNT3_PERIOD
402001d4 a CYREG_TCPWM_CNT3_PERIOD
402001d8 a CYREG_TCPWM_CNT3_PERIOD_BUFF
402001d8 a CYREG_TCPWM_CNT3_PERIOD_BUFF
402001c4 a CYREG_TCPWM_CNT3_STATUS
402001c4 a CYREG_TCPWM_CNT3_STATUS
402001e0 a CYREG_TCPWM_CNT3_TR_CTRL0
402001e0 a CYREG_TCPWM_CNT3_TR_CTRL0
402001e4 a CYREG_TCPWM_CNT3_TR_CTRL1
402001e4 a CYREG_TCPWM_CNT3_TR_CTRL1
402001e8 a CYREG_TCPWM_CNT3_TR_CTRL2
402001e8 a CYREG_TCPWM_CNT3_TR_CTRL2
40200000 a CYREG_TCPWM_CTRL
40200000 a CYREG_TCPWM_CTRL
4020000c a CYREG_TCPWM_INTR_CAUSE
4020000c a CYREG_TCPWM_INTR_CAUSE
40030004 a CYREG_TST_ADFT_CTRL
40030004 a CYREG_TST_ADFT_CTRL
40030000 a CYREG_TST_CTRL
40030000 a CYREG_TST_CTRL
40030008 a CYREG_TST_DDFT_CTRL
40030008 a CYREG_TST_DDFT_CTRL
40030014 a CYREG_TST_MODE
40030014 a CYREG_TST_MODE
40030018 a CYREG_TST_TRIM_CNTR1
40030018 a CYREG_TST_TRIM_CNTR1
4003001c a CYREG_TST_TRIM_CNTR2
4003001c a CYREG_TST_TRIM_CNTR2
400f6008 a CYREG_UDB_BCTL0_BOTSEL_L
400f6008 a CYREG_UDB_BCTL0_BOTSEL_L
400f6009 a CYREG_UDB_BCTL0_BOTSEL_U
400f6009 a CYREG_UDB_BCTL0_BOTSEL_U
400f6000 a CYREG_UDB_BCTL0_DRV
400f6000 a CYREG_UDB_BCTL0_DRV
400f6002 a CYREG_UDB_BCTL0_MBCLK_EN
400f6002 a CYREG_UDB_BCTL0_MBCLK_EN
400f6001 a CYREG_UDB_BCTL0_MDCLK_EN
400f6001 a CYREG_UDB_BCTL0_MDCLK_EN
400f6010 a CYREG_UDB_BCTL0_QCLK_EN0
400f6010 a CYREG_UDB_BCTL0_QCLK_EN0
400f6012 a CYREG_UDB_BCTL0_QCLK_EN1
400f6012 a CYREG_UDB_BCTL0_QCLK_EN1
400f6014 a CYREG_UDB_BCTL0_QCLK_EN2
400f6014 a CYREG_UDB_BCTL0_QCLK_EN2
400f6016 a CYREG_UDB_BCTL0_QCLK_EN3
400f6016 a CYREG_UDB_BCTL0_QCLK_EN3
400f600a a CYREG_UDB_BCTL0_TOPSEL_L
400f600a a CYREG_UDB_BCTL0_TOPSEL_L
400f600b a CYREG_UDB_BCTL0_TOPSEL_U
400f600b a CYREG_UDB_BCTL0_TOPSEL_U
400f1000 a CYREG_UDB_CAT16_A_00
400f1000 a CYREG_UDB_CAT16_A_00
400f1002 a CYREG_UDB_CAT16_A_01
400f1002 a CYREG_UDB_CAT16_A_01
400f1004 a CYREG_UDB_CAT16_A_02
400f1004 a CYREG_UDB_CAT16_A_02
400f1006 a CYREG_UDB_CAT16_A_03
400f1006 a CYREG_UDB_CAT16_A_03
400f1000 a CYREG_UDB_CAT16_A0
400f1000 a CYREG_UDB_CAT16_A0
400f1002 a CYREG_UDB_CAT16_A1
400f1002 a CYREG_UDB_CAT16_A1
400f1004 a CYREG_UDB_CAT16_A2
400f1004 a CYREG_UDB_CAT16_A2
400f1006 a CYREG_UDB_CAT16_A3
400f1006 a CYREG_UDB_CAT16_A3
400f1100 a CYREG_UDB_CAT16_ACTL_MSK_00
400f1100 a CYREG_UDB_CAT16_ACTL_MSK_00
400f1102 a CYREG_UDB_CAT16_ACTL_MSK_01
400f1102 a CYREG_UDB_CAT16_ACTL_MSK_01
400f1104 a CYREG_UDB_CAT16_ACTL_MSK_02
400f1104 a CYREG_UDB_CAT16_ACTL_MSK_02
400f1106 a CYREG_UDB_CAT16_ACTL_MSK_03
400f1106 a CYREG_UDB_CAT16_ACTL_MSK_03
400f1100 a CYREG_UDB_CAT16_ACTL_MSK0
400f1100 a CYREG_UDB_CAT16_ACTL_MSK0
400f1102 a CYREG_UDB_CAT16_ACTL_MSK1
400f1102 a CYREG_UDB_CAT16_ACTL_MSK1
400f1104 a CYREG_UDB_CAT16_ACTL_MSK2
400f1104 a CYREG_UDB_CAT16_ACTL_MSK2
400f1106 a CYREG_UDB_CAT16_ACTL_MSK3
400f1106 a CYREG_UDB_CAT16_ACTL_MSK3
400f10c0 a CYREG_UDB_CAT16_CTL_ST_00
400f10c0 a CYREG_UDB_CAT16_CTL_ST_00
400f10c2 a CYREG_UDB_CAT16_CTL_ST_01
400f10c2 a CYREG_UDB_CAT16_CTL_ST_01
400f10c4 a CYREG_UDB_CAT16_CTL_ST_02
400f10c4 a CYREG_UDB_CAT16_CTL_ST_02
400f10c6 a CYREG_UDB_CAT16_CTL_ST_03
400f10c6 a CYREG_UDB_CAT16_CTL_ST_03
400f10c0 a CYREG_UDB_CAT16_CTL_ST0
400f10c0 a CYREG_UDB_CAT16_CTL_ST0
400f10c2 a CYREG_UDB_CAT16_CTL_ST1
400f10c2 a CYREG_UDB_CAT16_CTL_ST1
400f10c4 a CYREG_UDB_CAT16_CTL_ST2
400f10c4 a CYREG_UDB_CAT16_CTL_ST2
400f10c6 a CYREG_UDB_CAT16_CTL_ST3
400f10c6 a CYREG_UDB_CAT16_CTL_ST3
400f1040 a CYREG_UDB_CAT16_D_00
400f1040 a CYREG_UDB_CAT16_D_00
400f1042 a CYREG_UDB_CAT16_D_01
400f1042 a CYREG_UDB_CAT16_D_01
400f1044 a CYREG_UDB_CAT16_D_02
400f1044 a CYREG_UDB_CAT16_D_02
400f1046 a CYREG_UDB_CAT16_D_03
400f1046 a CYREG_UDB_CAT16_D_03
400f1040 a CYREG_UDB_CAT16_D0
400f1040 a CYREG_UDB_CAT16_D0
400f1042 a CYREG_UDB_CAT16_D1
400f1042 a CYREG_UDB_CAT16_D1
400f1044 a CYREG_UDB_CAT16_D2
400f1044 a CYREG_UDB_CAT16_D2
400f1046 a CYREG_UDB_CAT16_D3
400f1046 a CYREG_UDB_CAT16_D3
400f1080 a CYREG_UDB_CAT16_F_00
400f1080 a CYREG_UDB_CAT16_F_00
400f1082 a CYREG_UDB_CAT16_F_01
400f1082 a CYREG_UDB_CAT16_F_01
400f1084 a CYREG_UDB_CAT16_F_02
400f1084 a CYREG_UDB_CAT16_F_02
400f1086 a CYREG_UDB_CAT16_F_03
400f1086 a CYREG_UDB_CAT16_F_03
400f1080 a CYREG_UDB_CAT16_F0
400f1080 a CYREG_UDB_CAT16_F0
400f1082 a CYREG_UDB_CAT16_F1
400f1082 a CYREG_UDB_CAT16_F1
400f1084 a CYREG_UDB_CAT16_F2
400f1084 a CYREG_UDB_CAT16_F2
400f1086 a CYREG_UDB_CAT16_F3
400f1086 a CYREG_UDB_CAT16_F3
400f1140 a CYREG_UDB_CAT16_MC_00
400f1140 a CYREG_UDB_CAT16_MC_00
400f1142 a CYREG_UDB_CAT16_MC_01
400f1142 a CYREG_UDB_CAT16_MC_01
400f1144 a CYREG_UDB_CAT16_MC_02
400f1144 a CYREG_UDB_CAT16_MC_02
400f1146 a CYREG_UDB_CAT16_MC_03
400f1146 a CYREG_UDB_CAT16_MC_03
400f1140 a CYREG_UDB_CAT16_MC0
400f1140 a CYREG_UDB_CAT16_MC0
400f1142 a CYREG_UDB_CAT16_MC1
400f1142 a CYREG_UDB_CAT16_MC1
400f1144 a CYREG_UDB_CAT16_MC2
400f1144 a CYREG_UDB_CAT16_MC2
400f1146 a CYREG_UDB_CAT16_MC3
400f1146 a CYREG_UDB_CAT16_MC3
400f40c0 a CYREG_UDB_DSI0_DSIINP0
400f40c0 a CYREG_UDB_DSI0_DSIINP0
400f40c2 a CYREG_UDB_DSI0_DSIINP1
400f40c2 a CYREG_UDB_DSI0_DSIINP1
400f40c4 a CYREG_UDB_DSI0_DSIINP2
400f40c4 a CYREG_UDB_DSI0_DSIINP2
400f40c6 a CYREG_UDB_DSI0_DSIINP3
400f40c6 a CYREG_UDB_DSI0_DSIINP3
400f40c8 a CYREG_UDB_DSI0_DSIINP4
400f40c8 a CYREG_UDB_DSI0_DSIINP4
400f40ca a CYREG_UDB_DSI0_DSIINP5
400f40ca a CYREG_UDB_DSI0_DSIINP5
400f40cc a CYREG_UDB_DSI0_DSIOUTP0
400f40cc a CYREG_UDB_DSI0_DSIOUTP0
400f40ce a CYREG_UDB_DSI0_DSIOUTP1
400f40ce a CYREG_UDB_DSI0_DSIOUTP1
400f40d0 a CYREG_UDB_DSI0_DSIOUTP2
400f40d0 a CYREG_UDB_DSI0_DSIOUTP2
400f40d2 a CYREG_UDB_DSI0_DSIOUTP3
400f40d2 a CYREG_UDB_DSI0_DSIOUTP3
400f40d4 a CYREG_UDB_DSI0_DSIOUTT0
400f40d4 a CYREG_UDB_DSI0_DSIOUTT0
400f40d6 a CYREG_UDB_DSI0_DSIOUTT1
400f40d6 a CYREG_UDB_DSI0_DSIOUTT1
400f40d8 a CYREG_UDB_DSI0_DSIOUTT2
400f40d8 a CYREG_UDB_DSI0_DSIOUTT2
400f40da a CYREG_UDB_DSI0_DSIOUTT3
400f40da a CYREG_UDB_DSI0_DSIOUTT3
400f40dc a CYREG_UDB_DSI0_DSIOUTT4
400f40dc a CYREG_UDB_DSI0_DSIOUTT4
400f40de a CYREG_UDB_DSI0_DSIOUTT5
400f40de a CYREG_UDB_DSI0_DSIOUTT5
400f4000 a CYREG_UDB_DSI0_HC0
400f4000 a CYREG_UDB_DSI0_HC0
400f4001 a CYREG_UDB_DSI0_HC1
400f4001 a CYREG_UDB_DSI0_HC1
400f400a a CYREG_UDB_DSI0_HC10
400f400a a CYREG_UDB_DSI0_HC10
400f4064 a CYREG_UDB_DSI0_HC100
400f4064 a CYREG_UDB_DSI0_HC100
400f4065 a CYREG_UDB_DSI0_HC101
400f4065 a CYREG_UDB_DSI0_HC101
400f4066 a CYREG_UDB_DSI0_HC102
400f4066 a CYREG_UDB_DSI0_HC102
400f4067 a CYREG_UDB_DSI0_HC103
400f4067 a CYREG_UDB_DSI0_HC103
400f4068 a CYREG_UDB_DSI0_HC104
400f4068 a CYREG_UDB_DSI0_HC104
400f4069 a CYREG_UDB_DSI0_HC105
400f4069 a CYREG_UDB_DSI0_HC105
400f406a a CYREG_UDB_DSI0_HC106
400f406a a CYREG_UDB_DSI0_HC106
400f406b a CYREG_UDB_DSI0_HC107
400f406b a CYREG_UDB_DSI0_HC107
400f406c a CYREG_UDB_DSI0_HC108
400f406c a CYREG_UDB_DSI0_HC108
400f406d a CYREG_UDB_DSI0_HC109
400f406d a CYREG_UDB_DSI0_HC109
400f400b a CYREG_UDB_DSI0_HC11
400f400b a CYREG_UDB_DSI0_HC11
400f406e a CYREG_UDB_DSI0_HC110
400f406e a CYREG_UDB_DSI0_HC110
400f406f a CYREG_UDB_DSI0_HC111
400f406f a CYREG_UDB_DSI0_HC111
400f4070 a CYREG_UDB_DSI0_HC112
400f4070 a CYREG_UDB_DSI0_HC112
400f4071 a CYREG_UDB_DSI0_HC113
400f4071 a CYREG_UDB_DSI0_HC113
400f4072 a CYREG_UDB_DSI0_HC114
400f4072 a CYREG_UDB_DSI0_HC114
400f4073 a CYREG_UDB_DSI0_HC115
400f4073 a CYREG_UDB_DSI0_HC115
400f4074 a CYREG_UDB_DSI0_HC116
400f4074 a CYREG_UDB_DSI0_HC116
400f4075 a CYREG_UDB_DSI0_HC117
400f4075 a CYREG_UDB_DSI0_HC117
400f4076 a CYREG_UDB_DSI0_HC118
400f4076 a CYREG_UDB_DSI0_HC118
400f4077 a CYREG_UDB_DSI0_HC119
400f4077 a CYREG_UDB_DSI0_HC119
400f400c a CYREG_UDB_DSI0_HC12
400f400c a CYREG_UDB_DSI0_HC12
400f4078 a CYREG_UDB_DSI0_HC120
400f4078 a CYREG_UDB_DSI0_HC120
400f4079 a CYREG_UDB_DSI0_HC121
400f4079 a CYREG_UDB_DSI0_HC121
400f407a a CYREG_UDB_DSI0_HC122
400f407a a CYREG_UDB_DSI0_HC122
400f407b a CYREG_UDB_DSI0_HC123
400f407b a CYREG_UDB_DSI0_HC123
400f407c a CYREG_UDB_DSI0_HC124
400f407c a CYREG_UDB_DSI0_HC124
400f407d a CYREG_UDB_DSI0_HC125
400f407d a CYREG_UDB_DSI0_HC125
400f407e a CYREG_UDB_DSI0_HC126
400f407e a CYREG_UDB_DSI0_HC126
400f407f a CYREG_UDB_DSI0_HC127
400f407f a CYREG_UDB_DSI0_HC127
400f400d a CYREG_UDB_DSI0_HC13
400f400d a CYREG_UDB_DSI0_HC13
400f400e a CYREG_UDB_DSI0_HC14
400f400e a CYREG_UDB_DSI0_HC14
400f400f a CYREG_UDB_DSI0_HC15
400f400f a CYREG_UDB_DSI0_HC15
400f4010 a CYREG_UDB_DSI0_HC16
400f4010 a CYREG_UDB_DSI0_HC16
400f4011 a CYREG_UDB_DSI0_HC17
400f4011 a CYREG_UDB_DSI0_HC17
400f4012 a CYREG_UDB_DSI0_HC18
400f4012 a CYREG_UDB_DSI0_HC18
400f4013 a CYREG_UDB_DSI0_HC19
400f4013 a CYREG_UDB_DSI0_HC19
400f4002 a CYREG_UDB_DSI0_HC2
400f4002 a CYREG_UDB_DSI0_HC2
400f4014 a CYREG_UDB_DSI0_HC20
400f4014 a CYREG_UDB_DSI0_HC20
400f4015 a CYREG_UDB_DSI0_HC21
400f4015 a CYREG_UDB_DSI0_HC21
400f4016 a CYREG_UDB_DSI0_HC22
400f4016 a CYREG_UDB_DSI0_HC22
400f4017 a CYREG_UDB_DSI0_HC23
400f4017 a CYREG_UDB_DSI0_HC23
400f4018 a CYREG_UDB_DSI0_HC24
400f4018 a CYREG_UDB_DSI0_HC24
400f4019 a CYREG_UDB_DSI0_HC25
400f4019 a CYREG_UDB_DSI0_HC25
400f401a a CYREG_UDB_DSI0_HC26
400f401a a CYREG_UDB_DSI0_HC26
400f401b a CYREG_UDB_DSI0_HC27
400f401b a CYREG_UDB_DSI0_HC27
400f401c a CYREG_UDB_DSI0_HC28
400f401c a CYREG_UDB_DSI0_HC28
400f401d a CYREG_UDB_DSI0_HC29
400f401d a CYREG_UDB_DSI0_HC29
400f4003 a CYREG_UDB_DSI0_HC3
400f4003 a CYREG_UDB_DSI0_HC3
400f401e a CYREG_UDB_DSI0_HC30
400f401e a CYREG_UDB_DSI0_HC30
400f401f a CYREG_UDB_DSI0_HC31
400f401f a CYREG_UDB_DSI0_HC31
400f4020 a CYREG_UDB_DSI0_HC32
400f4020 a CYREG_UDB_DSI0_HC32
400f4021 a CYREG_UDB_DSI0_HC33
400f4021 a CYREG_UDB_DSI0_HC33
400f4022 a CYREG_UDB_DSI0_HC34
400f4022 a CYREG_UDB_DSI0_HC34
400f4023 a CYREG_UDB_DSI0_HC35
400f4023 a CYREG_UDB_DSI0_HC35
400f4024 a CYREG_UDB_DSI0_HC36
400f4024 a CYREG_UDB_DSI0_HC36
400f4025 a CYREG_UDB_DSI0_HC37
400f4025 a CYREG_UDB_DSI0_HC37
400f4026 a CYREG_UDB_DSI0_HC38
400f4026 a CYREG_UDB_DSI0_HC38
400f4027 a CYREG_UDB_DSI0_HC39
400f4027 a CYREG_UDB_DSI0_HC39
400f4004 a CYREG_UDB_DSI0_HC4
400f4004 a CYREG_UDB_DSI0_HC4
400f4028 a CYREG_UDB_DSI0_HC40
400f4028 a CYREG_UDB_DSI0_HC40
400f4029 a CYREG_UDB_DSI0_HC41
400f4029 a CYREG_UDB_DSI0_HC41
400f402a a CYREG_UDB_DSI0_HC42
400f402a a CYREG_UDB_DSI0_HC42
400f402b a CYREG_UDB_DSI0_HC43
400f402b a CYREG_UDB_DSI0_HC43
400f402c a CYREG_UDB_DSI0_HC44
400f402c a CYREG_UDB_DSI0_HC44
400f402d a CYREG_UDB_DSI0_HC45
400f402d a CYREG_UDB_DSI0_HC45
400f402e a CYREG_UDB_DSI0_HC46
400f402e a CYREG_UDB_DSI0_HC46
400f402f a CYREG_UDB_DSI0_HC47
400f402f a CYREG_UDB_DSI0_HC47
400f4030 a CYREG_UDB_DSI0_HC48
400f4030 a CYREG_UDB_DSI0_HC48
400f4031 a CYREG_UDB_DSI0_HC49
400f4031 a CYREG_UDB_DSI0_HC49
400f4005 a CYREG_UDB_DSI0_HC5
400f4005 a CYREG_UDB_DSI0_HC5
400f4032 a CYREG_UDB_DSI0_HC50
400f4032 a CYREG_UDB_DSI0_HC50
400f4033 a CYREG_UDB_DSI0_HC51
400f4033 a CYREG_UDB_DSI0_HC51
400f4034 a CYREG_UDB_DSI0_HC52
400f4034 a CYREG_UDB_DSI0_HC52
400f4035 a CYREG_UDB_DSI0_HC53
400f4035 a CYREG_UDB_DSI0_HC53
400f4036 a CYREG_UDB_DSI0_HC54
400f4036 a CYREG_UDB_DSI0_HC54
400f4037 a CYREG_UDB_DSI0_HC55
400f4037 a CYREG_UDB_DSI0_HC55
400f4038 a CYREG_UDB_DSI0_HC56
400f4038 a CYREG_UDB_DSI0_HC56
400f4039 a CYREG_UDB_DSI0_HC57
400f4039 a CYREG_UDB_DSI0_HC57
400f403a a CYREG_UDB_DSI0_HC58
400f403a a CYREG_UDB_DSI0_HC58
400f403b a CYREG_UDB_DSI0_HC59
400f403b a CYREG_UDB_DSI0_HC59
400f4006 a CYREG_UDB_DSI0_HC6
400f4006 a CYREG_UDB_DSI0_HC6
400f403c a CYREG_UDB_DSI0_HC60
400f403c a CYREG_UDB_DSI0_HC60
400f403d a CYREG_UDB_DSI0_HC61
400f403d a CYREG_UDB_DSI0_HC61
400f403e a CYREG_UDB_DSI0_HC62
400f403e a CYREG_UDB_DSI0_HC62
400f403f a CYREG_UDB_DSI0_HC63
400f403f a CYREG_UDB_DSI0_HC63
400f4040 a CYREG_UDB_DSI0_HC64
400f4040 a CYREG_UDB_DSI0_HC64
400f4041 a CYREG_UDB_DSI0_HC65
400f4041 a CYREG_UDB_DSI0_HC65
400f4042 a CYREG_UDB_DSI0_HC66
400f4042 a CYREG_UDB_DSI0_HC66
400f4043 a CYREG_UDB_DSI0_HC67
400f4043 a CYREG_UDB_DSI0_HC67
400f4044 a CYREG_UDB_DSI0_HC68
400f4044 a CYREG_UDB_DSI0_HC68
400f4045 a CYREG_UDB_DSI0_HC69
400f4045 a CYREG_UDB_DSI0_HC69
400f4007 a CYREG_UDB_DSI0_HC7
400f4007 a CYREG_UDB_DSI0_HC7
400f4046 a CYREG_UDB_DSI0_HC70
400f4046 a CYREG_UDB_DSI0_HC70
400f4047 a CYREG_UDB_DSI0_HC71
400f4047 a CYREG_UDB_DSI0_HC71
400f4048 a CYREG_UDB_DSI0_HC72
400f4048 a CYREG_UDB_DSI0_HC72
400f4049 a CYREG_UDB_DSI0_HC73
400f4049 a CYREG_UDB_DSI0_HC73
400f404a a CYREG_UDB_DSI0_HC74
400f404a a CYREG_UDB_DSI0_HC74
400f404b a CYREG_UDB_DSI0_HC75
400f404b a CYREG_UDB_DSI0_HC75
400f404c a CYREG_UDB_DSI0_HC76
400f404c a CYREG_UDB_DSI0_HC76
400f404d a CYREG_UDB_DSI0_HC77
400f404d a CYREG_UDB_DSI0_HC77
400f404e a CYREG_UDB_DSI0_HC78
400f404e a CYREG_UDB_DSI0_HC78
400f404f a CYREG_UDB_DSI0_HC79
400f404f a CYREG_UDB_DSI0_HC79
400f4008 a CYREG_UDB_DSI0_HC8
400f4008 a CYREG_UDB_DSI0_HC8
400f4050 a CYREG_UDB_DSI0_HC80
400f4050 a CYREG_UDB_DSI0_HC80
400f4051 a CYREG_UDB_DSI0_HC81
400f4051 a CYREG_UDB_DSI0_HC81
400f4052 a CYREG_UDB_DSI0_HC82
400f4052 a CYREG_UDB_DSI0_HC82
400f4053 a CYREG_UDB_DSI0_HC83
400f4053 a CYREG_UDB_DSI0_HC83
400f4054 a CYREG_UDB_DSI0_HC84
400f4054 a CYREG_UDB_DSI0_HC84
400f4055 a CYREG_UDB_DSI0_HC85
400f4055 a CYREG_UDB_DSI0_HC85
400f4056 a CYREG_UDB_DSI0_HC86
400f4056 a CYREG_UDB_DSI0_HC86
400f4057 a CYREG_UDB_DSI0_HC87
400f4057 a CYREG_UDB_DSI0_HC87
400f4058 a CYREG_UDB_DSI0_HC88
400f4058 a CYREG_UDB_DSI0_HC88
400f4059 a CYREG_UDB_DSI0_HC89
400f4059 a CYREG_UDB_DSI0_HC89
400f4009 a CYREG_UDB_DSI0_HC9
400f4009 a CYREG_UDB_DSI0_HC9
400f405a a CYREG_UDB_DSI0_HC90
400f405a a CYREG_UDB_DSI0_HC90
400f405b a CYREG_UDB_DSI0_HC91
400f405b a CYREG_UDB_DSI0_HC91
400f405c a CYREG_UDB_DSI0_HC92
400f405c a CYREG_UDB_DSI0_HC92
400f405d a CYREG_UDB_DSI0_HC93
400f405d a CYREG_UDB_DSI0_HC93
400f405e a CYREG_UDB_DSI0_HC94
400f405e a CYREG_UDB_DSI0_HC94
400f405f a CYREG_UDB_DSI0_HC95
400f405f a CYREG_UDB_DSI0_HC95
400f4060 a CYREG_UDB_DSI0_HC96
400f4060 a CYREG_UDB_DSI0_HC96
400f4061 a CYREG_UDB_DSI0_HC97
400f4061 a CYREG_UDB_DSI0_HC97
400f4062 a CYREG_UDB_DSI0_HC98
400f4062 a CYREG_UDB_DSI0_HC98
400f4063 a CYREG_UDB_DSI0_HC99
400f4063 a CYREG_UDB_DSI0_HC99
400f4090 a CYREG_UDB_DSI0_HS0
400f4090 a CYREG_UDB_DSI0_HS0
400f4091 a CYREG_UDB_DSI0_HS1
400f4091 a CYREG_UDB_DSI0_HS1
400f409a a CYREG_UDB_DSI0_HS10
400f409a a CYREG_UDB_DSI0_HS10
400f409b a CYREG_UDB_DSI0_HS11
400f409b a CYREG_UDB_DSI0_HS11
400f409c a CYREG_UDB_DSI0_HS12
400f409c a CYREG_UDB_DSI0_HS12
400f409d a CYREG_UDB_DSI0_HS13
400f409d a CYREG_UDB_DSI0_HS13
400f409e a CYREG_UDB_DSI0_HS14
400f409e a CYREG_UDB_DSI0_HS14
400f409f a CYREG_UDB_DSI0_HS15
400f409f a CYREG_UDB_DSI0_HS15
400f40a0 a CYREG_UDB_DSI0_HS16
400f40a0 a CYREG_UDB_DSI0_HS16
400f40a1 a CYREG_UDB_DSI0_HS17
400f40a1 a CYREG_UDB_DSI0_HS17
400f40a2 a CYREG_UDB_DSI0_HS18
400f40a2 a CYREG_UDB_DSI0_HS18
400f40a3 a CYREG_UDB_DSI0_HS19
400f40a3 a CYREG_UDB_DSI0_HS19
400f4092 a CYREG_UDB_DSI0_HS2
400f4092 a CYREG_UDB_DSI0_HS2
400f40a4 a CYREG_UDB_DSI0_HS20
400f40a4 a CYREG_UDB_DSI0_HS20
400f40a5 a CYREG_UDB_DSI0_HS21
400f40a5 a CYREG_UDB_DSI0_HS21
400f40a6 a CYREG_UDB_DSI0_HS22
400f40a6 a CYREG_UDB_DSI0_HS22
400f40a7 a CYREG_UDB_DSI0_HS23
400f40a7 a CYREG_UDB_DSI0_HS23
400f4093 a CYREG_UDB_DSI0_HS3
400f4093 a CYREG_UDB_DSI0_HS3
400f4094 a CYREG_UDB_DSI0_HS4
400f4094 a CYREG_UDB_DSI0_HS4
400f4095 a CYREG_UDB_DSI0_HS5
400f4095 a CYREG_UDB_DSI0_HS5
400f4096 a CYREG_UDB_DSI0_HS6
400f4096 a CYREG_UDB_DSI0_HS6
400f4097 a CYREG_UDB_DSI0_HS7
400f4097 a CYREG_UDB_DSI0_HS7
400f4098 a CYREG_UDB_DSI0_HS8
400f4098 a CYREG_UDB_DSI0_HS8
400f4099 a CYREG_UDB_DSI0_HS9
400f4099 a CYREG_UDB_DSI0_HS9
400f4080 a CYREG_UDB_DSI0_HV_L0
400f4080 a CYREG_UDB_DSI0_HV_L0
400f4081 a CYREG_UDB_DSI0_HV_L1
400f4081 a CYREG_UDB_DSI0_HV_L1
400f408a a CYREG_UDB_DSI0_HV_L10
400f408a a CYREG_UDB_DSI0_HV_L10
400f408b a CYREG_UDB_DSI0_HV_L11
400f408b a CYREG_UDB_DSI0_HV_L11
400f408c a CYREG_UDB_DSI0_HV_L12
400f408c a CYREG_UDB_DSI0_HV_L12
400f408d a CYREG_UDB_DSI0_HV_L13
400f408d a CYREG_UDB_DSI0_HV_L13
400f408e a CYREG_UDB_DSI0_HV_L14
400f408e a CYREG_UDB_DSI0_HV_L14
400f408f a CYREG_UDB_DSI0_HV_L15
400f408f a CYREG_UDB_DSI0_HV_L15
400f4082 a CYREG_UDB_DSI0_HV_L2
400f4082 a CYREG_UDB_DSI0_HV_L2
400f4083 a CYREG_UDB_DSI0_HV_L3
400f4083 a CYREG_UDB_DSI0_HV_L3
400f4084 a CYREG_UDB_DSI0_HV_L4
400f4084 a CYREG_UDB_DSI0_HV_L4
400f4085 a CYREG_UDB_DSI0_HV_L5
400f4085 a CYREG_UDB_DSI0_HV_L5
400f4086 a CYREG_UDB_DSI0_HV_L6
400f4086 a CYREG_UDB_DSI0_HV_L6
400f4087 a CYREG_UDB_DSI0_HV_L7
400f4087 a CYREG_UDB_DSI0_HV_L7
400f4088 a CYREG_UDB_DSI0_HV_L8
400f4088 a CYREG_UDB_DSI0_HV_L8
400f4089 a CYREG_UDB_DSI0_HV_L9
400f4089 a CYREG_UDB_DSI0_HV_L9
400f40a8 a CYREG_UDB_DSI0_HV_R0
400f40a8 a CYREG_UDB_DSI0_HV_R0
400f40a9 a CYREG_UDB_DSI0_HV_R1
400f40a9 a CYREG_UDB_DSI0_HV_R1
400f40b2 a CYREG_UDB_DSI0_HV_R10
400f40b2 a CYREG_UDB_DSI0_HV_R10
400f40b3 a CYREG_UDB_DSI0_HV_R11
400f40b3 a CYREG_UDB_DSI0_HV_R11
400f40b4 a CYREG_UDB_DSI0_HV_R12
400f40b4 a CYREG_UDB_DSI0_HV_R12
400f40b5 a CYREG_UDB_DSI0_HV_R13
400f40b5 a CYREG_UDB_DSI0_HV_R13
400f40b6 a CYREG_UDB_DSI0_HV_R14
400f40b6 a CYREG_UDB_DSI0_HV_R14
400f40b7 a CYREG_UDB_DSI0_HV_R15
400f40b7 a CYREG_UDB_DSI0_HV_R15
400f40aa a CYREG_UDB_DSI0_HV_R2
400f40aa a CYREG_UDB_DSI0_HV_R2
400f40ab a CYREG_UDB_DSI0_HV_R3
400f40ab a CYREG_UDB_DSI0_HV_R3
400f40ac a CYREG_UDB_DSI0_HV_R4
400f40ac a CYREG_UDB_DSI0_HV_R4
400f40ad a CYREG_UDB_DSI0_HV_R5
400f40ad a CYREG_UDB_DSI0_HV_R5
400f40ae a CYREG_UDB_DSI0_HV_R6
400f40ae a CYREG_UDB_DSI0_HV_R6
400f40af a CYREG_UDB_DSI0_HV_R7
400f40af a CYREG_UDB_DSI0_HV_R7
400f40b0 a CYREG_UDB_DSI0_HV_R8
400f40b0 a CYREG_UDB_DSI0_HV_R8
400f40b1 a CYREG_UDB_DSI0_HV_R9
400f40b1 a CYREG_UDB_DSI0_HV_R9
400f40e0 a CYREG_UDB_DSI0_VS0
400f40e0 a CYREG_UDB_DSI0_VS0
400f40e2 a CYREG_UDB_DSI0_VS1
400f40e2 a CYREG_UDB_DSI0_VS1
400f40e4 a CYREG_UDB_DSI0_VS2
400f40e4 a CYREG_UDB_DSI0_VS2
400f40e6 a CYREG_UDB_DSI0_VS3
400f40e6 a CYREG_UDB_DSI0_VS3
400f40e8 a CYREG_UDB_DSI0_VS4
400f40e8 a CYREG_UDB_DSI0_VS4
400f40ea a CYREG_UDB_DSI0_VS5
400f40ea a CYREG_UDB_DSI0_VS5
400f40ec a CYREG_UDB_DSI0_VS6
400f40ec a CYREG_UDB_DSI0_VS6
400f40ee a CYREG_UDB_DSI0_VS7
400f40ee a CYREG_UDB_DSI0_VS7
400f41c0 a CYREG_UDB_DSI1_DSIINP0
400f41c0 a CYREG_UDB_DSI1_DSIINP0
400f41c2 a CYREG_UDB_DSI1_DSIINP1
400f41c2 a CYREG_UDB_DSI1_DSIINP1
400f41c4 a CYREG_UDB_DSI1_DSIINP2
400f41c4 a CYREG_UDB_DSI1_DSIINP2
400f41c6 a CYREG_UDB_DSI1_DSIINP3
400f41c6 a CYREG_UDB_DSI1_DSIINP3
400f41c8 a CYREG_UDB_DSI1_DSIINP4
400f41c8 a CYREG_UDB_DSI1_DSIINP4
400f41ca a CYREG_UDB_DSI1_DSIINP5
400f41ca a CYREG_UDB_DSI1_DSIINP5
400f41cc a CYREG_UDB_DSI1_DSIOUTP0
400f41cc a CYREG_UDB_DSI1_DSIOUTP0
400f41ce a CYREG_UDB_DSI1_DSIOUTP1
400f41ce a CYREG_UDB_DSI1_DSIOUTP1
400f41d0 a CYREG_UDB_DSI1_DSIOUTP2
400f41d0 a CYREG_UDB_DSI1_DSIOUTP2
400f41d2 a CYREG_UDB_DSI1_DSIOUTP3
400f41d2 a CYREG_UDB_DSI1_DSIOUTP3
400f41d4 a CYREG_UDB_DSI1_DSIOUTT0
400f41d4 a CYREG_UDB_DSI1_DSIOUTT0
400f41d6 a CYREG_UDB_DSI1_DSIOUTT1
400f41d6 a CYREG_UDB_DSI1_DSIOUTT1
400f41d8 a CYREG_UDB_DSI1_DSIOUTT2
400f41d8 a CYREG_UDB_DSI1_DSIOUTT2
400f41da a CYREG_UDB_DSI1_DSIOUTT3
400f41da a CYREG_UDB_DSI1_DSIOUTT3
400f41dc a CYREG_UDB_DSI1_DSIOUTT4
400f41dc a CYREG_UDB_DSI1_DSIOUTT4
400f41de a CYREG_UDB_DSI1_DSIOUTT5
400f41de a CYREG_UDB_DSI1_DSIOUTT5
400f4100 a CYREG_UDB_DSI1_HC0
400f4100 a CYREG_UDB_DSI1_HC0
400f4101 a CYREG_UDB_DSI1_HC1
400f4101 a CYREG_UDB_DSI1_HC1
400f410a a CYREG_UDB_DSI1_HC10
400f410a a CYREG_UDB_DSI1_HC10
400f4164 a CYREG_UDB_DSI1_HC100
400f4164 a CYREG_UDB_DSI1_HC100
400f4165 a CYREG_UDB_DSI1_HC101
400f4165 a CYREG_UDB_DSI1_HC101
400f4166 a CYREG_UDB_DSI1_HC102
400f4166 a CYREG_UDB_DSI1_HC102
400f4167 a CYREG_UDB_DSI1_HC103
400f4167 a CYREG_UDB_DSI1_HC103
400f4168 a CYREG_UDB_DSI1_HC104
400f4168 a CYREG_UDB_DSI1_HC104
400f4169 a CYREG_UDB_DSI1_HC105
400f4169 a CYREG_UDB_DSI1_HC105
400f416a a CYREG_UDB_DSI1_HC106
400f416a a CYREG_UDB_DSI1_HC106
400f416b a CYREG_UDB_DSI1_HC107
400f416b a CYREG_UDB_DSI1_HC107
400f416c a CYREG_UDB_DSI1_HC108
400f416c a CYREG_UDB_DSI1_HC108
400f416d a CYREG_UDB_DSI1_HC109
400f416d a CYREG_UDB_DSI1_HC109
400f410b a CYREG_UDB_DSI1_HC11
400f410b a CYREG_UDB_DSI1_HC11
400f416e a CYREG_UDB_DSI1_HC110
400f416e a CYREG_UDB_DSI1_HC110
400f416f a CYREG_UDB_DSI1_HC111
400f416f a CYREG_UDB_DSI1_HC111
400f4170 a CYREG_UDB_DSI1_HC112
400f4170 a CYREG_UDB_DSI1_HC112
400f4171 a CYREG_UDB_DSI1_HC113
400f4171 a CYREG_UDB_DSI1_HC113
400f4172 a CYREG_UDB_DSI1_HC114
400f4172 a CYREG_UDB_DSI1_HC114
400f4173 a CYREG_UDB_DSI1_HC115
400f4173 a CYREG_UDB_DSI1_HC115
400f4174 a CYREG_UDB_DSI1_HC116
400f4174 a CYREG_UDB_DSI1_HC116
400f4175 a CYREG_UDB_DSI1_HC117
400f4175 a CYREG_UDB_DSI1_HC117
400f4176 a CYREG_UDB_DSI1_HC118
400f4176 a CYREG_UDB_DSI1_HC118
400f4177 a CYREG_UDB_DSI1_HC119
400f4177 a CYREG_UDB_DSI1_HC119
400f410c a CYREG_UDB_DSI1_HC12
400f410c a CYREG_UDB_DSI1_HC12
400f4178 a CYREG_UDB_DSI1_HC120
400f4178 a CYREG_UDB_DSI1_HC120
400f4179 a CYREG_UDB_DSI1_HC121
400f4179 a CYREG_UDB_DSI1_HC121
400f417a a CYREG_UDB_DSI1_HC122
400f417a a CYREG_UDB_DSI1_HC122
400f417b a CYREG_UDB_DSI1_HC123
400f417b a CYREG_UDB_DSI1_HC123
400f417c a CYREG_UDB_DSI1_HC124
400f417c a CYREG_UDB_DSI1_HC124
400f417d a CYREG_UDB_DSI1_HC125
400f417d a CYREG_UDB_DSI1_HC125
400f417e a CYREG_UDB_DSI1_HC126
400f417e a CYREG_UDB_DSI1_HC126
400f417f a CYREG_UDB_DSI1_HC127
400f417f a CYREG_UDB_DSI1_HC127
400f410d a CYREG_UDB_DSI1_HC13
400f410d a CYREG_UDB_DSI1_HC13
400f410e a CYREG_UDB_DSI1_HC14
400f410e a CYREG_UDB_DSI1_HC14
400f410f a CYREG_UDB_DSI1_HC15
400f410f a CYREG_UDB_DSI1_HC15
400f4110 a CYREG_UDB_DSI1_HC16
400f4110 a CYREG_UDB_DSI1_HC16
400f4111 a CYREG_UDB_DSI1_HC17
400f4111 a CYREG_UDB_DSI1_HC17
400f4112 a CYREG_UDB_DSI1_HC18
400f4112 a CYREG_UDB_DSI1_HC18
400f4113 a CYREG_UDB_DSI1_HC19
400f4113 a CYREG_UDB_DSI1_HC19
400f4102 a CYREG_UDB_DSI1_HC2
400f4102 a CYREG_UDB_DSI1_HC2
400f4114 a CYREG_UDB_DSI1_HC20
400f4114 a CYREG_UDB_DSI1_HC20
400f4115 a CYREG_UDB_DSI1_HC21
400f4115 a CYREG_UDB_DSI1_HC21
400f4116 a CYREG_UDB_DSI1_HC22
400f4116 a CYREG_UDB_DSI1_HC22
400f4117 a CYREG_UDB_DSI1_HC23
400f4117 a CYREG_UDB_DSI1_HC23
400f4118 a CYREG_UDB_DSI1_HC24
400f4118 a CYREG_UDB_DSI1_HC24
400f4119 a CYREG_UDB_DSI1_HC25
400f4119 a CYREG_UDB_DSI1_HC25
400f411a a CYREG_UDB_DSI1_HC26
400f411a a CYREG_UDB_DSI1_HC26
400f411b a CYREG_UDB_DSI1_HC27
400f411b a CYREG_UDB_DSI1_HC27
400f411c a CYREG_UDB_DSI1_HC28
400f411c a CYREG_UDB_DSI1_HC28
400f411d a CYREG_UDB_DSI1_HC29
400f411d a CYREG_UDB_DSI1_HC29
400f4103 a CYREG_UDB_DSI1_HC3
400f4103 a CYREG_UDB_DSI1_HC3
400f411e a CYREG_UDB_DSI1_HC30
400f411e a CYREG_UDB_DSI1_HC30
400f411f a CYREG_UDB_DSI1_HC31
400f411f a CYREG_UDB_DSI1_HC31
400f4120 a CYREG_UDB_DSI1_HC32
400f4120 a CYREG_UDB_DSI1_HC32
400f4121 a CYREG_UDB_DSI1_HC33
400f4121 a CYREG_UDB_DSI1_HC33
400f4122 a CYREG_UDB_DSI1_HC34
400f4122 a CYREG_UDB_DSI1_HC34
400f4123 a CYREG_UDB_DSI1_HC35
400f4123 a CYREG_UDB_DSI1_HC35
400f4124 a CYREG_UDB_DSI1_HC36
400f4124 a CYREG_UDB_DSI1_HC36
400f4125 a CYREG_UDB_DSI1_HC37
400f4125 a CYREG_UDB_DSI1_HC37
400f4126 a CYREG_UDB_DSI1_HC38
400f4126 a CYREG_UDB_DSI1_HC38
400f4127 a CYREG_UDB_DSI1_HC39
400f4127 a CYREG_UDB_DSI1_HC39
400f4104 a CYREG_UDB_DSI1_HC4
400f4104 a CYREG_UDB_DSI1_HC4
400f4128 a CYREG_UDB_DSI1_HC40
400f4128 a CYREG_UDB_DSI1_HC40
400f4129 a CYREG_UDB_DSI1_HC41
400f4129 a CYREG_UDB_DSI1_HC41
400f412a a CYREG_UDB_DSI1_HC42
400f412a a CYREG_UDB_DSI1_HC42
400f412b a CYREG_UDB_DSI1_HC43
400f412b a CYREG_UDB_DSI1_HC43
400f412c a CYREG_UDB_DSI1_HC44
400f412c a CYREG_UDB_DSI1_HC44
400f412d a CYREG_UDB_DSI1_HC45
400f412d a CYREG_UDB_DSI1_HC45
400f412e a CYREG_UDB_DSI1_HC46
400f412e a CYREG_UDB_DSI1_HC46
400f412f a CYREG_UDB_DSI1_HC47
400f412f a CYREG_UDB_DSI1_HC47
400f4130 a CYREG_UDB_DSI1_HC48
400f4130 a CYREG_UDB_DSI1_HC48
400f4131 a CYREG_UDB_DSI1_HC49
400f4131 a CYREG_UDB_DSI1_HC49
400f4105 a CYREG_UDB_DSI1_HC5
400f4105 a CYREG_UDB_DSI1_HC5
400f4132 a CYREG_UDB_DSI1_HC50
400f4132 a CYREG_UDB_DSI1_HC50
400f4133 a CYREG_UDB_DSI1_HC51
400f4133 a CYREG_UDB_DSI1_HC51
400f4134 a CYREG_UDB_DSI1_HC52
400f4134 a CYREG_UDB_DSI1_HC52
400f4135 a CYREG_UDB_DSI1_HC53
400f4135 a CYREG_UDB_DSI1_HC53
400f4136 a CYREG_UDB_DSI1_HC54
400f4136 a CYREG_UDB_DSI1_HC54
400f4137 a CYREG_UDB_DSI1_HC55
400f4137 a CYREG_UDB_DSI1_HC55
400f4138 a CYREG_UDB_DSI1_HC56
400f4138 a CYREG_UDB_DSI1_HC56
400f4139 a CYREG_UDB_DSI1_HC57
400f4139 a CYREG_UDB_DSI1_HC57
400f413a a CYREG_UDB_DSI1_HC58
400f413a a CYREG_UDB_DSI1_HC58
400f413b a CYREG_UDB_DSI1_HC59
400f413b a CYREG_UDB_DSI1_HC59
400f4106 a CYREG_UDB_DSI1_HC6
400f4106 a CYREG_UDB_DSI1_HC6
400f413c a CYREG_UDB_DSI1_HC60
400f413c a CYREG_UDB_DSI1_HC60
400f413d a CYREG_UDB_DSI1_HC61
400f413d a CYREG_UDB_DSI1_HC61
400f413e a CYREG_UDB_DSI1_HC62
400f413e a CYREG_UDB_DSI1_HC62
400f413f a CYREG_UDB_DSI1_HC63
400f413f a CYREG_UDB_DSI1_HC63
400f4140 a CYREG_UDB_DSI1_HC64
400f4140 a CYREG_UDB_DSI1_HC64
400f4141 a CYREG_UDB_DSI1_HC65
400f4141 a CYREG_UDB_DSI1_HC65
400f4142 a CYREG_UDB_DSI1_HC66
400f4142 a CYREG_UDB_DSI1_HC66
400f4143 a CYREG_UDB_DSI1_HC67
400f4143 a CYREG_UDB_DSI1_HC67
400f4144 a CYREG_UDB_DSI1_HC68
400f4144 a CYREG_UDB_DSI1_HC68
400f4145 a CYREG_UDB_DSI1_HC69
400f4145 a CYREG_UDB_DSI1_HC69
400f4107 a CYREG_UDB_DSI1_HC7
400f4107 a CYREG_UDB_DSI1_HC7
400f4146 a CYREG_UDB_DSI1_HC70
400f4146 a CYREG_UDB_DSI1_HC70
400f4147 a CYREG_UDB_DSI1_HC71
400f4147 a CYREG_UDB_DSI1_HC71
400f4148 a CYREG_UDB_DSI1_HC72
400f4148 a CYREG_UDB_DSI1_HC72
400f4149 a CYREG_UDB_DSI1_HC73
400f4149 a CYREG_UDB_DSI1_HC73
400f414a a CYREG_UDB_DSI1_HC74
400f414a a CYREG_UDB_DSI1_HC74
400f414b a CYREG_UDB_DSI1_HC75
400f414b a CYREG_UDB_DSI1_HC75
400f414c a CYREG_UDB_DSI1_HC76
400f414c a CYREG_UDB_DSI1_HC76
400f414d a CYREG_UDB_DSI1_HC77
400f414d a CYREG_UDB_DSI1_HC77
400f414e a CYREG_UDB_DSI1_HC78
400f414e a CYREG_UDB_DSI1_HC78
400f414f a CYREG_UDB_DSI1_HC79
400f414f a CYREG_UDB_DSI1_HC79
400f4108 a CYREG_UDB_DSI1_HC8
400f4108 a CYREG_UDB_DSI1_HC8
400f4150 a CYREG_UDB_DSI1_HC80
400f4150 a CYREG_UDB_DSI1_HC80
400f4151 a CYREG_UDB_DSI1_HC81
400f4151 a CYREG_UDB_DSI1_HC81
400f4152 a CYREG_UDB_DSI1_HC82
400f4152 a CYREG_UDB_DSI1_HC82
400f4153 a CYREG_UDB_DSI1_HC83
400f4153 a CYREG_UDB_DSI1_HC83
400f4154 a CYREG_UDB_DSI1_HC84
400f4154 a CYREG_UDB_DSI1_HC84
400f4155 a CYREG_UDB_DSI1_HC85
400f4155 a CYREG_UDB_DSI1_HC85
400f4156 a CYREG_UDB_DSI1_HC86
400f4156 a CYREG_UDB_DSI1_HC86
400f4157 a CYREG_UDB_DSI1_HC87
400f4157 a CYREG_UDB_DSI1_HC87
400f4158 a CYREG_UDB_DSI1_HC88
400f4158 a CYREG_UDB_DSI1_HC88
400f4159 a CYREG_UDB_DSI1_HC89
400f4159 a CYREG_UDB_DSI1_HC89
400f4109 a CYREG_UDB_DSI1_HC9
400f4109 a CYREG_UDB_DSI1_HC9
400f415a a CYREG_UDB_DSI1_HC90
400f415a a CYREG_UDB_DSI1_HC90
400f415b a CYREG_UDB_DSI1_HC91
400f415b a CYREG_UDB_DSI1_HC91
400f415c a CYREG_UDB_DSI1_HC92
400f415c a CYREG_UDB_DSI1_HC92
400f415d a CYREG_UDB_DSI1_HC93
400f415d a CYREG_UDB_DSI1_HC93
400f415e a CYREG_UDB_DSI1_HC94
400f415e a CYREG_UDB_DSI1_HC94
400f415f a CYREG_UDB_DSI1_HC95
400f415f a CYREG_UDB_DSI1_HC95
400f4160 a CYREG_UDB_DSI1_HC96
400f4160 a CYREG_UDB_DSI1_HC96
400f4161 a CYREG_UDB_DSI1_HC97
400f4161 a CYREG_UDB_DSI1_HC97
400f4162 a CYREG_UDB_DSI1_HC98
400f4162 a CYREG_UDB_DSI1_HC98
400f4163 a CYREG_UDB_DSI1_HC99
400f4163 a CYREG_UDB_DSI1_HC99
400f4190 a CYREG_UDB_DSI1_HS0
400f4190 a CYREG_UDB_DSI1_HS0
400f4191 a CYREG_UDB_DSI1_HS1
400f4191 a CYREG_UDB_DSI1_HS1
400f419a a CYREG_UDB_DSI1_HS10
400f419a a CYREG_UDB_DSI1_HS10
400f419b a CYREG_UDB_DSI1_HS11
400f419b a CYREG_UDB_DSI1_HS11
400f419c a CYREG_UDB_DSI1_HS12
400f419c a CYREG_UDB_DSI1_HS12
400f419d a CYREG_UDB_DSI1_HS13
400f419d a CYREG_UDB_DSI1_HS13
400f419e a CYREG_UDB_DSI1_HS14
400f419e a CYREG_UDB_DSI1_HS14
400f419f a CYREG_UDB_DSI1_HS15
400f419f a CYREG_UDB_DSI1_HS15
400f41a0 a CYREG_UDB_DSI1_HS16
400f41a0 a CYREG_UDB_DSI1_HS16
400f41a1 a CYREG_UDB_DSI1_HS17
400f41a1 a CYREG_UDB_DSI1_HS17
400f41a2 a CYREG_UDB_DSI1_HS18
400f41a2 a CYREG_UDB_DSI1_HS18
400f41a3 a CYREG_UDB_DSI1_HS19
400f41a3 a CYREG_UDB_DSI1_HS19
400f4192 a CYREG_UDB_DSI1_HS2
400f4192 a CYREG_UDB_DSI1_HS2
400f41a4 a CYREG_UDB_DSI1_HS20
400f41a4 a CYREG_UDB_DSI1_HS20
400f41a5 a CYREG_UDB_DSI1_HS21
400f41a5 a CYREG_UDB_DSI1_HS21
400f41a6 a CYREG_UDB_DSI1_HS22
400f41a6 a CYREG_UDB_DSI1_HS22
400f41a7 a CYREG_UDB_DSI1_HS23
400f41a7 a CYREG_UDB_DSI1_HS23
400f4193 a CYREG_UDB_DSI1_HS3
400f4193 a CYREG_UDB_DSI1_HS3
400f4194 a CYREG_UDB_DSI1_HS4
400f4194 a CYREG_UDB_DSI1_HS4
400f4195 a CYREG_UDB_DSI1_HS5
400f4195 a CYREG_UDB_DSI1_HS5
400f4196 a CYREG_UDB_DSI1_HS6
400f4196 a CYREG_UDB_DSI1_HS6
400f4197 a CYREG_UDB_DSI1_HS7
400f4197 a CYREG_UDB_DSI1_HS7
400f4198 a CYREG_UDB_DSI1_HS8
400f4198 a CYREG_UDB_DSI1_HS8
400f4199 a CYREG_UDB_DSI1_HS9
400f4199 a CYREG_UDB_DSI1_HS9
400f4180 a CYREG_UDB_DSI1_HV_L0
400f4180 a CYREG_UDB_DSI1_HV_L0
400f4181 a CYREG_UDB_DSI1_HV_L1
400f4181 a CYREG_UDB_DSI1_HV_L1
400f418a a CYREG_UDB_DSI1_HV_L10
400f418a a CYREG_UDB_DSI1_HV_L10
400f418b a CYREG_UDB_DSI1_HV_L11
400f418b a CYREG_UDB_DSI1_HV_L11
400f418c a CYREG_UDB_DSI1_HV_L12
400f418c a CYREG_UDB_DSI1_HV_L12
400f418d a CYREG_UDB_DSI1_HV_L13
400f418d a CYREG_UDB_DSI1_HV_L13
400f418e a CYREG_UDB_DSI1_HV_L14
400f418e a CYREG_UDB_DSI1_HV_L14
400f418f a CYREG_UDB_DSI1_HV_L15
400f418f a CYREG_UDB_DSI1_HV_L15
400f4182 a CYREG_UDB_DSI1_HV_L2
400f4182 a CYREG_UDB_DSI1_HV_L2
400f4183 a CYREG_UDB_DSI1_HV_L3
400f4183 a CYREG_UDB_DSI1_HV_L3
400f4184 a CYREG_UDB_DSI1_HV_L4
400f4184 a CYREG_UDB_DSI1_HV_L4
400f4185 a CYREG_UDB_DSI1_HV_L5
400f4185 a CYREG_UDB_DSI1_HV_L5
400f4186 a CYREG_UDB_DSI1_HV_L6
400f4186 a CYREG_UDB_DSI1_HV_L6
400f4187 a CYREG_UDB_DSI1_HV_L7
400f4187 a CYREG_UDB_DSI1_HV_L7
400f4188 a CYREG_UDB_DSI1_HV_L8
400f4188 a CYREG_UDB_DSI1_HV_L8
400f4189 a CYREG_UDB_DSI1_HV_L9
400f4189 a CYREG_UDB_DSI1_HV_L9
400f41a8 a CYREG_UDB_DSI1_HV_R0
400f41a8 a CYREG_UDB_DSI1_HV_R0
400f41a9 a CYREG_UDB_DSI1_HV_R1
400f41a9 a CYREG_UDB_DSI1_HV_R1
400f41b2 a CYREG_UDB_DSI1_HV_R10
400f41b2 a CYREG_UDB_DSI1_HV_R10
400f41b3 a CYREG_UDB_DSI1_HV_R11
400f41b3 a CYREG_UDB_DSI1_HV_R11
400f41b4 a CYREG_UDB_DSI1_HV_R12
400f41b4 a CYREG_UDB_DSI1_HV_R12
400f41b5 a CYREG_UDB_DSI1_HV_R13
400f41b5 a CYREG_UDB_DSI1_HV_R13
400f41b6 a CYREG_UDB_DSI1_HV_R14
400f41b6 a CYREG_UDB_DSI1_HV_R14
400f41b7 a CYREG_UDB_DSI1_HV_R15
400f41b7 a CYREG_UDB_DSI1_HV_R15
400f41aa a CYREG_UDB_DSI1_HV_R2
400f41aa a CYREG_UDB_DSI1_HV_R2
400f41ab a CYREG_UDB_DSI1_HV_R3
400f41ab a CYREG_UDB_DSI1_HV_R3
400f41ac a CYREG_UDB_DSI1_HV_R4
400f41ac a CYREG_UDB_DSI1_HV_R4
400f41ad a CYREG_UDB_DSI1_HV_R5
400f41ad a CYREG_UDB_DSI1_HV_R5
400f41ae a CYREG_UDB_DSI1_HV_R6
400f41ae a CYREG_UDB_DSI1_HV_R6
400f41af a CYREG_UDB_DSI1_HV_R7
400f41af a CYREG_UDB_DSI1_HV_R7
400f41b0 a CYREG_UDB_DSI1_HV_R8
400f41b0 a CYREG_UDB_DSI1_HV_R8
400f41b1 a CYREG_UDB_DSI1_HV_R9
400f41b1 a CYREG_UDB_DSI1_HV_R9
400f41e0 a CYREG_UDB_DSI1_VS0
400f41e0 a CYREG_UDB_DSI1_VS0
400f41e2 a CYREG_UDB_DSI1_VS1
400f41e2 a CYREG_UDB_DSI1_VS1
400f41e4 a CYREG_UDB_DSI1_VS2
400f41e4 a CYREG_UDB_DSI1_VS2
400f41e6 a CYREG_UDB_DSI1_VS3
400f41e6 a CYREG_UDB_DSI1_VS3
400f41e8 a CYREG_UDB_DSI1_VS4
400f41e8 a CYREG_UDB_DSI1_VS4
400f41ea a CYREG_UDB_DSI1_VS5
400f41ea a CYREG_UDB_DSI1_VS5
400f41ec a CYREG_UDB_DSI1_VS6
400f41ec a CYREG_UDB_DSI1_VS6
400f41ee a CYREG_UDB_DSI1_VS7
400f41ee a CYREG_UDB_DSI1_VS7
400f42c0 a CYREG_UDB_DSI2_DSIINP0
400f42c0 a CYREG_UDB_DSI2_DSIINP0
400f42c2 a CYREG_UDB_DSI2_DSIINP1
400f42c2 a CYREG_UDB_DSI2_DSIINP1
400f42c4 a CYREG_UDB_DSI2_DSIINP2
400f42c4 a CYREG_UDB_DSI2_DSIINP2
400f42c6 a CYREG_UDB_DSI2_DSIINP3
400f42c6 a CYREG_UDB_DSI2_DSIINP3
400f42c8 a CYREG_UDB_DSI2_DSIINP4
400f42c8 a CYREG_UDB_DSI2_DSIINP4
400f42ca a CYREG_UDB_DSI2_DSIINP5
400f42ca a CYREG_UDB_DSI2_DSIINP5
400f42cc a CYREG_UDB_DSI2_DSIOUTP0
400f42cc a CYREG_UDB_DSI2_DSIOUTP0
400f42ce a CYREG_UDB_DSI2_DSIOUTP1
400f42ce a CYREG_UDB_DSI2_DSIOUTP1
400f42d0 a CYREG_UDB_DSI2_DSIOUTP2
400f42d0 a CYREG_UDB_DSI2_DSIOUTP2
400f42d2 a CYREG_UDB_DSI2_DSIOUTP3
400f42d2 a CYREG_UDB_DSI2_DSIOUTP3
400f42d4 a CYREG_UDB_DSI2_DSIOUTT0
400f42d4 a CYREG_UDB_DSI2_DSIOUTT0
400f42d6 a CYREG_UDB_DSI2_DSIOUTT1
400f42d6 a CYREG_UDB_DSI2_DSIOUTT1
400f42d8 a CYREG_UDB_DSI2_DSIOUTT2
400f42d8 a CYREG_UDB_DSI2_DSIOUTT2
400f42da a CYREG_UDB_DSI2_DSIOUTT3
400f42da a CYREG_UDB_DSI2_DSIOUTT3
400f42dc a CYREG_UDB_DSI2_DSIOUTT4
400f42dc a CYREG_UDB_DSI2_DSIOUTT4
400f42de a CYREG_UDB_DSI2_DSIOUTT5
400f42de a CYREG_UDB_DSI2_DSIOUTT5
400f4200 a CYREG_UDB_DSI2_HC0
400f4200 a CYREG_UDB_DSI2_HC0
400f4201 a CYREG_UDB_DSI2_HC1
400f4201 a CYREG_UDB_DSI2_HC1
400f420a a CYREG_UDB_DSI2_HC10
400f420a a CYREG_UDB_DSI2_HC10
400f4264 a CYREG_UDB_DSI2_HC100
400f4264 a CYREG_UDB_DSI2_HC100
400f4265 a CYREG_UDB_DSI2_HC101
400f4265 a CYREG_UDB_DSI2_HC101
400f4266 a CYREG_UDB_DSI2_HC102
400f4266 a CYREG_UDB_DSI2_HC102
400f4267 a CYREG_UDB_DSI2_HC103
400f4267 a CYREG_UDB_DSI2_HC103
400f4268 a CYREG_UDB_DSI2_HC104
400f4268 a CYREG_UDB_DSI2_HC104
400f4269 a CYREG_UDB_DSI2_HC105
400f4269 a CYREG_UDB_DSI2_HC105
400f426a a CYREG_UDB_DSI2_HC106
400f426a a CYREG_UDB_DSI2_HC106
400f426b a CYREG_UDB_DSI2_HC107
400f426b a CYREG_UDB_DSI2_HC107
400f426c a CYREG_UDB_DSI2_HC108
400f426c a CYREG_UDB_DSI2_HC108
400f426d a CYREG_UDB_DSI2_HC109
400f426d a CYREG_UDB_DSI2_HC109
400f420b a CYREG_UDB_DSI2_HC11
400f420b a CYREG_UDB_DSI2_HC11
400f426e a CYREG_UDB_DSI2_HC110
400f426e a CYREG_UDB_DSI2_HC110
400f426f a CYREG_UDB_DSI2_HC111
400f426f a CYREG_UDB_DSI2_HC111
400f4270 a CYREG_UDB_DSI2_HC112
400f4270 a CYREG_UDB_DSI2_HC112
400f4271 a CYREG_UDB_DSI2_HC113
400f4271 a CYREG_UDB_DSI2_HC113
400f4272 a CYREG_UDB_DSI2_HC114
400f4272 a CYREG_UDB_DSI2_HC114
400f4273 a CYREG_UDB_DSI2_HC115
400f4273 a CYREG_UDB_DSI2_HC115
400f4274 a CYREG_UDB_DSI2_HC116
400f4274 a CYREG_UDB_DSI2_HC116
400f4275 a CYREG_UDB_DSI2_HC117
400f4275 a CYREG_UDB_DSI2_HC117
400f4276 a CYREG_UDB_DSI2_HC118
400f4276 a CYREG_UDB_DSI2_HC118
400f4277 a CYREG_UDB_DSI2_HC119
400f4277 a CYREG_UDB_DSI2_HC119
400f420c a CYREG_UDB_DSI2_HC12
400f420c a CYREG_UDB_DSI2_HC12
400f4278 a CYREG_UDB_DSI2_HC120
400f4278 a CYREG_UDB_DSI2_HC120
400f4279 a CYREG_UDB_DSI2_HC121
400f4279 a CYREG_UDB_DSI2_HC121
400f427a a CYREG_UDB_DSI2_HC122
400f427a a CYREG_UDB_DSI2_HC122
400f427b a CYREG_UDB_DSI2_HC123
400f427b a CYREG_UDB_DSI2_HC123
400f427c a CYREG_UDB_DSI2_HC124
400f427c a CYREG_UDB_DSI2_HC124
400f427d a CYREG_UDB_DSI2_HC125
400f427d a CYREG_UDB_DSI2_HC125
400f427e a CYREG_UDB_DSI2_HC126
400f427e a CYREG_UDB_DSI2_HC126
400f427f a CYREG_UDB_DSI2_HC127
400f427f a CYREG_UDB_DSI2_HC127
400f420d a CYREG_UDB_DSI2_HC13
400f420d a CYREG_UDB_DSI2_HC13
400f420e a CYREG_UDB_DSI2_HC14
400f420e a CYREG_UDB_DSI2_HC14
400f420f a CYREG_UDB_DSI2_HC15
400f420f a CYREG_UDB_DSI2_HC15
400f4210 a CYREG_UDB_DSI2_HC16
400f4210 a CYREG_UDB_DSI2_HC16
400f4211 a CYREG_UDB_DSI2_HC17
400f4211 a CYREG_UDB_DSI2_HC17
400f4212 a CYREG_UDB_DSI2_HC18
400f4212 a CYREG_UDB_DSI2_HC18
400f4213 a CYREG_UDB_DSI2_HC19
400f4213 a CYREG_UDB_DSI2_HC19
400f4202 a CYREG_UDB_DSI2_HC2
400f4202 a CYREG_UDB_DSI2_HC2
400f4214 a CYREG_UDB_DSI2_HC20
400f4214 a CYREG_UDB_DSI2_HC20
400f4215 a CYREG_UDB_DSI2_HC21
400f4215 a CYREG_UDB_DSI2_HC21
400f4216 a CYREG_UDB_DSI2_HC22
400f4216 a CYREG_UDB_DSI2_HC22
400f4217 a CYREG_UDB_DSI2_HC23
400f4217 a CYREG_UDB_DSI2_HC23
400f4218 a CYREG_UDB_DSI2_HC24
400f4218 a CYREG_UDB_DSI2_HC24
400f4219 a CYREG_UDB_DSI2_HC25
400f4219 a CYREG_UDB_DSI2_HC25
400f421a a CYREG_UDB_DSI2_HC26
400f421a a CYREG_UDB_DSI2_HC26
400f421b a CYREG_UDB_DSI2_HC27
400f421b a CYREG_UDB_DSI2_HC27
400f421c a CYREG_UDB_DSI2_HC28
400f421c a CYREG_UDB_DSI2_HC28
400f421d a CYREG_UDB_DSI2_HC29
400f421d a CYREG_UDB_DSI2_HC29
400f4203 a CYREG_UDB_DSI2_HC3
400f4203 a CYREG_UDB_DSI2_HC3
400f421e a CYREG_UDB_DSI2_HC30
400f421e a CYREG_UDB_DSI2_HC30
400f421f a CYREG_UDB_DSI2_HC31
400f421f a CYREG_UDB_DSI2_HC31
400f4220 a CYREG_UDB_DSI2_HC32
400f4220 a CYREG_UDB_DSI2_HC32
400f4221 a CYREG_UDB_DSI2_HC33
400f4221 a CYREG_UDB_DSI2_HC33
400f4222 a CYREG_UDB_DSI2_HC34
400f4222 a CYREG_UDB_DSI2_HC34
400f4223 a CYREG_UDB_DSI2_HC35
400f4223 a CYREG_UDB_DSI2_HC35
400f4224 a CYREG_UDB_DSI2_HC36
400f4224 a CYREG_UDB_DSI2_HC36
400f4225 a CYREG_UDB_DSI2_HC37
400f4225 a CYREG_UDB_DSI2_HC37
400f4226 a CYREG_UDB_DSI2_HC38
400f4226 a CYREG_UDB_DSI2_HC38
400f4227 a CYREG_UDB_DSI2_HC39
400f4227 a CYREG_UDB_DSI2_HC39
400f4204 a CYREG_UDB_DSI2_HC4
400f4204 a CYREG_UDB_DSI2_HC4
400f4228 a CYREG_UDB_DSI2_HC40
400f4228 a CYREG_UDB_DSI2_HC40
400f4229 a CYREG_UDB_DSI2_HC41
400f4229 a CYREG_UDB_DSI2_HC41
400f422a a CYREG_UDB_DSI2_HC42
400f422a a CYREG_UDB_DSI2_HC42
400f422b a CYREG_UDB_DSI2_HC43
400f422b a CYREG_UDB_DSI2_HC43
400f422c a CYREG_UDB_DSI2_HC44
400f422c a CYREG_UDB_DSI2_HC44
400f422d a CYREG_UDB_DSI2_HC45
400f422d a CYREG_UDB_DSI2_HC45
400f422e a CYREG_UDB_DSI2_HC46
400f422e a CYREG_UDB_DSI2_HC46
400f422f a CYREG_UDB_DSI2_HC47
400f422f a CYREG_UDB_DSI2_HC47
400f4230 a CYREG_UDB_DSI2_HC48
400f4230 a CYREG_UDB_DSI2_HC48
400f4231 a CYREG_UDB_DSI2_HC49
400f4231 a CYREG_UDB_DSI2_HC49
400f4205 a CYREG_UDB_DSI2_HC5
400f4205 a CYREG_UDB_DSI2_HC5
400f4232 a CYREG_UDB_DSI2_HC50
400f4232 a CYREG_UDB_DSI2_HC50
400f4233 a CYREG_UDB_DSI2_HC51
400f4233 a CYREG_UDB_DSI2_HC51
400f4234 a CYREG_UDB_DSI2_HC52
400f4234 a CYREG_UDB_DSI2_HC52
400f4235 a CYREG_UDB_DSI2_HC53
400f4235 a CYREG_UDB_DSI2_HC53
400f4236 a CYREG_UDB_DSI2_HC54
400f4236 a CYREG_UDB_DSI2_HC54
400f4237 a CYREG_UDB_DSI2_HC55
400f4237 a CYREG_UDB_DSI2_HC55
400f4238 a CYREG_UDB_DSI2_HC56
400f4238 a CYREG_UDB_DSI2_HC56
400f4239 a CYREG_UDB_DSI2_HC57
400f4239 a CYREG_UDB_DSI2_HC57
400f423a a CYREG_UDB_DSI2_HC58
400f423a a CYREG_UDB_DSI2_HC58
400f423b a CYREG_UDB_DSI2_HC59
400f423b a CYREG_UDB_DSI2_HC59
400f4206 a CYREG_UDB_DSI2_HC6
400f4206 a CYREG_UDB_DSI2_HC6
400f423c a CYREG_UDB_DSI2_HC60
400f423c a CYREG_UDB_DSI2_HC60
400f423d a CYREG_UDB_DSI2_HC61
400f423d a CYREG_UDB_DSI2_HC61
400f423e a CYREG_UDB_DSI2_HC62
400f423e a CYREG_UDB_DSI2_HC62
400f423f a CYREG_UDB_DSI2_HC63
400f423f a CYREG_UDB_DSI2_HC63
400f4240 a CYREG_UDB_DSI2_HC64
400f4240 a CYREG_UDB_DSI2_HC64
400f4241 a CYREG_UDB_DSI2_HC65
400f4241 a CYREG_UDB_DSI2_HC65
400f4242 a CYREG_UDB_DSI2_HC66
400f4242 a CYREG_UDB_DSI2_HC66
400f4243 a CYREG_UDB_DSI2_HC67
400f4243 a CYREG_UDB_DSI2_HC67
400f4244 a CYREG_UDB_DSI2_HC68
400f4244 a CYREG_UDB_DSI2_HC68
400f4245 a CYREG_UDB_DSI2_HC69
400f4245 a CYREG_UDB_DSI2_HC69
400f4207 a CYREG_UDB_DSI2_HC7
400f4207 a CYREG_UDB_DSI2_HC7
400f4246 a CYREG_UDB_DSI2_HC70
400f4246 a CYREG_UDB_DSI2_HC70
400f4247 a CYREG_UDB_DSI2_HC71
400f4247 a CYREG_UDB_DSI2_HC71
400f4248 a CYREG_UDB_DSI2_HC72
400f4248 a CYREG_UDB_DSI2_HC72
400f4249 a CYREG_UDB_DSI2_HC73
400f4249 a CYREG_UDB_DSI2_HC73
400f424a a CYREG_UDB_DSI2_HC74
400f424a a CYREG_UDB_DSI2_HC74
400f424b a CYREG_UDB_DSI2_HC75
400f424b a CYREG_UDB_DSI2_HC75
400f424c a CYREG_UDB_DSI2_HC76
400f424c a CYREG_UDB_DSI2_HC76
400f424d a CYREG_UDB_DSI2_HC77
400f424d a CYREG_UDB_DSI2_HC77
400f424e a CYREG_UDB_DSI2_HC78
400f424e a CYREG_UDB_DSI2_HC78
400f424f a CYREG_UDB_DSI2_HC79
400f424f a CYREG_UDB_DSI2_HC79
400f4208 a CYREG_UDB_DSI2_HC8
400f4208 a CYREG_UDB_DSI2_HC8
400f4250 a CYREG_UDB_DSI2_HC80
400f4250 a CYREG_UDB_DSI2_HC80
400f4251 a CYREG_UDB_DSI2_HC81
400f4251 a CYREG_UDB_DSI2_HC81
400f4252 a CYREG_UDB_DSI2_HC82
400f4252 a CYREG_UDB_DSI2_HC82
400f4253 a CYREG_UDB_DSI2_HC83
400f4253 a CYREG_UDB_DSI2_HC83
400f4254 a CYREG_UDB_DSI2_HC84
400f4254 a CYREG_UDB_DSI2_HC84
400f4255 a CYREG_UDB_DSI2_HC85
400f4255 a CYREG_UDB_DSI2_HC85
400f4256 a CYREG_UDB_DSI2_HC86
400f4256 a CYREG_UDB_DSI2_HC86
400f4257 a CYREG_UDB_DSI2_HC87
400f4257 a CYREG_UDB_DSI2_HC87
400f4258 a CYREG_UDB_DSI2_HC88
400f4258 a CYREG_UDB_DSI2_HC88
400f4259 a CYREG_UDB_DSI2_HC89
400f4259 a CYREG_UDB_DSI2_HC89
400f4209 a CYREG_UDB_DSI2_HC9
400f4209 a CYREG_UDB_DSI2_HC9
400f425a a CYREG_UDB_DSI2_HC90
400f425a a CYREG_UDB_DSI2_HC90
400f425b a CYREG_UDB_DSI2_HC91
400f425b a CYREG_UDB_DSI2_HC91
400f425c a CYREG_UDB_DSI2_HC92
400f425c a CYREG_UDB_DSI2_HC92
400f425d a CYREG_UDB_DSI2_HC93
400f425d a CYREG_UDB_DSI2_HC93
400f425e a CYREG_UDB_DSI2_HC94
400f425e a CYREG_UDB_DSI2_HC94
400f425f a CYREG_UDB_DSI2_HC95
400f425f a CYREG_UDB_DSI2_HC95
400f4260 a CYREG_UDB_DSI2_HC96
400f4260 a CYREG_UDB_DSI2_HC96
400f4261 a CYREG_UDB_DSI2_HC97
400f4261 a CYREG_UDB_DSI2_HC97
400f4262 a CYREG_UDB_DSI2_HC98
400f4262 a CYREG_UDB_DSI2_HC98
400f4263 a CYREG_UDB_DSI2_HC99
400f4263 a CYREG_UDB_DSI2_HC99
400f4290 a CYREG_UDB_DSI2_HS0
400f4290 a CYREG_UDB_DSI2_HS0
400f4291 a CYREG_UDB_DSI2_HS1
400f4291 a CYREG_UDB_DSI2_HS1
400f429a a CYREG_UDB_DSI2_HS10
400f429a a CYREG_UDB_DSI2_HS10
400f429b a CYREG_UDB_DSI2_HS11
400f429b a CYREG_UDB_DSI2_HS11
400f429c a CYREG_UDB_DSI2_HS12
400f429c a CYREG_UDB_DSI2_HS12
400f429d a CYREG_UDB_DSI2_HS13
400f429d a CYREG_UDB_DSI2_HS13
400f429e a CYREG_UDB_DSI2_HS14
400f429e a CYREG_UDB_DSI2_HS14
400f429f a CYREG_UDB_DSI2_HS15
400f429f a CYREG_UDB_DSI2_HS15
400f42a0 a CYREG_UDB_DSI2_HS16
400f42a0 a CYREG_UDB_DSI2_HS16
400f42a1 a CYREG_UDB_DSI2_HS17
400f42a1 a CYREG_UDB_DSI2_HS17
400f42a2 a CYREG_UDB_DSI2_HS18
400f42a2 a CYREG_UDB_DSI2_HS18
400f42a3 a CYREG_UDB_DSI2_HS19
400f42a3 a CYREG_UDB_DSI2_HS19
400f4292 a CYREG_UDB_DSI2_HS2
400f4292 a CYREG_UDB_DSI2_HS2
400f42a4 a CYREG_UDB_DSI2_HS20
400f42a4 a CYREG_UDB_DSI2_HS20
400f42a5 a CYREG_UDB_DSI2_HS21
400f42a5 a CYREG_UDB_DSI2_HS21
400f42a6 a CYREG_UDB_DSI2_HS22
400f42a6 a CYREG_UDB_DSI2_HS22
400f42a7 a CYREG_UDB_DSI2_HS23
400f42a7 a CYREG_UDB_DSI2_HS23
400f4293 a CYREG_UDB_DSI2_HS3
400f4293 a CYREG_UDB_DSI2_HS3
400f4294 a CYREG_UDB_DSI2_HS4
400f4294 a CYREG_UDB_DSI2_HS4
400f4295 a CYREG_UDB_DSI2_HS5
400f4295 a CYREG_UDB_DSI2_HS5
400f4296 a CYREG_UDB_DSI2_HS6
400f4296 a CYREG_UDB_DSI2_HS6
400f4297 a CYREG_UDB_DSI2_HS7
400f4297 a CYREG_UDB_DSI2_HS7
400f4298 a CYREG_UDB_DSI2_HS8
400f4298 a CYREG_UDB_DSI2_HS8
400f4299 a CYREG_UDB_DSI2_HS9
400f4299 a CYREG_UDB_DSI2_HS9
400f4280 a CYREG_UDB_DSI2_HV_L0
400f4280 a CYREG_UDB_DSI2_HV_L0
400f4281 a CYREG_UDB_DSI2_HV_L1
400f4281 a CYREG_UDB_DSI2_HV_L1
400f428a a CYREG_UDB_DSI2_HV_L10
400f428a a CYREG_UDB_DSI2_HV_L10
400f428b a CYREG_UDB_DSI2_HV_L11
400f428b a CYREG_UDB_DSI2_HV_L11
400f428c a CYREG_UDB_DSI2_HV_L12
400f428c a CYREG_UDB_DSI2_HV_L12
400f428d a CYREG_UDB_DSI2_HV_L13
400f428d a CYREG_UDB_DSI2_HV_L13
400f428e a CYREG_UDB_DSI2_HV_L14
400f428e a CYREG_UDB_DSI2_HV_L14
400f428f a CYREG_UDB_DSI2_HV_L15
400f428f a CYREG_UDB_DSI2_HV_L15
400f4282 a CYREG_UDB_DSI2_HV_L2
400f4282 a CYREG_UDB_DSI2_HV_L2
400f4283 a CYREG_UDB_DSI2_HV_L3
400f4283 a CYREG_UDB_DSI2_HV_L3
400f4284 a CYREG_UDB_DSI2_HV_L4
400f4284 a CYREG_UDB_DSI2_HV_L4
400f4285 a CYREG_UDB_DSI2_HV_L5
400f4285 a CYREG_UDB_DSI2_HV_L5
400f4286 a CYREG_UDB_DSI2_HV_L6
400f4286 a CYREG_UDB_DSI2_HV_L6
400f4287 a CYREG_UDB_DSI2_HV_L7
400f4287 a CYREG_UDB_DSI2_HV_L7
400f4288 a CYREG_UDB_DSI2_HV_L8
400f4288 a CYREG_UDB_DSI2_HV_L8
400f4289 a CYREG_UDB_DSI2_HV_L9
400f4289 a CYREG_UDB_DSI2_HV_L9
400f42a8 a CYREG_UDB_DSI2_HV_R0
400f42a8 a CYREG_UDB_DSI2_HV_R0
400f42a9 a CYREG_UDB_DSI2_HV_R1
400f42a9 a CYREG_UDB_DSI2_HV_R1
400f42b2 a CYREG_UDB_DSI2_HV_R10
400f42b2 a CYREG_UDB_DSI2_HV_R10
400f42b3 a CYREG_UDB_DSI2_HV_R11
400f42b3 a CYREG_UDB_DSI2_HV_R11
400f42b4 a CYREG_UDB_DSI2_HV_R12
400f42b4 a CYREG_UDB_DSI2_HV_R12
400f42b5 a CYREG_UDB_DSI2_HV_R13
400f42b5 a CYREG_UDB_DSI2_HV_R13
400f42b6 a CYREG_UDB_DSI2_HV_R14
400f42b6 a CYREG_UDB_DSI2_HV_R14
400f42b7 a CYREG_UDB_DSI2_HV_R15
400f42b7 a CYREG_UDB_DSI2_HV_R15
400f42aa a CYREG_UDB_DSI2_HV_R2
400f42aa a CYREG_UDB_DSI2_HV_R2
400f42ab a CYREG_UDB_DSI2_HV_R3
400f42ab a CYREG_UDB_DSI2_HV_R3
400f42ac a CYREG_UDB_DSI2_HV_R4
400f42ac a CYREG_UDB_DSI2_HV_R4
400f42ad a CYREG_UDB_DSI2_HV_R5
400f42ad a CYREG_UDB_DSI2_HV_R5
400f42ae a CYREG_UDB_DSI2_HV_R6
400f42ae a CYREG_UDB_DSI2_HV_R6
400f42af a CYREG_UDB_DSI2_HV_R7
400f42af a CYREG_UDB_DSI2_HV_R7
400f42b0 a CYREG_UDB_DSI2_HV_R8
400f42b0 a CYREG_UDB_DSI2_HV_R8
400f42b1 a CYREG_UDB_DSI2_HV_R9
400f42b1 a CYREG_UDB_DSI2_HV_R9
400f42e0 a CYREG_UDB_DSI2_VS0
400f42e0 a CYREG_UDB_DSI2_VS0
400f42e2 a CYREG_UDB_DSI2_VS1
400f42e2 a CYREG_UDB_DSI2_VS1
400f42e4 a CYREG_UDB_DSI2_VS2
400f42e4 a CYREG_UDB_DSI2_VS2
400f42e6 a CYREG_UDB_DSI2_VS3
400f42e6 a CYREG_UDB_DSI2_VS3
400f42e8 a CYREG_UDB_DSI2_VS4
400f42e8 a CYREG_UDB_DSI2_VS4
400f42ea a CYREG_UDB_DSI2_VS5
400f42ea a CYREG_UDB_DSI2_VS5
400f42ec a CYREG_UDB_DSI2_VS6
400f42ec a CYREG_UDB_DSI2_VS6
400f42ee a CYREG_UDB_DSI2_VS7
400f42ee a CYREG_UDB_DSI2_VS7
400f43c0 a CYREG_UDB_DSI3_DSIINP0
400f43c0 a CYREG_UDB_DSI3_DSIINP0
400f43c2 a CYREG_UDB_DSI3_DSIINP1
400f43c2 a CYREG_UDB_DSI3_DSIINP1
400f43c4 a CYREG_UDB_DSI3_DSIINP2
400f43c4 a CYREG_UDB_DSI3_DSIINP2
400f43c6 a CYREG_UDB_DSI3_DSIINP3
400f43c6 a CYREG_UDB_DSI3_DSIINP3
400f43c8 a CYREG_UDB_DSI3_DSIINP4
400f43c8 a CYREG_UDB_DSI3_DSIINP4
400f43ca a CYREG_UDB_DSI3_DSIINP5
400f43ca a CYREG_UDB_DSI3_DSIINP5
400f43cc a CYREG_UDB_DSI3_DSIOUTP0
400f43cc a CYREG_UDB_DSI3_DSIOUTP0
400f43ce a CYREG_UDB_DSI3_DSIOUTP1
400f43ce a CYREG_UDB_DSI3_DSIOUTP1
400f43d0 a CYREG_UDB_DSI3_DSIOUTP2
400f43d0 a CYREG_UDB_DSI3_DSIOUTP2
400f43d2 a CYREG_UDB_DSI3_DSIOUTP3
400f43d2 a CYREG_UDB_DSI3_DSIOUTP3
400f43d4 a CYREG_UDB_DSI3_DSIOUTT0
400f43d4 a CYREG_UDB_DSI3_DSIOUTT0
400f43d6 a CYREG_UDB_DSI3_DSIOUTT1
400f43d6 a CYREG_UDB_DSI3_DSIOUTT1
400f43d8 a CYREG_UDB_DSI3_DSIOUTT2
400f43d8 a CYREG_UDB_DSI3_DSIOUTT2
400f43da a CYREG_UDB_DSI3_DSIOUTT3
400f43da a CYREG_UDB_DSI3_DSIOUTT3
400f43dc a CYREG_UDB_DSI3_DSIOUTT4
400f43dc a CYREG_UDB_DSI3_DSIOUTT4
400f43de a CYREG_UDB_DSI3_DSIOUTT5
400f43de a CYREG_UDB_DSI3_DSIOUTT5
400f4300 a CYREG_UDB_DSI3_HC0
400f4300 a CYREG_UDB_DSI3_HC0
400f4301 a CYREG_UDB_DSI3_HC1
400f4301 a CYREG_UDB_DSI3_HC1
400f430a a CYREG_UDB_DSI3_HC10
400f430a a CYREG_UDB_DSI3_HC10
400f4364 a CYREG_UDB_DSI3_HC100
400f4364 a CYREG_UDB_DSI3_HC100
400f4365 a CYREG_UDB_DSI3_HC101
400f4365 a CYREG_UDB_DSI3_HC101
400f4366 a CYREG_UDB_DSI3_HC102
400f4366 a CYREG_UDB_DSI3_HC102
400f4367 a CYREG_UDB_DSI3_HC103
400f4367 a CYREG_UDB_DSI3_HC103
400f4368 a CYREG_UDB_DSI3_HC104
400f4368 a CYREG_UDB_DSI3_HC104
400f4369 a CYREG_UDB_DSI3_HC105
400f4369 a CYREG_UDB_DSI3_HC105
400f436a a CYREG_UDB_DSI3_HC106
400f436a a CYREG_UDB_DSI3_HC106
400f436b a CYREG_UDB_DSI3_HC107
400f436b a CYREG_UDB_DSI3_HC107
400f436c a CYREG_UDB_DSI3_HC108
400f436c a CYREG_UDB_DSI3_HC108
400f436d a CYREG_UDB_DSI3_HC109
400f436d a CYREG_UDB_DSI3_HC109
400f430b a CYREG_UDB_DSI3_HC11
400f430b a CYREG_UDB_DSI3_HC11
400f436e a CYREG_UDB_DSI3_HC110
400f436e a CYREG_UDB_DSI3_HC110
400f436f a CYREG_UDB_DSI3_HC111
400f436f a CYREG_UDB_DSI3_HC111
400f4370 a CYREG_UDB_DSI3_HC112
400f4370 a CYREG_UDB_DSI3_HC112
400f4371 a CYREG_UDB_DSI3_HC113
400f4371 a CYREG_UDB_DSI3_HC113
400f4372 a CYREG_UDB_DSI3_HC114
400f4372 a CYREG_UDB_DSI3_HC114
400f4373 a CYREG_UDB_DSI3_HC115
400f4373 a CYREG_UDB_DSI3_HC115
400f4374 a CYREG_UDB_DSI3_HC116
400f4374 a CYREG_UDB_DSI3_HC116
400f4375 a CYREG_UDB_DSI3_HC117
400f4375 a CYREG_UDB_DSI3_HC117
400f4376 a CYREG_UDB_DSI3_HC118
400f4376 a CYREG_UDB_DSI3_HC118
400f4377 a CYREG_UDB_DSI3_HC119
400f4377 a CYREG_UDB_DSI3_HC119
400f430c a CYREG_UDB_DSI3_HC12
400f430c a CYREG_UDB_DSI3_HC12
400f4378 a CYREG_UDB_DSI3_HC120
400f4378 a CYREG_UDB_DSI3_HC120
400f4379 a CYREG_UDB_DSI3_HC121
400f4379 a CYREG_UDB_DSI3_HC121
400f437a a CYREG_UDB_DSI3_HC122
400f437a a CYREG_UDB_DSI3_HC122
400f437b a CYREG_UDB_DSI3_HC123
400f437b a CYREG_UDB_DSI3_HC123
400f437c a CYREG_UDB_DSI3_HC124
400f437c a CYREG_UDB_DSI3_HC124
400f437d a CYREG_UDB_DSI3_HC125
400f437d a CYREG_UDB_DSI3_HC125
400f437e a CYREG_UDB_DSI3_HC126
400f437e a CYREG_UDB_DSI3_HC126
400f437f a CYREG_UDB_DSI3_HC127
400f437f a CYREG_UDB_DSI3_HC127
400f430d a CYREG_UDB_DSI3_HC13
400f430d a CYREG_UDB_DSI3_HC13
400f430e a CYREG_UDB_DSI3_HC14
400f430e a CYREG_UDB_DSI3_HC14
400f430f a CYREG_UDB_DSI3_HC15
400f430f a CYREG_UDB_DSI3_HC15
400f4310 a CYREG_UDB_DSI3_HC16
400f4310 a CYREG_UDB_DSI3_HC16
400f4311 a CYREG_UDB_DSI3_HC17
400f4311 a CYREG_UDB_DSI3_HC17
400f4312 a CYREG_UDB_DSI3_HC18
400f4312 a CYREG_UDB_DSI3_HC18
400f4313 a CYREG_UDB_DSI3_HC19
400f4313 a CYREG_UDB_DSI3_HC19
400f4302 a CYREG_UDB_DSI3_HC2
400f4302 a CYREG_UDB_DSI3_HC2
400f4314 a CYREG_UDB_DSI3_HC20
400f4314 a CYREG_UDB_DSI3_HC20
400f4315 a CYREG_UDB_DSI3_HC21
400f4315 a CYREG_UDB_DSI3_HC21
400f4316 a CYREG_UDB_DSI3_HC22
400f4316 a CYREG_UDB_DSI3_HC22
400f4317 a CYREG_UDB_DSI3_HC23
400f4317 a CYREG_UDB_DSI3_HC23
400f4318 a CYREG_UDB_DSI3_HC24
400f4318 a CYREG_UDB_DSI3_HC24
400f4319 a CYREG_UDB_DSI3_HC25
400f4319 a CYREG_UDB_DSI3_HC25
400f431a a CYREG_UDB_DSI3_HC26
400f431a a CYREG_UDB_DSI3_HC26
400f431b a CYREG_UDB_DSI3_HC27
400f431b a CYREG_UDB_DSI3_HC27
400f431c a CYREG_UDB_DSI3_HC28
400f431c a CYREG_UDB_DSI3_HC28
400f431d a CYREG_UDB_DSI3_HC29
400f431d a CYREG_UDB_DSI3_HC29
400f4303 a CYREG_UDB_DSI3_HC3
400f4303 a CYREG_UDB_DSI3_HC3
400f431e a CYREG_UDB_DSI3_HC30
400f431e a CYREG_UDB_DSI3_HC30
400f431f a CYREG_UDB_DSI3_HC31
400f431f a CYREG_UDB_DSI3_HC31
400f4320 a CYREG_UDB_DSI3_HC32
400f4320 a CYREG_UDB_DSI3_HC32
400f4321 a CYREG_UDB_DSI3_HC33
400f4321 a CYREG_UDB_DSI3_HC33
400f4322 a CYREG_UDB_DSI3_HC34
400f4322 a CYREG_UDB_DSI3_HC34
400f4323 a CYREG_UDB_DSI3_HC35
400f4323 a CYREG_UDB_DSI3_HC35
400f4324 a CYREG_UDB_DSI3_HC36
400f4324 a CYREG_UDB_DSI3_HC36
400f4325 a CYREG_UDB_DSI3_HC37
400f4325 a CYREG_UDB_DSI3_HC37
400f4326 a CYREG_UDB_DSI3_HC38
400f4326 a CYREG_UDB_DSI3_HC38
400f4327 a CYREG_UDB_DSI3_HC39
400f4327 a CYREG_UDB_DSI3_HC39
400f4304 a CYREG_UDB_DSI3_HC4
400f4304 a CYREG_UDB_DSI3_HC4
400f4328 a CYREG_UDB_DSI3_HC40
400f4328 a CYREG_UDB_DSI3_HC40
400f4329 a CYREG_UDB_DSI3_HC41
400f4329 a CYREG_UDB_DSI3_HC41
400f432a a CYREG_UDB_DSI3_HC42
400f432a a CYREG_UDB_DSI3_HC42
400f432b a CYREG_UDB_DSI3_HC43
400f432b a CYREG_UDB_DSI3_HC43
400f432c a CYREG_UDB_DSI3_HC44
400f432c a CYREG_UDB_DSI3_HC44
400f432d a CYREG_UDB_DSI3_HC45
400f432d a CYREG_UDB_DSI3_HC45
400f432e a CYREG_UDB_DSI3_HC46
400f432e a CYREG_UDB_DSI3_HC46
400f432f a CYREG_UDB_DSI3_HC47
400f432f a CYREG_UDB_DSI3_HC47
400f4330 a CYREG_UDB_DSI3_HC48
400f4330 a CYREG_UDB_DSI3_HC48
400f4331 a CYREG_UDB_DSI3_HC49
400f4331 a CYREG_UDB_DSI3_HC49
400f4305 a CYREG_UDB_DSI3_HC5
400f4305 a CYREG_UDB_DSI3_HC5
400f4332 a CYREG_UDB_DSI3_HC50
400f4332 a CYREG_UDB_DSI3_HC50
400f4333 a CYREG_UDB_DSI3_HC51
400f4333 a CYREG_UDB_DSI3_HC51
400f4334 a CYREG_UDB_DSI3_HC52
400f4334 a CYREG_UDB_DSI3_HC52
400f4335 a CYREG_UDB_DSI3_HC53
400f4335 a CYREG_UDB_DSI3_HC53
400f4336 a CYREG_UDB_DSI3_HC54
400f4336 a CYREG_UDB_DSI3_HC54
400f4337 a CYREG_UDB_DSI3_HC55
400f4337 a CYREG_UDB_DSI3_HC55
400f4338 a CYREG_UDB_DSI3_HC56
400f4338 a CYREG_UDB_DSI3_HC56
400f4339 a CYREG_UDB_DSI3_HC57
400f4339 a CYREG_UDB_DSI3_HC57
400f433a a CYREG_UDB_DSI3_HC58
400f433a a CYREG_UDB_DSI3_HC58
400f433b a CYREG_UDB_DSI3_HC59
400f433b a CYREG_UDB_DSI3_HC59
400f4306 a CYREG_UDB_DSI3_HC6
400f4306 a CYREG_UDB_DSI3_HC6
400f433c a CYREG_UDB_DSI3_HC60
400f433c a CYREG_UDB_DSI3_HC60
400f433d a CYREG_UDB_DSI3_HC61
400f433d a CYREG_UDB_DSI3_HC61
400f433e a CYREG_UDB_DSI3_HC62
400f433e a CYREG_UDB_DSI3_HC62
400f433f a CYREG_UDB_DSI3_HC63
400f433f a CYREG_UDB_DSI3_HC63
400f4340 a CYREG_UDB_DSI3_HC64
400f4340 a CYREG_UDB_DSI3_HC64
400f4341 a CYREG_UDB_DSI3_HC65
400f4341 a CYREG_UDB_DSI3_HC65
400f4342 a CYREG_UDB_DSI3_HC66
400f4342 a CYREG_UDB_DSI3_HC66
400f4343 a CYREG_UDB_DSI3_HC67
400f4343 a CYREG_UDB_DSI3_HC67
400f4344 a CYREG_UDB_DSI3_HC68
400f4344 a CYREG_UDB_DSI3_HC68
400f4345 a CYREG_UDB_DSI3_HC69
400f4345 a CYREG_UDB_DSI3_HC69
400f4307 a CYREG_UDB_DSI3_HC7
400f4307 a CYREG_UDB_DSI3_HC7
400f4346 a CYREG_UDB_DSI3_HC70
400f4346 a CYREG_UDB_DSI3_HC70
400f4347 a CYREG_UDB_DSI3_HC71
400f4347 a CYREG_UDB_DSI3_HC71
400f4348 a CYREG_UDB_DSI3_HC72
400f4348 a CYREG_UDB_DSI3_HC72
400f4349 a CYREG_UDB_DSI3_HC73
400f4349 a CYREG_UDB_DSI3_HC73
400f434a a CYREG_UDB_DSI3_HC74
400f434a a CYREG_UDB_DSI3_HC74
400f434b a CYREG_UDB_DSI3_HC75
400f434b a CYREG_UDB_DSI3_HC75
400f434c a CYREG_UDB_DSI3_HC76
400f434c a CYREG_UDB_DSI3_HC76
400f434d a CYREG_UDB_DSI3_HC77
400f434d a CYREG_UDB_DSI3_HC77
400f434e a CYREG_UDB_DSI3_HC78
400f434e a CYREG_UDB_DSI3_HC78
400f434f a CYREG_UDB_DSI3_HC79
400f434f a CYREG_UDB_DSI3_HC79
400f4308 a CYREG_UDB_DSI3_HC8
400f4308 a CYREG_UDB_DSI3_HC8
400f4350 a CYREG_UDB_DSI3_HC80
400f4350 a CYREG_UDB_DSI3_HC80
400f4351 a CYREG_UDB_DSI3_HC81
400f4351 a CYREG_UDB_DSI3_HC81
400f4352 a CYREG_UDB_DSI3_HC82
400f4352 a CYREG_UDB_DSI3_HC82
400f4353 a CYREG_UDB_DSI3_HC83
400f4353 a CYREG_UDB_DSI3_HC83
400f4354 a CYREG_UDB_DSI3_HC84
400f4354 a CYREG_UDB_DSI3_HC84
400f4355 a CYREG_UDB_DSI3_HC85
400f4355 a CYREG_UDB_DSI3_HC85
400f4356 a CYREG_UDB_DSI3_HC86
400f4356 a CYREG_UDB_DSI3_HC86
400f4357 a CYREG_UDB_DSI3_HC87
400f4357 a CYREG_UDB_DSI3_HC87
400f4358 a CYREG_UDB_DSI3_HC88
400f4358 a CYREG_UDB_DSI3_HC88
400f4359 a CYREG_UDB_DSI3_HC89
400f4359 a CYREG_UDB_DSI3_HC89
400f4309 a CYREG_UDB_DSI3_HC9
400f4309 a CYREG_UDB_DSI3_HC9
400f435a a CYREG_UDB_DSI3_HC90
400f435a a CYREG_UDB_DSI3_HC90
400f435b a CYREG_UDB_DSI3_HC91
400f435b a CYREG_UDB_DSI3_HC91
400f435c a CYREG_UDB_DSI3_HC92
400f435c a CYREG_UDB_DSI3_HC92
400f435d a CYREG_UDB_DSI3_HC93
400f435d a CYREG_UDB_DSI3_HC93
400f435e a CYREG_UDB_DSI3_HC94
400f435e a CYREG_UDB_DSI3_HC94
400f435f a CYREG_UDB_DSI3_HC95
400f435f a CYREG_UDB_DSI3_HC95
400f4360 a CYREG_UDB_DSI3_HC96
400f4360 a CYREG_UDB_DSI3_HC96
400f4361 a CYREG_UDB_DSI3_HC97
400f4361 a CYREG_UDB_DSI3_HC97
400f4362 a CYREG_UDB_DSI3_HC98
400f4362 a CYREG_UDB_DSI3_HC98
400f4363 a CYREG_UDB_DSI3_HC99
400f4363 a CYREG_UDB_DSI3_HC99
400f4390 a CYREG_UDB_DSI3_HS0
400f4390 a CYREG_UDB_DSI3_HS0
400f4391 a CYREG_UDB_DSI3_HS1
400f4391 a CYREG_UDB_DSI3_HS1
400f439a a CYREG_UDB_DSI3_HS10
400f439a a CYREG_UDB_DSI3_HS10
400f439b a CYREG_UDB_DSI3_HS11
400f439b a CYREG_UDB_DSI3_HS11
400f439c a CYREG_UDB_DSI3_HS12
400f439c a CYREG_UDB_DSI3_HS12
400f439d a CYREG_UDB_DSI3_HS13
400f439d a CYREG_UDB_DSI3_HS13
400f439e a CYREG_UDB_DSI3_HS14
400f439e a CYREG_UDB_DSI3_HS14
400f439f a CYREG_UDB_DSI3_HS15
400f439f a CYREG_UDB_DSI3_HS15
400f43a0 a CYREG_UDB_DSI3_HS16
400f43a0 a CYREG_UDB_DSI3_HS16
400f43a1 a CYREG_UDB_DSI3_HS17
400f43a1 a CYREG_UDB_DSI3_HS17
400f43a2 a CYREG_UDB_DSI3_HS18
400f43a2 a CYREG_UDB_DSI3_HS18
400f43a3 a CYREG_UDB_DSI3_HS19
400f43a3 a CYREG_UDB_DSI3_HS19
400f4392 a CYREG_UDB_DSI3_HS2
400f4392 a CYREG_UDB_DSI3_HS2
400f43a4 a CYREG_UDB_DSI3_HS20
400f43a4 a CYREG_UDB_DSI3_HS20
400f43a5 a CYREG_UDB_DSI3_HS21
400f43a5 a CYREG_UDB_DSI3_HS21
400f43a6 a CYREG_UDB_DSI3_HS22
400f43a6 a CYREG_UDB_DSI3_HS22
400f43a7 a CYREG_UDB_DSI3_HS23
400f43a7 a CYREG_UDB_DSI3_HS23
400f4393 a CYREG_UDB_DSI3_HS3
400f4393 a CYREG_UDB_DSI3_HS3
400f4394 a CYREG_UDB_DSI3_HS4
400f4394 a CYREG_UDB_DSI3_HS4
400f4395 a CYREG_UDB_DSI3_HS5
400f4395 a CYREG_UDB_DSI3_HS5
400f4396 a CYREG_UDB_DSI3_HS6
400f4396 a CYREG_UDB_DSI3_HS6
400f4397 a CYREG_UDB_DSI3_HS7
400f4397 a CYREG_UDB_DSI3_HS7
400f4398 a CYREG_UDB_DSI3_HS8
400f4398 a CYREG_UDB_DSI3_HS8
400f4399 a CYREG_UDB_DSI3_HS9
400f4399 a CYREG_UDB_DSI3_HS9
400f4380 a CYREG_UDB_DSI3_HV_L0
400f4380 a CYREG_UDB_DSI3_HV_L0
400f4381 a CYREG_UDB_DSI3_HV_L1
400f4381 a CYREG_UDB_DSI3_HV_L1
400f438a a CYREG_UDB_DSI3_HV_L10
400f438a a CYREG_UDB_DSI3_HV_L10
400f438b a CYREG_UDB_DSI3_HV_L11
400f438b a CYREG_UDB_DSI3_HV_L11
400f438c a CYREG_UDB_DSI3_HV_L12
400f438c a CYREG_UDB_DSI3_HV_L12
400f438d a CYREG_UDB_DSI3_HV_L13
400f438d a CYREG_UDB_DSI3_HV_L13
400f438e a CYREG_UDB_DSI3_HV_L14
400f438e a CYREG_UDB_DSI3_HV_L14
400f438f a CYREG_UDB_DSI3_HV_L15
400f438f a CYREG_UDB_DSI3_HV_L15
400f4382 a CYREG_UDB_DSI3_HV_L2
400f4382 a CYREG_UDB_DSI3_HV_L2
400f4383 a CYREG_UDB_DSI3_HV_L3
400f4383 a CYREG_UDB_DSI3_HV_L3
400f4384 a CYREG_UDB_DSI3_HV_L4
400f4384 a CYREG_UDB_DSI3_HV_L4
400f4385 a CYREG_UDB_DSI3_HV_L5
400f4385 a CYREG_UDB_DSI3_HV_L5
400f4386 a CYREG_UDB_DSI3_HV_L6
400f4386 a CYREG_UDB_DSI3_HV_L6
400f4387 a CYREG_UDB_DSI3_HV_L7
400f4387 a CYREG_UDB_DSI3_HV_L7
400f4388 a CYREG_UDB_DSI3_HV_L8
400f4388 a CYREG_UDB_DSI3_HV_L8
400f4389 a CYREG_UDB_DSI3_HV_L9
400f4389 a CYREG_UDB_DSI3_HV_L9
400f43a8 a CYREG_UDB_DSI3_HV_R0
400f43a8 a CYREG_UDB_DSI3_HV_R0
400f43a9 a CYREG_UDB_DSI3_HV_R1
400f43a9 a CYREG_UDB_DSI3_HV_R1
400f43b2 a CYREG_UDB_DSI3_HV_R10
400f43b2 a CYREG_UDB_DSI3_HV_R10
400f43b3 a CYREG_UDB_DSI3_HV_R11
400f43b3 a CYREG_UDB_DSI3_HV_R11
400f43b4 a CYREG_UDB_DSI3_HV_R12
400f43b4 a CYREG_UDB_DSI3_HV_R12
400f43b5 a CYREG_UDB_DSI3_HV_R13
400f43b5 a CYREG_UDB_DSI3_HV_R13
400f43b6 a CYREG_UDB_DSI3_HV_R14
400f43b6 a CYREG_UDB_DSI3_HV_R14
400f43b7 a CYREG_UDB_DSI3_HV_R15
400f43b7 a CYREG_UDB_DSI3_HV_R15
400f43aa a CYREG_UDB_DSI3_HV_R2
400f43aa a CYREG_UDB_DSI3_HV_R2
400f43ab a CYREG_UDB_DSI3_HV_R3
400f43ab a CYREG_UDB_DSI3_HV_R3
400f43ac a CYREG_UDB_DSI3_HV_R4
400f43ac a CYREG_UDB_DSI3_HV_R4
400f43ad a CYREG_UDB_DSI3_HV_R5
400f43ad a CYREG_UDB_DSI3_HV_R5
400f43ae a CYREG_UDB_DSI3_HV_R6
400f43ae a CYREG_UDB_DSI3_HV_R6
400f43af a CYREG_UDB_DSI3_HV_R7
400f43af a CYREG_UDB_DSI3_HV_R7
400f43b0 a CYREG_UDB_DSI3_HV_R8
400f43b0 a CYREG_UDB_DSI3_HV_R8
400f43b1 a CYREG_UDB_DSI3_HV_R9
400f43b1 a CYREG_UDB_DSI3_HV_R9
400f43e0 a CYREG_UDB_DSI3_VS0
400f43e0 a CYREG_UDB_DSI3_VS0
400f43e2 a CYREG_UDB_DSI3_VS1
400f43e2 a CYREG_UDB_DSI3_VS1
400f43e4 a CYREG_UDB_DSI3_VS2
400f43e4 a CYREG_UDB_DSI3_VS2
400f43e6 a CYREG_UDB_DSI3_VS3
400f43e6 a CYREG_UDB_DSI3_VS3
400f43e8 a CYREG_UDB_DSI3_VS4
400f43e8 a CYREG_UDB_DSI3_VS4
400f43ea a CYREG_UDB_DSI3_VS5
400f43ea a CYREG_UDB_DSI3_VS5
400f43ec a CYREG_UDB_DSI3_VS6
400f43ec a CYREG_UDB_DSI3_VS6
400f43ee a CYREG_UDB_DSI3_VS7
400f43ee a CYREG_UDB_DSI3_VS7
400f8000 a CYREG_UDB_INT_CFG
400f8000 a CYREG_UDB_INT_CFG
400f31d0 a CYREG_UDB_P0_ROUTE_DPIN0
400f31d0 a CYREG_UDB_P0_ROUTE_DPIN0
400f31d2 a CYREG_UDB_P0_ROUTE_DPIN1
400f31d2 a CYREG_UDB_P0_ROUTE_DPIN1
400f3100 a CYREG_UDB_P0_ROUTE_HC0
400f3100 a CYREG_UDB_P0_ROUTE_HC0
400f3101 a CYREG_UDB_P0_ROUTE_HC1
400f3101 a CYREG_UDB_P0_ROUTE_HC1
400f310a a CYREG_UDB_P0_ROUTE_HC10
400f310a a CYREG_UDB_P0_ROUTE_HC10
400f3164 a CYREG_UDB_P0_ROUTE_HC100
400f3164 a CYREG_UDB_P0_ROUTE_HC100
400f3165 a CYREG_UDB_P0_ROUTE_HC101
400f3165 a CYREG_UDB_P0_ROUTE_HC101
400f3166 a CYREG_UDB_P0_ROUTE_HC102
400f3166 a CYREG_UDB_P0_ROUTE_HC102
400f3167 a CYREG_UDB_P0_ROUTE_HC103
400f3167 a CYREG_UDB_P0_ROUTE_HC103
400f3168 a CYREG_UDB_P0_ROUTE_HC104
400f3168 a CYREG_UDB_P0_ROUTE_HC104
400f3169 a CYREG_UDB_P0_ROUTE_HC105
400f3169 a CYREG_UDB_P0_ROUTE_HC105
400f316a a CYREG_UDB_P0_ROUTE_HC106
400f316a a CYREG_UDB_P0_ROUTE_HC106
400f316b a CYREG_UDB_P0_ROUTE_HC107
400f316b a CYREG_UDB_P0_ROUTE_HC107
400f316c a CYREG_UDB_P0_ROUTE_HC108
400f316c a CYREG_UDB_P0_ROUTE_HC108
400f316d a CYREG_UDB_P0_ROUTE_HC109
400f316d a CYREG_UDB_P0_ROUTE_HC109
400f310b a CYREG_UDB_P0_ROUTE_HC11
400f310b a CYREG_UDB_P0_ROUTE_HC11
400f316e a CYREG_UDB_P0_ROUTE_HC110
400f316e a CYREG_UDB_P0_ROUTE_HC110
400f316f a CYREG_UDB_P0_ROUTE_HC111
400f316f a CYREG_UDB_P0_ROUTE_HC111
400f3170 a CYREG_UDB_P0_ROUTE_HC112
400f3170 a CYREG_UDB_P0_ROUTE_HC112
400f3171 a CYREG_UDB_P0_ROUTE_HC113
400f3171 a CYREG_UDB_P0_ROUTE_HC113
400f3172 a CYREG_UDB_P0_ROUTE_HC114
400f3172 a CYREG_UDB_P0_ROUTE_HC114
400f3173 a CYREG_UDB_P0_ROUTE_HC115
400f3173 a CYREG_UDB_P0_ROUTE_HC115
400f3174 a CYREG_UDB_P0_ROUTE_HC116
400f3174 a CYREG_UDB_P0_ROUTE_HC116
400f3175 a CYREG_UDB_P0_ROUTE_HC117
400f3175 a CYREG_UDB_P0_ROUTE_HC117
400f3176 a CYREG_UDB_P0_ROUTE_HC118
400f3176 a CYREG_UDB_P0_ROUTE_HC118
400f3177 a CYREG_UDB_P0_ROUTE_HC119
400f3177 a CYREG_UDB_P0_ROUTE_HC119
400f310c a CYREG_UDB_P0_ROUTE_HC12
400f310c a CYREG_UDB_P0_ROUTE_HC12
400f3178 a CYREG_UDB_P0_ROUTE_HC120
400f3178 a CYREG_UDB_P0_ROUTE_HC120
400f3179 a CYREG_UDB_P0_ROUTE_HC121
400f3179 a CYREG_UDB_P0_ROUTE_HC121
400f317a a CYREG_UDB_P0_ROUTE_HC122
400f317a a CYREG_UDB_P0_ROUTE_HC122
400f317b a CYREG_UDB_P0_ROUTE_HC123
400f317b a CYREG_UDB_P0_ROUTE_HC123
400f317c a CYREG_UDB_P0_ROUTE_HC124
400f317c a CYREG_UDB_P0_ROUTE_HC124
400f317d a CYREG_UDB_P0_ROUTE_HC125
400f317d a CYREG_UDB_P0_ROUTE_HC125
400f317e a CYREG_UDB_P0_ROUTE_HC126
400f317e a CYREG_UDB_P0_ROUTE_HC126
400f317f a CYREG_UDB_P0_ROUTE_HC127
400f317f a CYREG_UDB_P0_ROUTE_HC127
400f310d a CYREG_UDB_P0_ROUTE_HC13
400f310d a CYREG_UDB_P0_ROUTE_HC13
400f310e a CYREG_UDB_P0_ROUTE_HC14
400f310e a CYREG_UDB_P0_ROUTE_HC14
400f310f a CYREG_UDB_P0_ROUTE_HC15
400f310f a CYREG_UDB_P0_ROUTE_HC15
400f3110 a CYREG_UDB_P0_ROUTE_HC16
400f3110 a CYREG_UDB_P0_ROUTE_HC16
400f3111 a CYREG_UDB_P0_ROUTE_HC17
400f3111 a CYREG_UDB_P0_ROUTE_HC17
400f3112 a CYREG_UDB_P0_ROUTE_HC18
400f3112 a CYREG_UDB_P0_ROUTE_HC18
400f3113 a CYREG_UDB_P0_ROUTE_HC19
400f3113 a CYREG_UDB_P0_ROUTE_HC19
400f3102 a CYREG_UDB_P0_ROUTE_HC2
400f3102 a CYREG_UDB_P0_ROUTE_HC2
400f3114 a CYREG_UDB_P0_ROUTE_HC20
400f3114 a CYREG_UDB_P0_ROUTE_HC20
400f3115 a CYREG_UDB_P0_ROUTE_HC21
400f3115 a CYREG_UDB_P0_ROUTE_HC21
400f3116 a CYREG_UDB_P0_ROUTE_HC22
400f3116 a CYREG_UDB_P0_ROUTE_HC22
400f3117 a CYREG_UDB_P0_ROUTE_HC23
400f3117 a CYREG_UDB_P0_ROUTE_HC23
400f3118 a CYREG_UDB_P0_ROUTE_HC24
400f3118 a CYREG_UDB_P0_ROUTE_HC24
400f3119 a CYREG_UDB_P0_ROUTE_HC25
400f3119 a CYREG_UDB_P0_ROUTE_HC25
400f311a a CYREG_UDB_P0_ROUTE_HC26
400f311a a CYREG_UDB_P0_ROUTE_HC26
400f311b a CYREG_UDB_P0_ROUTE_HC27
400f311b a CYREG_UDB_P0_ROUTE_HC27
400f311c a CYREG_UDB_P0_ROUTE_HC28
400f311c a CYREG_UDB_P0_ROUTE_HC28
400f311d a CYREG_UDB_P0_ROUTE_HC29
400f311d a CYREG_UDB_P0_ROUTE_HC29
400f3103 a CYREG_UDB_P0_ROUTE_HC3
400f3103 a CYREG_UDB_P0_ROUTE_HC3
400f311e a CYREG_UDB_P0_ROUTE_HC30
400f311e a CYREG_UDB_P0_ROUTE_HC30
400f311f a CYREG_UDB_P0_ROUTE_HC31
400f311f a CYREG_UDB_P0_ROUTE_HC31
400f3120 a CYREG_UDB_P0_ROUTE_HC32
400f3120 a CYREG_UDB_P0_ROUTE_HC32
400f3121 a CYREG_UDB_P0_ROUTE_HC33
400f3121 a CYREG_UDB_P0_ROUTE_HC33
400f3122 a CYREG_UDB_P0_ROUTE_HC34
400f3122 a CYREG_UDB_P0_ROUTE_HC34
400f3123 a CYREG_UDB_P0_ROUTE_HC35
400f3123 a CYREG_UDB_P0_ROUTE_HC35
400f3124 a CYREG_UDB_P0_ROUTE_HC36
400f3124 a CYREG_UDB_P0_ROUTE_HC36
400f3125 a CYREG_UDB_P0_ROUTE_HC37
400f3125 a CYREG_UDB_P0_ROUTE_HC37
400f3126 a CYREG_UDB_P0_ROUTE_HC38
400f3126 a CYREG_UDB_P0_ROUTE_HC38
400f3127 a CYREG_UDB_P0_ROUTE_HC39
400f3127 a CYREG_UDB_P0_ROUTE_HC39
400f3104 a CYREG_UDB_P0_ROUTE_HC4
400f3104 a CYREG_UDB_P0_ROUTE_HC4
400f3128 a CYREG_UDB_P0_ROUTE_HC40
400f3128 a CYREG_UDB_P0_ROUTE_HC40
400f3129 a CYREG_UDB_P0_ROUTE_HC41
400f3129 a CYREG_UDB_P0_ROUTE_HC41
400f312a a CYREG_UDB_P0_ROUTE_HC42
400f312a a CYREG_UDB_P0_ROUTE_HC42
400f312b a CYREG_UDB_P0_ROUTE_HC43
400f312b a CYREG_UDB_P0_ROUTE_HC43
400f312c a CYREG_UDB_P0_ROUTE_HC44
400f312c a CYREG_UDB_P0_ROUTE_HC44
400f312d a CYREG_UDB_P0_ROUTE_HC45
400f312d a CYREG_UDB_P0_ROUTE_HC45
400f312e a CYREG_UDB_P0_ROUTE_HC46
400f312e a CYREG_UDB_P0_ROUTE_HC46
400f312f a CYREG_UDB_P0_ROUTE_HC47
400f312f a CYREG_UDB_P0_ROUTE_HC47
400f3130 a CYREG_UDB_P0_ROUTE_HC48
400f3130 a CYREG_UDB_P0_ROUTE_HC48
400f3131 a CYREG_UDB_P0_ROUTE_HC49
400f3131 a CYREG_UDB_P0_ROUTE_HC49
400f3105 a CYREG_UDB_P0_ROUTE_HC5
400f3105 a CYREG_UDB_P0_ROUTE_HC5
400f3132 a CYREG_UDB_P0_ROUTE_HC50
400f3132 a CYREG_UDB_P0_ROUTE_HC50
400f3133 a CYREG_UDB_P0_ROUTE_HC51
400f3133 a CYREG_UDB_P0_ROUTE_HC51
400f3134 a CYREG_UDB_P0_ROUTE_HC52
400f3134 a CYREG_UDB_P0_ROUTE_HC52
400f3135 a CYREG_UDB_P0_ROUTE_HC53
400f3135 a CYREG_UDB_P0_ROUTE_HC53
400f3136 a CYREG_UDB_P0_ROUTE_HC54
400f3136 a CYREG_UDB_P0_ROUTE_HC54
400f3137 a CYREG_UDB_P0_ROUTE_HC55
400f3137 a CYREG_UDB_P0_ROUTE_HC55
400f3138 a CYREG_UDB_P0_ROUTE_HC56
400f3138 a CYREG_UDB_P0_ROUTE_HC56
400f3139 a CYREG_UDB_P0_ROUTE_HC57
400f3139 a CYREG_UDB_P0_ROUTE_HC57
400f313a a CYREG_UDB_P0_ROUTE_HC58
400f313a a CYREG_UDB_P0_ROUTE_HC58
400f313b a CYREG_UDB_P0_ROUTE_HC59
400f313b a CYREG_UDB_P0_ROUTE_HC59
400f3106 a CYREG_UDB_P0_ROUTE_HC6
400f3106 a CYREG_UDB_P0_ROUTE_HC6
400f313c a CYREG_UDB_P0_ROUTE_HC60
400f313c a CYREG_UDB_P0_ROUTE_HC60
400f313d a CYREG_UDB_P0_ROUTE_HC61
400f313d a CYREG_UDB_P0_ROUTE_HC61
400f313e a CYREG_UDB_P0_ROUTE_HC62
400f313e a CYREG_UDB_P0_ROUTE_HC62
400f313f a CYREG_UDB_P0_ROUTE_HC63
400f313f a CYREG_UDB_P0_ROUTE_HC63
400f3140 a CYREG_UDB_P0_ROUTE_HC64
400f3140 a CYREG_UDB_P0_ROUTE_HC64
400f3141 a CYREG_UDB_P0_ROUTE_HC65
400f3141 a CYREG_UDB_P0_ROUTE_HC65
400f3142 a CYREG_UDB_P0_ROUTE_HC66
400f3142 a CYREG_UDB_P0_ROUTE_HC66
400f3143 a CYREG_UDB_P0_ROUTE_HC67
400f3143 a CYREG_UDB_P0_ROUTE_HC67
400f3144 a CYREG_UDB_P0_ROUTE_HC68
400f3144 a CYREG_UDB_P0_ROUTE_HC68
400f3145 a CYREG_UDB_P0_ROUTE_HC69
400f3145 a CYREG_UDB_P0_ROUTE_HC69
400f3107 a CYREG_UDB_P0_ROUTE_HC7
400f3107 a CYREG_UDB_P0_ROUTE_HC7
400f3146 a CYREG_UDB_P0_ROUTE_HC70
400f3146 a CYREG_UDB_P0_ROUTE_HC70
400f3147 a CYREG_UDB_P0_ROUTE_HC71
400f3147 a CYREG_UDB_P0_ROUTE_HC71
400f3148 a CYREG_UDB_P0_ROUTE_HC72
400f3148 a CYREG_UDB_P0_ROUTE_HC72
400f3149 a CYREG_UDB_P0_ROUTE_HC73
400f3149 a CYREG_UDB_P0_ROUTE_HC73
400f314a a CYREG_UDB_P0_ROUTE_HC74
400f314a a CYREG_UDB_P0_ROUTE_HC74
400f314b a CYREG_UDB_P0_ROUTE_HC75
400f314b a CYREG_UDB_P0_ROUTE_HC75
400f314c a CYREG_UDB_P0_ROUTE_HC76
400f314c a CYREG_UDB_P0_ROUTE_HC76
400f314d a CYREG_UDB_P0_ROUTE_HC77
400f314d a CYREG_UDB_P0_ROUTE_HC77
400f314e a CYREG_UDB_P0_ROUTE_HC78
400f314e a CYREG_UDB_P0_ROUTE_HC78
400f314f a CYREG_UDB_P0_ROUTE_HC79
400f314f a CYREG_UDB_P0_ROUTE_HC79
400f3108 a CYREG_UDB_P0_ROUTE_HC8
400f3108 a CYREG_UDB_P0_ROUTE_HC8
400f3150 a CYREG_UDB_P0_ROUTE_HC80
400f3150 a CYREG_UDB_P0_ROUTE_HC80
400f3151 a CYREG_UDB_P0_ROUTE_HC81
400f3151 a CYREG_UDB_P0_ROUTE_HC81
400f3152 a CYREG_UDB_P0_ROUTE_HC82
400f3152 a CYREG_UDB_P0_ROUTE_HC82
400f3153 a CYREG_UDB_P0_ROUTE_HC83
400f3153 a CYREG_UDB_P0_ROUTE_HC83
400f3154 a CYREG_UDB_P0_ROUTE_HC84
400f3154 a CYREG_UDB_P0_ROUTE_HC84
400f3155 a CYREG_UDB_P0_ROUTE_HC85
400f3155 a CYREG_UDB_P0_ROUTE_HC85
400f3156 a CYREG_UDB_P0_ROUTE_HC86
400f3156 a CYREG_UDB_P0_ROUTE_HC86
400f3157 a CYREG_UDB_P0_ROUTE_HC87
400f3157 a CYREG_UDB_P0_ROUTE_HC87
400f3158 a CYREG_UDB_P0_ROUTE_HC88
400f3158 a CYREG_UDB_P0_ROUTE_HC88
400f3159 a CYREG_UDB_P0_ROUTE_HC89
400f3159 a CYREG_UDB_P0_ROUTE_HC89
400f3109 a CYREG_UDB_P0_ROUTE_HC9
400f3109 a CYREG_UDB_P0_ROUTE_HC9
400f315a a CYREG_UDB_P0_ROUTE_HC90
400f315a a CYREG_UDB_P0_ROUTE_HC90
400f315b a CYREG_UDB_P0_ROUTE_HC91
400f315b a CYREG_UDB_P0_ROUTE_HC91
400f315c a CYREG_UDB_P0_ROUTE_HC92
400f315c a CYREG_UDB_P0_ROUTE_HC92
400f315d a CYREG_UDB_P0_ROUTE_HC93
400f315d a CYREG_UDB_P0_ROUTE_HC93
400f315e a CYREG_UDB_P0_ROUTE_HC94
400f315e a CYREG_UDB_P0_ROUTE_HC94
400f315f a CYREG_UDB_P0_ROUTE_HC95
400f315f a CYREG_UDB_P0_ROUTE_HC95
400f3160 a CYREG_UDB_P0_ROUTE_HC96
400f3160 a CYREG_UDB_P0_ROUTE_HC96
400f3161 a CYREG_UDB_P0_ROUTE_HC97
400f3161 a CYREG_UDB_P0_ROUTE_HC97
400f3162 a CYREG_UDB_P0_ROUTE_HC98
400f3162 a CYREG_UDB_P0_ROUTE_HC98
400f3163 a CYREG_UDB_P0_ROUTE_HC99
400f3163 a CYREG_UDB_P0_ROUTE_HC99
400f3190 a CYREG_UDB_P0_ROUTE_HS0
400f3190 a CYREG_UDB_P0_ROUTE_HS0
400f3191 a CYREG_UDB_P0_ROUTE_HS1
400f3191 a CYREG_UDB_P0_ROUTE_HS1
400f319a a CYREG_UDB_P0_ROUTE_HS10
400f319a a CYREG_UDB_P0_ROUTE_HS10
400f319b a CYREG_UDB_P0_ROUTE_HS11
400f319b a CYREG_UDB_P0_ROUTE_HS11
400f319c a CYREG_UDB_P0_ROUTE_HS12
400f319c a CYREG_UDB_P0_ROUTE_HS12
400f319d a CYREG_UDB_P0_ROUTE_HS13
400f319d a CYREG_UDB_P0_ROUTE_HS13
400f319e a CYREG_UDB_P0_ROUTE_HS14
400f319e a CYREG_UDB_P0_ROUTE_HS14
400f319f a CYREG_UDB_P0_ROUTE_HS15
400f319f a CYREG_UDB_P0_ROUTE_HS15
400f31a0 a CYREG_UDB_P0_ROUTE_HS16
400f31a0 a CYREG_UDB_P0_ROUTE_HS16
400f31a1 a CYREG_UDB_P0_ROUTE_HS17
400f31a1 a CYREG_UDB_P0_ROUTE_HS17
400f31a2 a CYREG_UDB_P0_ROUTE_HS18
400f31a2 a CYREG_UDB_P0_ROUTE_HS18
400f31a3 a CYREG_UDB_P0_ROUTE_HS19
400f31a3 a CYREG_UDB_P0_ROUTE_HS19
400f3192 a CYREG_UDB_P0_ROUTE_HS2
400f3192 a CYREG_UDB_P0_ROUTE_HS2
400f31a4 a CYREG_UDB_P0_ROUTE_HS20
400f31a4 a CYREG_UDB_P0_ROUTE_HS20
400f31a5 a CYREG_UDB_P0_ROUTE_HS21
400f31a5 a CYREG_UDB_P0_ROUTE_HS21
400f31a6 a CYREG_UDB_P0_ROUTE_HS22
400f31a6 a CYREG_UDB_P0_ROUTE_HS22
400f31a7 a CYREG_UDB_P0_ROUTE_HS23
400f31a7 a CYREG_UDB_P0_ROUTE_HS23
400f3193 a CYREG_UDB_P0_ROUTE_HS3
400f3193 a CYREG_UDB_P0_ROUTE_HS3
400f3194 a CYREG_UDB_P0_ROUTE_HS4
400f3194 a CYREG_UDB_P0_ROUTE_HS4
400f3195 a CYREG_UDB_P0_ROUTE_HS5
400f3195 a CYREG_UDB_P0_ROUTE_HS5
400f3196 a CYREG_UDB_P0_ROUTE_HS6
400f3196 a CYREG_UDB_P0_ROUTE_HS6
400f3197 a CYREG_UDB_P0_ROUTE_HS7
400f3197 a CYREG_UDB_P0_ROUTE_HS7
400f3198 a CYREG_UDB_P0_ROUTE_HS8
400f3198 a CYREG_UDB_P0_ROUTE_HS8
400f3199 a CYREG_UDB_P0_ROUTE_HS9
400f3199 a CYREG_UDB_P0_ROUTE_HS9
400f3180 a CYREG_UDB_P0_ROUTE_HV_L0
400f3180 a CYREG_UDB_P0_ROUTE_HV_L0
400f3181 a CYREG_UDB_P0_ROUTE_HV_L1
400f3181 a CYREG_UDB_P0_ROUTE_HV_L1
400f318a a CYREG_UDB_P0_ROUTE_HV_L10
400f318a a CYREG_UDB_P0_ROUTE_HV_L10
400f318b a CYREG_UDB_P0_ROUTE_HV_L11
400f318b a CYREG_UDB_P0_ROUTE_HV_L11
400f318c a CYREG_UDB_P0_ROUTE_HV_L12
400f318c a CYREG_UDB_P0_ROUTE_HV_L12
400f318d a CYREG_UDB_P0_ROUTE_HV_L13
400f318d a CYREG_UDB_P0_ROUTE_HV_L13
400f318e a CYREG_UDB_P0_ROUTE_HV_L14
400f318e a CYREG_UDB_P0_ROUTE_HV_L14
400f318f a CYREG_UDB_P0_ROUTE_HV_L15
400f318f a CYREG_UDB_P0_ROUTE_HV_L15
400f3182 a CYREG_UDB_P0_ROUTE_HV_L2
400f3182 a CYREG_UDB_P0_ROUTE_HV_L2
400f3183 a CYREG_UDB_P0_ROUTE_HV_L3
400f3183 a CYREG_UDB_P0_ROUTE_HV_L3
400f3184 a CYREG_UDB_P0_ROUTE_HV_L4
400f3184 a CYREG_UDB_P0_ROUTE_HV_L4
400f3185 a CYREG_UDB_P0_ROUTE_HV_L5
400f3185 a CYREG_UDB_P0_ROUTE_HV_L5
400f3186 a CYREG_UDB_P0_ROUTE_HV_L6
400f3186 a CYREG_UDB_P0_ROUTE_HV_L6
400f3187 a CYREG_UDB_P0_ROUTE_HV_L7
400f3187 a CYREG_UDB_P0_ROUTE_HV_L7
400f3188 a CYREG_UDB_P0_ROUTE_HV_L8
400f3188 a CYREG_UDB_P0_ROUTE_HV_L8
400f3189 a CYREG_UDB_P0_ROUTE_HV_L9
400f3189 a CYREG_UDB_P0_ROUTE_HV_L9
400f31a8 a CYREG_UDB_P0_ROUTE_HV_R0
400f31a8 a CYREG_UDB_P0_ROUTE_HV_R0
400f31a9 a CYREG_UDB_P0_ROUTE_HV_R1
400f31a9 a CYREG_UDB_P0_ROUTE_HV_R1
400f31b2 a CYREG_UDB_P0_ROUTE_HV_R10
400f31b2 a CYREG_UDB_P0_ROUTE_HV_R10
400f31b3 a CYREG_UDB_P0_ROUTE_HV_R11
400f31b3 a CYREG_UDB_P0_ROUTE_HV_R11
400f31b4 a CYREG_UDB_P0_ROUTE_HV_R12
400f31b4 a CYREG_UDB_P0_ROUTE_HV_R12
400f31b5 a CYREG_UDB_P0_ROUTE_HV_R13
400f31b5 a CYREG_UDB_P0_ROUTE_HV_R13
400f31b6 a CYREG_UDB_P0_ROUTE_HV_R14
400f31b6 a CYREG_UDB_P0_ROUTE_HV_R14
400f31b7 a CYREG_UDB_P0_ROUTE_HV_R15
400f31b7 a CYREG_UDB_P0_ROUTE_HV_R15
400f31aa a CYREG_UDB_P0_ROUTE_HV_R2
400f31aa a CYREG_UDB_P0_ROUTE_HV_R2
400f31ab a CYREG_UDB_P0_ROUTE_HV_R3
400f31ab a CYREG_UDB_P0_ROUTE_HV_R3
400f31ac a CYREG_UDB_P0_ROUTE_HV_R4
400f31ac a CYREG_UDB_P0_ROUTE_HV_R4
400f31ad a CYREG_UDB_P0_ROUTE_HV_R5
400f31ad a CYREG_UDB_P0_ROUTE_HV_R5
400f31ae a CYREG_UDB_P0_ROUTE_HV_R6
400f31ae a CYREG_UDB_P0_ROUTE_HV_R6
400f31af a CYREG_UDB_P0_ROUTE_HV_R7
400f31af a CYREG_UDB_P0_ROUTE_HV_R7
400f31b0 a CYREG_UDB_P0_ROUTE_HV_R8
400f31b0 a CYREG_UDB_P0_ROUTE_HV_R8
400f31b1 a CYREG_UDB_P0_ROUTE_HV_R9
400f31b1 a CYREG_UDB_P0_ROUTE_HV_R9
400f31c0 a CYREG_UDB_P0_ROUTE_PLD0IN0
400f31c0 a CYREG_UDB_P0_ROUTE_PLD0IN0
400f31c2 a CYREG_UDB_P0_ROUTE_PLD0IN1
400f31c2 a CYREG_UDB_P0_ROUTE_PLD0IN1
400f31c4 a CYREG_UDB_P0_ROUTE_PLD0IN2
400f31c4 a CYREG_UDB_P0_ROUTE_PLD0IN2
400f31ca a CYREG_UDB_P0_ROUTE_PLD1IN0
400f31ca a CYREG_UDB_P0_ROUTE_PLD1IN0
400f31cc a CYREG_UDB_P0_ROUTE_PLD1IN1
400f31cc a CYREG_UDB_P0_ROUTE_PLD1IN1
400f31ce a CYREG_UDB_P0_ROUTE_PLD1IN2
400f31ce a CYREG_UDB_P0_ROUTE_PLD1IN2
400f31de a CYREG_UDB_P0_ROUTE_RCIN
400f31de a CYREG_UDB_P0_ROUTE_RCIN
400f31d6 a CYREG_UDB_P0_ROUTE_SCIN
400f31d6 a CYREG_UDB_P0_ROUTE_SCIN
400f31d8 a CYREG_UDB_P0_ROUTE_SCIOIN
400f31d8 a CYREG_UDB_P0_ROUTE_SCIOIN
400f31e0 a CYREG_UDB_P0_ROUTE_VS0
400f31e0 a CYREG_UDB_P0_ROUTE_VS0
400f31e2 a CYREG_UDB_P0_ROUTE_VS1
400f31e2 a CYREG_UDB_P0_ROUTE_VS1
400f31e4 a CYREG_UDB_P0_ROUTE_VS2
400f31e4 a CYREG_UDB_P0_ROUTE_VS2
400f31e6 a CYREG_UDB_P0_ROUTE_VS3
400f31e6 a CYREG_UDB_P0_ROUTE_VS3
400f31e8 a CYREG_UDB_P0_ROUTE_VS4
400f31e8 a CYREG_UDB_P0_ROUTE_VS4
400f31ea a CYREG_UDB_P0_ROUTE_VS5
400f31ea a CYREG_UDB_P0_ROUTE_VS5
400f31ec a CYREG_UDB_P0_ROUTE_VS6
400f31ec a CYREG_UDB_P0_ROUTE_VS6
400f31ee a CYREG_UDB_P0_ROUTE_VS7
400f31ee a CYREG_UDB_P0_ROUTE_VS7
400f3040 a CYREG_UDB_P0_U0_CFG0
400f3040 a CYREG_UDB_P0_U0_CFG0
400f3041 a CYREG_UDB_P0_U0_CFG1
400f3041 a CYREG_UDB_P0_U0_CFG1
400f304a a CYREG_UDB_P0_U0_CFG10
400f304a a CYREG_UDB_P0_U0_CFG10
400f304b a CYREG_UDB_P0_U0_CFG11
400f304b a CYREG_UDB_P0_U0_CFG11
400f304c a CYREG_UDB_P0_U0_CFG12
400f304c a CYREG_UDB_P0_U0_CFG12
400f304d a CYREG_UDB_P0_U0_CFG13
400f304d a CYREG_UDB_P0_U0_CFG13
400f304e a CYREG_UDB_P0_U0_CFG14
400f304e a CYREG_UDB_P0_U0_CFG14
400f304f a CYREG_UDB_P0_U0_CFG15
400f304f a CYREG_UDB_P0_U0_CFG15
400f3050 a CYREG_UDB_P0_U0_CFG16
400f3050 a CYREG_UDB_P0_U0_CFG16
400f3051 a CYREG_UDB_P0_U0_CFG17
400f3051 a CYREG_UDB_P0_U0_CFG17
400f3052 a CYREG_UDB_P0_U0_CFG18
400f3052 a CYREG_UDB_P0_U0_CFG18
400f3053 a CYREG_UDB_P0_U0_CFG19
400f3053 a CYREG_UDB_P0_U0_CFG19
400f3042 a CYREG_UDB_P0_U0_CFG2
400f3042 a CYREG_UDB_P0_U0_CFG2
400f3054 a CYREG_UDB_P0_U0_CFG20
400f3054 a CYREG_UDB_P0_U0_CFG20
400f3055 a CYREG_UDB_P0_U0_CFG21
400f3055 a CYREG_UDB_P0_U0_CFG21
400f3056 a CYREG_UDB_P0_U0_CFG22
400f3056 a CYREG_UDB_P0_U0_CFG22
400f3057 a CYREG_UDB_P0_U0_CFG23
400f3057 a CYREG_UDB_P0_U0_CFG23
400f3058 a CYREG_UDB_P0_U0_CFG24
400f3058 a CYREG_UDB_P0_U0_CFG24
400f3059 a CYREG_UDB_P0_U0_CFG25
400f3059 a CYREG_UDB_P0_U0_CFG25
400f305a a CYREG_UDB_P0_U0_CFG26
400f305a a CYREG_UDB_P0_U0_CFG26
400f305b a CYREG_UDB_P0_U0_CFG27
400f305b a CYREG_UDB_P0_U0_CFG27
400f305c a CYREG_UDB_P0_U0_CFG28
400f305c a CYREG_UDB_P0_U0_CFG28
400f305d a CYREG_UDB_P0_U0_CFG29
400f305d a CYREG_UDB_P0_U0_CFG29
400f3043 a CYREG_UDB_P0_U0_CFG3
400f3043 a CYREG_UDB_P0_U0_CFG3
400f305e a CYREG_UDB_P0_U0_CFG30
400f305e a CYREG_UDB_P0_U0_CFG30
400f305f a CYREG_UDB_P0_U0_CFG31
400f305f a CYREG_UDB_P0_U0_CFG31
400f3044 a CYREG_UDB_P0_U0_CFG4
400f3044 a CYREG_UDB_P0_U0_CFG4
400f3045 a CYREG_UDB_P0_U0_CFG5
400f3045 a CYREG_UDB_P0_U0_CFG5
400f3046 a CYREG_UDB_P0_U0_CFG6
400f3046 a CYREG_UDB_P0_U0_CFG6
400f3047 a CYREG_UDB_P0_U0_CFG7
400f3047 a CYREG_UDB_P0_U0_CFG7
400f3048 a CYREG_UDB_P0_U0_CFG8
400f3048 a CYREG_UDB_P0_U0_CFG8
400f3049 a CYREG_UDB_P0_U0_CFG9
400f3049 a CYREG_UDB_P0_U0_CFG9
400f3060 a CYREG_UDB_P0_U0_DCFG0
400f3060 a CYREG_UDB_P0_U0_DCFG0
400f3062 a CYREG_UDB_P0_U0_DCFG1
400f3062 a CYREG_UDB_P0_U0_DCFG1
400f3064 a CYREG_UDB_P0_U0_DCFG2
400f3064 a CYREG_UDB_P0_U0_DCFG2
400f3066 a CYREG_UDB_P0_U0_DCFG3
400f3066 a CYREG_UDB_P0_U0_DCFG3
400f3068 a CYREG_UDB_P0_U0_DCFG4
400f3068 a CYREG_UDB_P0_U0_DCFG4
400f306a a CYREG_UDB_P0_U0_DCFG5
400f306a a CYREG_UDB_P0_U0_DCFG5
400f306c a CYREG_UDB_P0_U0_DCFG6
400f306c a CYREG_UDB_P0_U0_DCFG6
400f306e a CYREG_UDB_P0_U0_DCFG7
400f306e a CYREG_UDB_P0_U0_DCFG7
400f3000 a CYREG_UDB_P0_U0_PLD_IT0
400f3000 a CYREG_UDB_P0_U0_PLD_IT0
400f3004 a CYREG_UDB_P0_U0_PLD_IT1
400f3004 a CYREG_UDB_P0_U0_PLD_IT1
400f3028 a CYREG_UDB_P0_U0_PLD_IT10
400f3028 a CYREG_UDB_P0_U0_PLD_IT10
400f302c a CYREG_UDB_P0_U0_PLD_IT11
400f302c a CYREG_UDB_P0_U0_PLD_IT11
400f3008 a CYREG_UDB_P0_U0_PLD_IT2
400f3008 a CYREG_UDB_P0_U0_PLD_IT2
400f300c a CYREG_UDB_P0_U0_PLD_IT3
400f300c a CYREG_UDB_P0_U0_PLD_IT3
400f3010 a CYREG_UDB_P0_U0_PLD_IT4
400f3010 a CYREG_UDB_P0_U0_PLD_IT4
400f3014 a CYREG_UDB_P0_U0_PLD_IT5
400f3014 a CYREG_UDB_P0_U0_PLD_IT5
400f3018 a CYREG_UDB_P0_U0_PLD_IT6
400f3018 a CYREG_UDB_P0_U0_PLD_IT6
400f301c a CYREG_UDB_P0_U0_PLD_IT7
400f301c a CYREG_UDB_P0_U0_PLD_IT7
400f3020 a CYREG_UDB_P0_U0_PLD_IT8
400f3020 a CYREG_UDB_P0_U0_PLD_IT8
400f3024 a CYREG_UDB_P0_U0_PLD_IT9
400f3024 a CYREG_UDB_P0_U0_PLD_IT9
400f303e a CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS
400f303e a CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS
400f3038 a CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST
400f3038 a CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST
400f303a a CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB
400f303a a CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB
400f303c a CYREG_UDB_P0_U0_PLD_MC_SET_RESET
400f303c a CYREG_UDB_P0_U0_PLD_MC_SET_RESET
400f3030 a CYREG_UDB_P0_U0_PLD_ORT0
400f3030 a CYREG_UDB_P0_U0_PLD_ORT0
400f3032 a CYREG_UDB_P0_U0_PLD_ORT1
400f3032 a CYREG_UDB_P0_U0_PLD_ORT1
400f3034 a CYREG_UDB_P0_U0_PLD_ORT2
400f3034 a CYREG_UDB_P0_U0_PLD_ORT2
400f3036 a CYREG_UDB_P0_U0_PLD_ORT3
400f3036 a CYREG_UDB_P0_U0_PLD_ORT3
400f30c0 a CYREG_UDB_P0_U1_CFG0
400f30c0 a CYREG_UDB_P0_U1_CFG0
400f30c1 a CYREG_UDB_P0_U1_CFG1
400f30c1 a CYREG_UDB_P0_U1_CFG1
400f30ca a CYREG_UDB_P0_U1_CFG10
400f30ca a CYREG_UDB_P0_U1_CFG10
400f30cb a CYREG_UDB_P0_U1_CFG11
400f30cb a CYREG_UDB_P0_U1_CFG11
400f30cc a CYREG_UDB_P0_U1_CFG12
400f30cc a CYREG_UDB_P0_U1_CFG12
400f30cd a CYREG_UDB_P0_U1_CFG13
400f30cd a CYREG_UDB_P0_U1_CFG13
400f30ce a CYREG_UDB_P0_U1_CFG14
400f30ce a CYREG_UDB_P0_U1_CFG14
400f30cf a CYREG_UDB_P0_U1_CFG15
400f30cf a CYREG_UDB_P0_U1_CFG15
400f30d0 a CYREG_UDB_P0_U1_CFG16
400f30d0 a CYREG_UDB_P0_U1_CFG16
400f30d1 a CYREG_UDB_P0_U1_CFG17
400f30d1 a CYREG_UDB_P0_U1_CFG17
400f30d2 a CYREG_UDB_P0_U1_CFG18
400f30d2 a CYREG_UDB_P0_U1_CFG18
400f30d3 a CYREG_UDB_P0_U1_CFG19
400f30d3 a CYREG_UDB_P0_U1_CFG19
400f30c2 a CYREG_UDB_P0_U1_CFG2
400f30c2 a CYREG_UDB_P0_U1_CFG2
400f30d4 a CYREG_UDB_P0_U1_CFG20
400f30d4 a CYREG_UDB_P0_U1_CFG20
400f30d5 a CYREG_UDB_P0_U1_CFG21
400f30d5 a CYREG_UDB_P0_U1_CFG21
400f30d6 a CYREG_UDB_P0_U1_CFG22
400f30d6 a CYREG_UDB_P0_U1_CFG22
400f30d7 a CYREG_UDB_P0_U1_CFG23
400f30d7 a CYREG_UDB_P0_U1_CFG23
400f30d8 a CYREG_UDB_P0_U1_CFG24
400f30d8 a CYREG_UDB_P0_U1_CFG24
400f30d9 a CYREG_UDB_P0_U1_CFG25
400f30d9 a CYREG_UDB_P0_U1_CFG25
400f30da a CYREG_UDB_P0_U1_CFG26
400f30da a CYREG_UDB_P0_U1_CFG26
400f30db a CYREG_UDB_P0_U1_CFG27
400f30db a CYREG_UDB_P0_U1_CFG27
400f30dc a CYREG_UDB_P0_U1_CFG28
400f30dc a CYREG_UDB_P0_U1_CFG28
400f30dd a CYREG_UDB_P0_U1_CFG29
400f30dd a CYREG_UDB_P0_U1_CFG29
400f30c3 a CYREG_UDB_P0_U1_CFG3
400f30c3 a CYREG_UDB_P0_U1_CFG3
400f30de a CYREG_UDB_P0_U1_CFG30
400f30de a CYREG_UDB_P0_U1_CFG30
400f30df a CYREG_UDB_P0_U1_CFG31
400f30df a CYREG_UDB_P0_U1_CFG31
400f30c4 a CYREG_UDB_P0_U1_CFG4
400f30c4 a CYREG_UDB_P0_U1_CFG4
400f30c5 a CYREG_UDB_P0_U1_CFG5
400f30c5 a CYREG_UDB_P0_U1_CFG5
400f30c6 a CYREG_UDB_P0_U1_CFG6
400f30c6 a CYREG_UDB_P0_U1_CFG6
400f30c7 a CYREG_UDB_P0_U1_CFG7
400f30c7 a CYREG_UDB_P0_U1_CFG7
400f30c8 a CYREG_UDB_P0_U1_CFG8
400f30c8 a CYREG_UDB_P0_U1_CFG8
400f30c9 a CYREG_UDB_P0_U1_CFG9
400f30c9 a CYREG_UDB_P0_U1_CFG9
400f30e0 a CYREG_UDB_P0_U1_DCFG0
400f30e0 a CYREG_UDB_P0_U1_DCFG0
400f30e2 a CYREG_UDB_P0_U1_DCFG1
400f30e2 a CYREG_UDB_P0_U1_DCFG1
400f30e4 a CYREG_UDB_P0_U1_DCFG2
400f30e4 a CYREG_UDB_P0_U1_DCFG2
400f30e6 a CYREG_UDB_P0_U1_DCFG3
400f30e6 a CYREG_UDB_P0_U1_DCFG3
400f30e8 a CYREG_UDB_P0_U1_DCFG4
400f30e8 a CYREG_UDB_P0_U1_DCFG4
400f30ea a CYREG_UDB_P0_U1_DCFG5
400f30ea a CYREG_UDB_P0_U1_DCFG5
400f30ec a CYREG_UDB_P0_U1_DCFG6
400f30ec a CYREG_UDB_P0_U1_DCFG6
400f30ee a CYREG_UDB_P0_U1_DCFG7
400f30ee a CYREG_UDB_P0_U1_DCFG7
400f3080 a CYREG_UDB_P0_U1_PLD_IT0
400f3080 a CYREG_UDB_P0_U1_PLD_IT0
400f3084 a CYREG_UDB_P0_U1_PLD_IT1
400f3084 a CYREG_UDB_P0_U1_PLD_IT1
400f30a8 a CYREG_UDB_P0_U1_PLD_IT10
400f30a8 a CYREG_UDB_P0_U1_PLD_IT10
400f30ac a CYREG_UDB_P0_U1_PLD_IT11
400f30ac a CYREG_UDB_P0_U1_PLD_IT11
400f3088 a CYREG_UDB_P0_U1_PLD_IT2
400f3088 a CYREG_UDB_P0_U1_PLD_IT2
400f308c a CYREG_UDB_P0_U1_PLD_IT3
400f308c a CYREG_UDB_P0_U1_PLD_IT3
400f3090 a CYREG_UDB_P0_U1_PLD_IT4
400f3090 a CYREG_UDB_P0_U1_PLD_IT4
400f3094 a CYREG_UDB_P0_U1_PLD_IT5
400f3094 a CYREG_UDB_P0_U1_PLD_IT5
400f3098 a CYREG_UDB_P0_U1_PLD_IT6
400f3098 a CYREG_UDB_P0_U1_PLD_IT6
400f309c a CYREG_UDB_P0_U1_PLD_IT7
400f309c a CYREG_UDB_P0_U1_PLD_IT7
400f30a0 a CYREG_UDB_P0_U1_PLD_IT8
400f30a0 a CYREG_UDB_P0_U1_PLD_IT8
400f30a4 a CYREG_UDB_P0_U1_PLD_IT9
400f30a4 a CYREG_UDB_P0_U1_PLD_IT9
400f30be a CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS
400f30be a CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS
400f30b8 a CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST
400f30b8 a CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST
400f30ba a CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB
400f30ba a CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB
400f30bc a CYREG_UDB_P0_U1_PLD_MC_SET_RESET
400f30bc a CYREG_UDB_P0_U1_PLD_MC_SET_RESET
400f30b0 a CYREG_UDB_P0_U1_PLD_ORT0
400f30b0 a CYREG_UDB_P0_U1_PLD_ORT0
400f30b2 a CYREG_UDB_P0_U1_PLD_ORT1
400f30b2 a CYREG_UDB_P0_U1_PLD_ORT1
400f30b4 a CYREG_UDB_P0_U1_PLD_ORT2
400f30b4 a CYREG_UDB_P0_U1_PLD_ORT2
400f30b6 a CYREG_UDB_P0_U1_PLD_ORT3
400f30b6 a CYREG_UDB_P0_U1_PLD_ORT3
400f33d0 a CYREG_UDB_P1_ROUTE_DPIN0
400f33d0 a CYREG_UDB_P1_ROUTE_DPIN0
400f33d2 a CYREG_UDB_P1_ROUTE_DPIN1
400f33d2 a CYREG_UDB_P1_ROUTE_DPIN1
400f3300 a CYREG_UDB_P1_ROUTE_HC0
400f3300 a CYREG_UDB_P1_ROUTE_HC0
400f3301 a CYREG_UDB_P1_ROUTE_HC1
400f3301 a CYREG_UDB_P1_ROUTE_HC1
400f330a a CYREG_UDB_P1_ROUTE_HC10
400f330a a CYREG_UDB_P1_ROUTE_HC10
400f3364 a CYREG_UDB_P1_ROUTE_HC100
400f3364 a CYREG_UDB_P1_ROUTE_HC100
400f3365 a CYREG_UDB_P1_ROUTE_HC101
400f3365 a CYREG_UDB_P1_ROUTE_HC101
400f3366 a CYREG_UDB_P1_ROUTE_HC102
400f3366 a CYREG_UDB_P1_ROUTE_HC102
400f3367 a CYREG_UDB_P1_ROUTE_HC103
400f3367 a CYREG_UDB_P1_ROUTE_HC103
400f3368 a CYREG_UDB_P1_ROUTE_HC104
400f3368 a CYREG_UDB_P1_ROUTE_HC104
400f3369 a CYREG_UDB_P1_ROUTE_HC105
400f3369 a CYREG_UDB_P1_ROUTE_HC105
400f336a a CYREG_UDB_P1_ROUTE_HC106
400f336a a CYREG_UDB_P1_ROUTE_HC106
400f336b a CYREG_UDB_P1_ROUTE_HC107
400f336b a CYREG_UDB_P1_ROUTE_HC107
400f336c a CYREG_UDB_P1_ROUTE_HC108
400f336c a CYREG_UDB_P1_ROUTE_HC108
400f336d a CYREG_UDB_P1_ROUTE_HC109
400f336d a CYREG_UDB_P1_ROUTE_HC109
400f330b a CYREG_UDB_P1_ROUTE_HC11
400f330b a CYREG_UDB_P1_ROUTE_HC11
400f336e a CYREG_UDB_P1_ROUTE_HC110
400f336e a CYREG_UDB_P1_ROUTE_HC110
400f336f a CYREG_UDB_P1_ROUTE_HC111
400f336f a CYREG_UDB_P1_ROUTE_HC111
400f3370 a CYREG_UDB_P1_ROUTE_HC112
400f3370 a CYREG_UDB_P1_ROUTE_HC112
400f3371 a CYREG_UDB_P1_ROUTE_HC113
400f3371 a CYREG_UDB_P1_ROUTE_HC113
400f3372 a CYREG_UDB_P1_ROUTE_HC114
400f3372 a CYREG_UDB_P1_ROUTE_HC114
400f3373 a CYREG_UDB_P1_ROUTE_HC115
400f3373 a CYREG_UDB_P1_ROUTE_HC115
400f3374 a CYREG_UDB_P1_ROUTE_HC116
400f3374 a CYREG_UDB_P1_ROUTE_HC116
400f3375 a CYREG_UDB_P1_ROUTE_HC117
400f3375 a CYREG_UDB_P1_ROUTE_HC117
400f3376 a CYREG_UDB_P1_ROUTE_HC118
400f3376 a CYREG_UDB_P1_ROUTE_HC118
400f3377 a CYREG_UDB_P1_ROUTE_HC119
400f3377 a CYREG_UDB_P1_ROUTE_HC119
400f330c a CYREG_UDB_P1_ROUTE_HC12
400f330c a CYREG_UDB_P1_ROUTE_HC12
400f3378 a CYREG_UDB_P1_ROUTE_HC120
400f3378 a CYREG_UDB_P1_ROUTE_HC120
400f3379 a CYREG_UDB_P1_ROUTE_HC121
400f3379 a CYREG_UDB_P1_ROUTE_HC121
400f337a a CYREG_UDB_P1_ROUTE_HC122
400f337a a CYREG_UDB_P1_ROUTE_HC122
400f337b a CYREG_UDB_P1_ROUTE_HC123
400f337b a CYREG_UDB_P1_ROUTE_HC123
400f337c a CYREG_UDB_P1_ROUTE_HC124
400f337c a CYREG_UDB_P1_ROUTE_HC124
400f337d a CYREG_UDB_P1_ROUTE_HC125
400f337d a CYREG_UDB_P1_ROUTE_HC125
400f337e a CYREG_UDB_P1_ROUTE_HC126
400f337e a CYREG_UDB_P1_ROUTE_HC126
400f337f a CYREG_UDB_P1_ROUTE_HC127
400f337f a CYREG_UDB_P1_ROUTE_HC127
400f330d a CYREG_UDB_P1_ROUTE_HC13
400f330d a CYREG_UDB_P1_ROUTE_HC13
400f330e a CYREG_UDB_P1_ROUTE_HC14
400f330e a CYREG_UDB_P1_ROUTE_HC14
400f330f a CYREG_UDB_P1_ROUTE_HC15
400f330f a CYREG_UDB_P1_ROUTE_HC15
400f3310 a CYREG_UDB_P1_ROUTE_HC16
400f3310 a CYREG_UDB_P1_ROUTE_HC16
400f3311 a CYREG_UDB_P1_ROUTE_HC17
400f3311 a CYREG_UDB_P1_ROUTE_HC17
400f3312 a CYREG_UDB_P1_ROUTE_HC18
400f3312 a CYREG_UDB_P1_ROUTE_HC18
400f3313 a CYREG_UDB_P1_ROUTE_HC19
400f3313 a CYREG_UDB_P1_ROUTE_HC19
400f3302 a CYREG_UDB_P1_ROUTE_HC2
400f3302 a CYREG_UDB_P1_ROUTE_HC2
400f3314 a CYREG_UDB_P1_ROUTE_HC20
400f3314 a CYREG_UDB_P1_ROUTE_HC20
400f3315 a CYREG_UDB_P1_ROUTE_HC21
400f3315 a CYREG_UDB_P1_ROUTE_HC21
400f3316 a CYREG_UDB_P1_ROUTE_HC22
400f3316 a CYREG_UDB_P1_ROUTE_HC22
400f3317 a CYREG_UDB_P1_ROUTE_HC23
400f3317 a CYREG_UDB_P1_ROUTE_HC23
400f3318 a CYREG_UDB_P1_ROUTE_HC24
400f3318 a CYREG_UDB_P1_ROUTE_HC24
400f3319 a CYREG_UDB_P1_ROUTE_HC25
400f3319 a CYREG_UDB_P1_ROUTE_HC25
400f331a a CYREG_UDB_P1_ROUTE_HC26
400f331a a CYREG_UDB_P1_ROUTE_HC26
400f331b a CYREG_UDB_P1_ROUTE_HC27
400f331b a CYREG_UDB_P1_ROUTE_HC27
400f331c a CYREG_UDB_P1_ROUTE_HC28
400f331c a CYREG_UDB_P1_ROUTE_HC28
400f331d a CYREG_UDB_P1_ROUTE_HC29
400f331d a CYREG_UDB_P1_ROUTE_HC29
400f3303 a CYREG_UDB_P1_ROUTE_HC3
400f3303 a CYREG_UDB_P1_ROUTE_HC3
400f331e a CYREG_UDB_P1_ROUTE_HC30
400f331e a CYREG_UDB_P1_ROUTE_HC30
400f331f a CYREG_UDB_P1_ROUTE_HC31
400f331f a CYREG_UDB_P1_ROUTE_HC31
400f3320 a CYREG_UDB_P1_ROUTE_HC32
400f3320 a CYREG_UDB_P1_ROUTE_HC32
400f3321 a CYREG_UDB_P1_ROUTE_HC33
400f3321 a CYREG_UDB_P1_ROUTE_HC33
400f3322 a CYREG_UDB_P1_ROUTE_HC34
400f3322 a CYREG_UDB_P1_ROUTE_HC34
400f3323 a CYREG_UDB_P1_ROUTE_HC35
400f3323 a CYREG_UDB_P1_ROUTE_HC35
400f3324 a CYREG_UDB_P1_ROUTE_HC36
400f3324 a CYREG_UDB_P1_ROUTE_HC36
400f3325 a CYREG_UDB_P1_ROUTE_HC37
400f3325 a CYREG_UDB_P1_ROUTE_HC37
400f3326 a CYREG_UDB_P1_ROUTE_HC38
400f3326 a CYREG_UDB_P1_ROUTE_HC38
400f3327 a CYREG_UDB_P1_ROUTE_HC39
400f3327 a CYREG_UDB_P1_ROUTE_HC39
400f3304 a CYREG_UDB_P1_ROUTE_HC4
400f3304 a CYREG_UDB_P1_ROUTE_HC4
400f3328 a CYREG_UDB_P1_ROUTE_HC40
400f3328 a CYREG_UDB_P1_ROUTE_HC40
400f3329 a CYREG_UDB_P1_ROUTE_HC41
400f3329 a CYREG_UDB_P1_ROUTE_HC41
400f332a a CYREG_UDB_P1_ROUTE_HC42
400f332a a CYREG_UDB_P1_ROUTE_HC42
400f332b a CYREG_UDB_P1_ROUTE_HC43
400f332b a CYREG_UDB_P1_ROUTE_HC43
400f332c a CYREG_UDB_P1_ROUTE_HC44
400f332c a CYREG_UDB_P1_ROUTE_HC44
400f332d a CYREG_UDB_P1_ROUTE_HC45
400f332d a CYREG_UDB_P1_ROUTE_HC45
400f332e a CYREG_UDB_P1_ROUTE_HC46
400f332e a CYREG_UDB_P1_ROUTE_HC46
400f332f a CYREG_UDB_P1_ROUTE_HC47
400f332f a CYREG_UDB_P1_ROUTE_HC47
400f3330 a CYREG_UDB_P1_ROUTE_HC48
400f3330 a CYREG_UDB_P1_ROUTE_HC48
400f3331 a CYREG_UDB_P1_ROUTE_HC49
400f3331 a CYREG_UDB_P1_ROUTE_HC49
400f3305 a CYREG_UDB_P1_ROUTE_HC5
400f3305 a CYREG_UDB_P1_ROUTE_HC5
400f3332 a CYREG_UDB_P1_ROUTE_HC50
400f3332 a CYREG_UDB_P1_ROUTE_HC50
400f3333 a CYREG_UDB_P1_ROUTE_HC51
400f3333 a CYREG_UDB_P1_ROUTE_HC51
400f3334 a CYREG_UDB_P1_ROUTE_HC52
400f3334 a CYREG_UDB_P1_ROUTE_HC52
400f3335 a CYREG_UDB_P1_ROUTE_HC53
400f3335 a CYREG_UDB_P1_ROUTE_HC53
400f3336 a CYREG_UDB_P1_ROUTE_HC54
400f3336 a CYREG_UDB_P1_ROUTE_HC54
400f3337 a CYREG_UDB_P1_ROUTE_HC55
400f3337 a CYREG_UDB_P1_ROUTE_HC55
400f3338 a CYREG_UDB_P1_ROUTE_HC56
400f3338 a CYREG_UDB_P1_ROUTE_HC56
400f3339 a CYREG_UDB_P1_ROUTE_HC57
400f3339 a CYREG_UDB_P1_ROUTE_HC57
400f333a a CYREG_UDB_P1_ROUTE_HC58
400f333a a CYREG_UDB_P1_ROUTE_HC58
400f333b a CYREG_UDB_P1_ROUTE_HC59
400f333b a CYREG_UDB_P1_ROUTE_HC59
400f3306 a CYREG_UDB_P1_ROUTE_HC6
400f3306 a CYREG_UDB_P1_ROUTE_HC6
400f333c a CYREG_UDB_P1_ROUTE_HC60
400f333c a CYREG_UDB_P1_ROUTE_HC60
400f333d a CYREG_UDB_P1_ROUTE_HC61
400f333d a CYREG_UDB_P1_ROUTE_HC61
400f333e a CYREG_UDB_P1_ROUTE_HC62
400f333e a CYREG_UDB_P1_ROUTE_HC62
400f333f a CYREG_UDB_P1_ROUTE_HC63
400f333f a CYREG_UDB_P1_ROUTE_HC63
400f3340 a CYREG_UDB_P1_ROUTE_HC64
400f3340 a CYREG_UDB_P1_ROUTE_HC64
400f3341 a CYREG_UDB_P1_ROUTE_HC65
400f3341 a CYREG_UDB_P1_ROUTE_HC65
400f3342 a CYREG_UDB_P1_ROUTE_HC66
400f3342 a CYREG_UDB_P1_ROUTE_HC66
400f3343 a CYREG_UDB_P1_ROUTE_HC67
400f3343 a CYREG_UDB_P1_ROUTE_HC67
400f3344 a CYREG_UDB_P1_ROUTE_HC68
400f3344 a CYREG_UDB_P1_ROUTE_HC68
400f3345 a CYREG_UDB_P1_ROUTE_HC69
400f3345 a CYREG_UDB_P1_ROUTE_HC69
400f3307 a CYREG_UDB_P1_ROUTE_HC7
400f3307 a CYREG_UDB_P1_ROUTE_HC7
400f3346 a CYREG_UDB_P1_ROUTE_HC70
400f3346 a CYREG_UDB_P1_ROUTE_HC70
400f3347 a CYREG_UDB_P1_ROUTE_HC71
400f3347 a CYREG_UDB_P1_ROUTE_HC71
400f3348 a CYREG_UDB_P1_ROUTE_HC72
400f3348 a CYREG_UDB_P1_ROUTE_HC72
400f3349 a CYREG_UDB_P1_ROUTE_HC73
400f3349 a CYREG_UDB_P1_ROUTE_HC73
400f334a a CYREG_UDB_P1_ROUTE_HC74
400f334a a CYREG_UDB_P1_ROUTE_HC74
400f334b a CYREG_UDB_P1_ROUTE_HC75
400f334b a CYREG_UDB_P1_ROUTE_HC75
400f334c a CYREG_UDB_P1_ROUTE_HC76
400f334c a CYREG_UDB_P1_ROUTE_HC76
400f334d a CYREG_UDB_P1_ROUTE_HC77
400f334d a CYREG_UDB_P1_ROUTE_HC77
400f334e a CYREG_UDB_P1_ROUTE_HC78
400f334e a CYREG_UDB_P1_ROUTE_HC78
400f334f a CYREG_UDB_P1_ROUTE_HC79
400f334f a CYREG_UDB_P1_ROUTE_HC79
400f3308 a CYREG_UDB_P1_ROUTE_HC8
400f3308 a CYREG_UDB_P1_ROUTE_HC8
400f3350 a CYREG_UDB_P1_ROUTE_HC80
400f3350 a CYREG_UDB_P1_ROUTE_HC80
400f3351 a CYREG_UDB_P1_ROUTE_HC81
400f3351 a CYREG_UDB_P1_ROUTE_HC81
400f3352 a CYREG_UDB_P1_ROUTE_HC82
400f3352 a CYREG_UDB_P1_ROUTE_HC82
400f3353 a CYREG_UDB_P1_ROUTE_HC83
400f3353 a CYREG_UDB_P1_ROUTE_HC83
400f3354 a CYREG_UDB_P1_ROUTE_HC84
400f3354 a CYREG_UDB_P1_ROUTE_HC84
400f3355 a CYREG_UDB_P1_ROUTE_HC85
400f3355 a CYREG_UDB_P1_ROUTE_HC85
400f3356 a CYREG_UDB_P1_ROUTE_HC86
400f3356 a CYREG_UDB_P1_ROUTE_HC86
400f3357 a CYREG_UDB_P1_ROUTE_HC87
400f3357 a CYREG_UDB_P1_ROUTE_HC87
400f3358 a CYREG_UDB_P1_ROUTE_HC88
400f3358 a CYREG_UDB_P1_ROUTE_HC88
400f3359 a CYREG_UDB_P1_ROUTE_HC89
400f3359 a CYREG_UDB_P1_ROUTE_HC89
400f3309 a CYREG_UDB_P1_ROUTE_HC9
400f3309 a CYREG_UDB_P1_ROUTE_HC9
400f335a a CYREG_UDB_P1_ROUTE_HC90
400f335a a CYREG_UDB_P1_ROUTE_HC90
400f335b a CYREG_UDB_P1_ROUTE_HC91
400f335b a CYREG_UDB_P1_ROUTE_HC91
400f335c a CYREG_UDB_P1_ROUTE_HC92
400f335c a CYREG_UDB_P1_ROUTE_HC92
400f335d a CYREG_UDB_P1_ROUTE_HC93
400f335d a CYREG_UDB_P1_ROUTE_HC93
400f335e a CYREG_UDB_P1_ROUTE_HC94
400f335e a CYREG_UDB_P1_ROUTE_HC94
400f335f a CYREG_UDB_P1_ROUTE_HC95
400f335f a CYREG_UDB_P1_ROUTE_HC95
400f3360 a CYREG_UDB_P1_ROUTE_HC96
400f3360 a CYREG_UDB_P1_ROUTE_HC96
400f3361 a CYREG_UDB_P1_ROUTE_HC97
400f3361 a CYREG_UDB_P1_ROUTE_HC97
400f3362 a CYREG_UDB_P1_ROUTE_HC98
400f3362 a CYREG_UDB_P1_ROUTE_HC98
400f3363 a CYREG_UDB_P1_ROUTE_HC99
400f3363 a CYREG_UDB_P1_ROUTE_HC99
400f3390 a CYREG_UDB_P1_ROUTE_HS0
400f3390 a CYREG_UDB_P1_ROUTE_HS0
400f3391 a CYREG_UDB_P1_ROUTE_HS1
400f3391 a CYREG_UDB_P1_ROUTE_HS1
400f339a a CYREG_UDB_P1_ROUTE_HS10
400f339a a CYREG_UDB_P1_ROUTE_HS10
400f339b a CYREG_UDB_P1_ROUTE_HS11
400f339b a CYREG_UDB_P1_ROUTE_HS11
400f339c a CYREG_UDB_P1_ROUTE_HS12
400f339c a CYREG_UDB_P1_ROUTE_HS12
400f339d a CYREG_UDB_P1_ROUTE_HS13
400f339d a CYREG_UDB_P1_ROUTE_HS13
400f339e a CYREG_UDB_P1_ROUTE_HS14
400f339e a CYREG_UDB_P1_ROUTE_HS14
400f339f a CYREG_UDB_P1_ROUTE_HS15
400f339f a CYREG_UDB_P1_ROUTE_HS15
400f33a0 a CYREG_UDB_P1_ROUTE_HS16
400f33a0 a CYREG_UDB_P1_ROUTE_HS16
400f33a1 a CYREG_UDB_P1_ROUTE_HS17
400f33a1 a CYREG_UDB_P1_ROUTE_HS17
400f33a2 a CYREG_UDB_P1_ROUTE_HS18
400f33a2 a CYREG_UDB_P1_ROUTE_HS18
400f33a3 a CYREG_UDB_P1_ROUTE_HS19
400f33a3 a CYREG_UDB_P1_ROUTE_HS19
400f3392 a CYREG_UDB_P1_ROUTE_HS2
400f3392 a CYREG_UDB_P1_ROUTE_HS2
400f33a4 a CYREG_UDB_P1_ROUTE_HS20
400f33a4 a CYREG_UDB_P1_ROUTE_HS20
400f33a5 a CYREG_UDB_P1_ROUTE_HS21
400f33a5 a CYREG_UDB_P1_ROUTE_HS21
400f33a6 a CYREG_UDB_P1_ROUTE_HS22
400f33a6 a CYREG_UDB_P1_ROUTE_HS22
400f33a7 a CYREG_UDB_P1_ROUTE_HS23
400f33a7 a CYREG_UDB_P1_ROUTE_HS23
400f3393 a CYREG_UDB_P1_ROUTE_HS3
400f3393 a CYREG_UDB_P1_ROUTE_HS3
400f3394 a CYREG_UDB_P1_ROUTE_HS4
400f3394 a CYREG_UDB_P1_ROUTE_HS4
400f3395 a CYREG_UDB_P1_ROUTE_HS5
400f3395 a CYREG_UDB_P1_ROUTE_HS5
400f3396 a CYREG_UDB_P1_ROUTE_HS6
400f3396 a CYREG_UDB_P1_ROUTE_HS6
400f3397 a CYREG_UDB_P1_ROUTE_HS7
400f3397 a CYREG_UDB_P1_ROUTE_HS7
400f3398 a CYREG_UDB_P1_ROUTE_HS8
400f3398 a CYREG_UDB_P1_ROUTE_HS8
400f3399 a CYREG_UDB_P1_ROUTE_HS9
400f3399 a CYREG_UDB_P1_ROUTE_HS9
400f3380 a CYREG_UDB_P1_ROUTE_HV_L0
400f3380 a CYREG_UDB_P1_ROUTE_HV_L0
400f3381 a CYREG_UDB_P1_ROUTE_HV_L1
400f3381 a CYREG_UDB_P1_ROUTE_HV_L1
400f338a a CYREG_UDB_P1_ROUTE_HV_L10
400f338a a CYREG_UDB_P1_ROUTE_HV_L10
400f338b a CYREG_UDB_P1_ROUTE_HV_L11
400f338b a CYREG_UDB_P1_ROUTE_HV_L11
400f338c a CYREG_UDB_P1_ROUTE_HV_L12
400f338c a CYREG_UDB_P1_ROUTE_HV_L12
400f338d a CYREG_UDB_P1_ROUTE_HV_L13
400f338d a CYREG_UDB_P1_ROUTE_HV_L13
400f338e a CYREG_UDB_P1_ROUTE_HV_L14
400f338e a CYREG_UDB_P1_ROUTE_HV_L14
400f338f a CYREG_UDB_P1_ROUTE_HV_L15
400f338f a CYREG_UDB_P1_ROUTE_HV_L15
400f3382 a CYREG_UDB_P1_ROUTE_HV_L2
400f3382 a CYREG_UDB_P1_ROUTE_HV_L2
400f3383 a CYREG_UDB_P1_ROUTE_HV_L3
400f3383 a CYREG_UDB_P1_ROUTE_HV_L3
400f3384 a CYREG_UDB_P1_ROUTE_HV_L4
400f3384 a CYREG_UDB_P1_ROUTE_HV_L4
400f3385 a CYREG_UDB_P1_ROUTE_HV_L5
400f3385 a CYREG_UDB_P1_ROUTE_HV_L5
400f3386 a CYREG_UDB_P1_ROUTE_HV_L6
400f3386 a CYREG_UDB_P1_ROUTE_HV_L6
400f3387 a CYREG_UDB_P1_ROUTE_HV_L7
400f3387 a CYREG_UDB_P1_ROUTE_HV_L7
400f3388 a CYREG_UDB_P1_ROUTE_HV_L8
400f3388 a CYREG_UDB_P1_ROUTE_HV_L8
400f3389 a CYREG_UDB_P1_ROUTE_HV_L9
400f3389 a CYREG_UDB_P1_ROUTE_HV_L9
400f33a8 a CYREG_UDB_P1_ROUTE_HV_R0
400f33a8 a CYREG_UDB_P1_ROUTE_HV_R0
400f33a9 a CYREG_UDB_P1_ROUTE_HV_R1
400f33a9 a CYREG_UDB_P1_ROUTE_HV_R1
400f33b2 a CYREG_UDB_P1_ROUTE_HV_R10
400f33b2 a CYREG_UDB_P1_ROUTE_HV_R10
400f33b3 a CYREG_UDB_P1_ROUTE_HV_R11
400f33b3 a CYREG_UDB_P1_ROUTE_HV_R11
400f33b4 a CYREG_UDB_P1_ROUTE_HV_R12
400f33b4 a CYREG_UDB_P1_ROUTE_HV_R12
400f33b5 a CYREG_UDB_P1_ROUTE_HV_R13
400f33b5 a CYREG_UDB_P1_ROUTE_HV_R13
400f33b6 a CYREG_UDB_P1_ROUTE_HV_R14
400f33b6 a CYREG_UDB_P1_ROUTE_HV_R14
400f33b7 a CYREG_UDB_P1_ROUTE_HV_R15
400f33b7 a CYREG_UDB_P1_ROUTE_HV_R15
400f33aa a CYREG_UDB_P1_ROUTE_HV_R2
400f33aa a CYREG_UDB_P1_ROUTE_HV_R2
400f33ab a CYREG_UDB_P1_ROUTE_HV_R3
400f33ab a CYREG_UDB_P1_ROUTE_HV_R3
400f33ac a CYREG_UDB_P1_ROUTE_HV_R4
400f33ac a CYREG_UDB_P1_ROUTE_HV_R4
400f33ad a CYREG_UDB_P1_ROUTE_HV_R5
400f33ad a CYREG_UDB_P1_ROUTE_HV_R5
400f33ae a CYREG_UDB_P1_ROUTE_HV_R6
400f33ae a CYREG_UDB_P1_ROUTE_HV_R6
400f33af a CYREG_UDB_P1_ROUTE_HV_R7
400f33af a CYREG_UDB_P1_ROUTE_HV_R7
400f33b0 a CYREG_UDB_P1_ROUTE_HV_R8
400f33b0 a CYREG_UDB_P1_ROUTE_HV_R8
400f33b1 a CYREG_UDB_P1_ROUTE_HV_R9
400f33b1 a CYREG_UDB_P1_ROUTE_HV_R9
400f33c0 a CYREG_UDB_P1_ROUTE_PLD0IN0
400f33c0 a CYREG_UDB_P1_ROUTE_PLD0IN0
400f33c2 a CYREG_UDB_P1_ROUTE_PLD0IN1
400f33c2 a CYREG_UDB_P1_ROUTE_PLD0IN1
400f33c4 a CYREG_UDB_P1_ROUTE_PLD0IN2
400f33c4 a CYREG_UDB_P1_ROUTE_PLD0IN2
400f33ca a CYREG_UDB_P1_ROUTE_PLD1IN0
400f33ca a CYREG_UDB_P1_ROUTE_PLD1IN0
400f33cc a CYREG_UDB_P1_ROUTE_PLD1IN1
400f33cc a CYREG_UDB_P1_ROUTE_PLD1IN1
400f33ce a CYREG_UDB_P1_ROUTE_PLD1IN2
400f33ce a CYREG_UDB_P1_ROUTE_PLD1IN2
400f33de a CYREG_UDB_P1_ROUTE_RCIN
400f33de a CYREG_UDB_P1_ROUTE_RCIN
400f33d6 a CYREG_UDB_P1_ROUTE_SCIN
400f33d6 a CYREG_UDB_P1_ROUTE_SCIN
400f33d8 a CYREG_UDB_P1_ROUTE_SCIOIN
400f33d8 a CYREG_UDB_P1_ROUTE_SCIOIN
400f33e0 a CYREG_UDB_P1_ROUTE_VS0
400f33e0 a CYREG_UDB_P1_ROUTE_VS0
400f33e2 a CYREG_UDB_P1_ROUTE_VS1
400f33e2 a CYREG_UDB_P1_ROUTE_VS1
400f33e4 a CYREG_UDB_P1_ROUTE_VS2
400f33e4 a CYREG_UDB_P1_ROUTE_VS2
400f33e6 a CYREG_UDB_P1_ROUTE_VS3
400f33e6 a CYREG_UDB_P1_ROUTE_VS3
400f33e8 a CYREG_UDB_P1_ROUTE_VS4
400f33e8 a CYREG_UDB_P1_ROUTE_VS4
400f33ea a CYREG_UDB_P1_ROUTE_VS5
400f33ea a CYREG_UDB_P1_ROUTE_VS5
400f33ec a CYREG_UDB_P1_ROUTE_VS6
400f33ec a CYREG_UDB_P1_ROUTE_VS6
400f33ee a CYREG_UDB_P1_ROUTE_VS7
400f33ee a CYREG_UDB_P1_ROUTE_VS7
400f3240 a CYREG_UDB_P1_U0_CFG0
400f3240 a CYREG_UDB_P1_U0_CFG0
400f3241 a CYREG_UDB_P1_U0_CFG1
400f3241 a CYREG_UDB_P1_U0_CFG1
400f324a a CYREG_UDB_P1_U0_CFG10
400f324a a CYREG_UDB_P1_U0_CFG10
400f324b a CYREG_UDB_P1_U0_CFG11
400f324b a CYREG_UDB_P1_U0_CFG11
400f324c a CYREG_UDB_P1_U0_CFG12
400f324c a CYREG_UDB_P1_U0_CFG12
400f324d a CYREG_UDB_P1_U0_CFG13
400f324d a CYREG_UDB_P1_U0_CFG13
400f324e a CYREG_UDB_P1_U0_CFG14
400f324e a CYREG_UDB_P1_U0_CFG14
400f324f a CYREG_UDB_P1_U0_CFG15
400f324f a CYREG_UDB_P1_U0_CFG15
400f3250 a CYREG_UDB_P1_U0_CFG16
400f3250 a CYREG_UDB_P1_U0_CFG16
400f3251 a CYREG_UDB_P1_U0_CFG17
400f3251 a CYREG_UDB_P1_U0_CFG17
400f3252 a CYREG_UDB_P1_U0_CFG18
400f3252 a CYREG_UDB_P1_U0_CFG18
400f3253 a CYREG_UDB_P1_U0_CFG19
400f3253 a CYREG_UDB_P1_U0_CFG19
400f3242 a CYREG_UDB_P1_U0_CFG2
400f3242 a CYREG_UDB_P1_U0_CFG2
400f3254 a CYREG_UDB_P1_U0_CFG20
400f3254 a CYREG_UDB_P1_U0_CFG20
400f3255 a CYREG_UDB_P1_U0_CFG21
400f3255 a CYREG_UDB_P1_U0_CFG21
400f3256 a CYREG_UDB_P1_U0_CFG22
400f3256 a CYREG_UDB_P1_U0_CFG22
400f3257 a CYREG_UDB_P1_U0_CFG23
400f3257 a CYREG_UDB_P1_U0_CFG23
400f3258 a CYREG_UDB_P1_U0_CFG24
400f3258 a CYREG_UDB_P1_U0_CFG24
400f3259 a CYREG_UDB_P1_U0_CFG25
400f3259 a CYREG_UDB_P1_U0_CFG25
400f325a a CYREG_UDB_P1_U0_CFG26
400f325a a CYREG_UDB_P1_U0_CFG26
400f325b a CYREG_UDB_P1_U0_CFG27
400f325b a CYREG_UDB_P1_U0_CFG27
400f325c a CYREG_UDB_P1_U0_CFG28
400f325c a CYREG_UDB_P1_U0_CFG28
400f325d a CYREG_UDB_P1_U0_CFG29
400f325d a CYREG_UDB_P1_U0_CFG29
400f3243 a CYREG_UDB_P1_U0_CFG3
400f3243 a CYREG_UDB_P1_U0_CFG3
400f325e a CYREG_UDB_P1_U0_CFG30
400f325e a CYREG_UDB_P1_U0_CFG30
400f325f a CYREG_UDB_P1_U0_CFG31
400f325f a CYREG_UDB_P1_U0_CFG31
400f3244 a CYREG_UDB_P1_U0_CFG4
400f3244 a CYREG_UDB_P1_U0_CFG4
400f3245 a CYREG_UDB_P1_U0_CFG5
400f3245 a CYREG_UDB_P1_U0_CFG5
400f3246 a CYREG_UDB_P1_U0_CFG6
400f3246 a CYREG_UDB_P1_U0_CFG6
400f3247 a CYREG_UDB_P1_U0_CFG7
400f3247 a CYREG_UDB_P1_U0_CFG7
400f3248 a CYREG_UDB_P1_U0_CFG8
400f3248 a CYREG_UDB_P1_U0_CFG8
400f3249 a CYREG_UDB_P1_U0_CFG9
400f3249 a CYREG_UDB_P1_U0_CFG9
400f3260 a CYREG_UDB_P1_U0_DCFG0
400f3260 a CYREG_UDB_P1_U0_DCFG0
400f3262 a CYREG_UDB_P1_U0_DCFG1
400f3262 a CYREG_UDB_P1_U0_DCFG1
400f3264 a CYREG_UDB_P1_U0_DCFG2
400f3264 a CYREG_UDB_P1_U0_DCFG2
400f3266 a CYREG_UDB_P1_U0_DCFG3
400f3266 a CYREG_UDB_P1_U0_DCFG3
400f3268 a CYREG_UDB_P1_U0_DCFG4
400f3268 a CYREG_UDB_P1_U0_DCFG4
400f326a a CYREG_UDB_P1_U0_DCFG5
400f326a a CYREG_UDB_P1_U0_DCFG5
400f326c a CYREG_UDB_P1_U0_DCFG6
400f326c a CYREG_UDB_P1_U0_DCFG6
400f326e a CYREG_UDB_P1_U0_DCFG7
400f326e a CYREG_UDB_P1_U0_DCFG7
400f3200 a CYREG_UDB_P1_U0_PLD_IT0
400f3200 a CYREG_UDB_P1_U0_PLD_IT0
400f3204 a CYREG_UDB_P1_U0_PLD_IT1
400f3204 a CYREG_UDB_P1_U0_PLD_IT1
400f3228 a CYREG_UDB_P1_U0_PLD_IT10
400f3228 a CYREG_UDB_P1_U0_PLD_IT10
400f322c a CYREG_UDB_P1_U0_PLD_IT11
400f322c a CYREG_UDB_P1_U0_PLD_IT11
400f3208 a CYREG_UDB_P1_U0_PLD_IT2
400f3208 a CYREG_UDB_P1_U0_PLD_IT2
400f320c a CYREG_UDB_P1_U0_PLD_IT3
400f320c a CYREG_UDB_P1_U0_PLD_IT3
400f3210 a CYREG_UDB_P1_U0_PLD_IT4
400f3210 a CYREG_UDB_P1_U0_PLD_IT4
400f3214 a CYREG_UDB_P1_U0_PLD_IT5
400f3214 a CYREG_UDB_P1_U0_PLD_IT5
400f3218 a CYREG_UDB_P1_U0_PLD_IT6
400f3218 a CYREG_UDB_P1_U0_PLD_IT6
400f321c a CYREG_UDB_P1_U0_PLD_IT7
400f321c a CYREG_UDB_P1_U0_PLD_IT7
400f3220 a CYREG_UDB_P1_U0_PLD_IT8
400f3220 a CYREG_UDB_P1_U0_PLD_IT8
400f3224 a CYREG_UDB_P1_U0_PLD_IT9
400f3224 a CYREG_UDB_P1_U0_PLD_IT9
400f323e a CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS
400f323e a CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS
400f3238 a CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST
400f3238 a CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST
400f323a a CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB
400f323a a CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB
400f323c a CYREG_UDB_P1_U0_PLD_MC_SET_RESET
400f323c a CYREG_UDB_P1_U0_PLD_MC_SET_RESET
400f3230 a CYREG_UDB_P1_U0_PLD_ORT0
400f3230 a CYREG_UDB_P1_U0_PLD_ORT0
400f3232 a CYREG_UDB_P1_U0_PLD_ORT1
400f3232 a CYREG_UDB_P1_U0_PLD_ORT1
400f3234 a CYREG_UDB_P1_U0_PLD_ORT2
400f3234 a CYREG_UDB_P1_U0_PLD_ORT2
400f3236 a CYREG_UDB_P1_U0_PLD_ORT3
400f3236 a CYREG_UDB_P1_U0_PLD_ORT3
400f32c0 a CYREG_UDB_P1_U1_CFG0
400f32c0 a CYREG_UDB_P1_U1_CFG0
400f32c1 a CYREG_UDB_P1_U1_CFG1
400f32c1 a CYREG_UDB_P1_U1_CFG1
400f32ca a CYREG_UDB_P1_U1_CFG10
400f32ca a CYREG_UDB_P1_U1_CFG10
400f32cb a CYREG_UDB_P1_U1_CFG11
400f32cb a CYREG_UDB_P1_U1_CFG11
400f32cc a CYREG_UDB_P1_U1_CFG12
400f32cc a CYREG_UDB_P1_U1_CFG12
400f32cd a CYREG_UDB_P1_U1_CFG13
400f32cd a CYREG_UDB_P1_U1_CFG13
400f32ce a CYREG_UDB_P1_U1_CFG14
400f32ce a CYREG_UDB_P1_U1_CFG14
400f32cf a CYREG_UDB_P1_U1_CFG15
400f32cf a CYREG_UDB_P1_U1_CFG15
400f32d0 a CYREG_UDB_P1_U1_CFG16
400f32d0 a CYREG_UDB_P1_U1_CFG16
400f32d1 a CYREG_UDB_P1_U1_CFG17
400f32d1 a CYREG_UDB_P1_U1_CFG17
400f32d2 a CYREG_UDB_P1_U1_CFG18
400f32d2 a CYREG_UDB_P1_U1_CFG18
400f32d3 a CYREG_UDB_P1_U1_CFG19
400f32d3 a CYREG_UDB_P1_U1_CFG19
400f32c2 a CYREG_UDB_P1_U1_CFG2
400f32c2 a CYREG_UDB_P1_U1_CFG2
400f32d4 a CYREG_UDB_P1_U1_CFG20
400f32d4 a CYREG_UDB_P1_U1_CFG20
400f32d5 a CYREG_UDB_P1_U1_CFG21
400f32d5 a CYREG_UDB_P1_U1_CFG21
400f32d6 a CYREG_UDB_P1_U1_CFG22
400f32d6 a CYREG_UDB_P1_U1_CFG22
400f32d7 a CYREG_UDB_P1_U1_CFG23
400f32d7 a CYREG_UDB_P1_U1_CFG23
400f32d8 a CYREG_UDB_P1_U1_CFG24
400f32d8 a CYREG_UDB_P1_U1_CFG24
400f32d9 a CYREG_UDB_P1_U1_CFG25
400f32d9 a CYREG_UDB_P1_U1_CFG25
400f32da a CYREG_UDB_P1_U1_CFG26
400f32da a CYREG_UDB_P1_U1_CFG26
400f32db a CYREG_UDB_P1_U1_CFG27
400f32db a CYREG_UDB_P1_U1_CFG27
400f32dc a CYREG_UDB_P1_U1_CFG28
400f32dc a CYREG_UDB_P1_U1_CFG28
400f32dd a CYREG_UDB_P1_U1_CFG29
400f32dd a CYREG_UDB_P1_U1_CFG29
400f32c3 a CYREG_UDB_P1_U1_CFG3
400f32c3 a CYREG_UDB_P1_U1_CFG3
400f32de a CYREG_UDB_P1_U1_CFG30
400f32de a CYREG_UDB_P1_U1_CFG30
400f32df a CYREG_UDB_P1_U1_CFG31
400f32df a CYREG_UDB_P1_U1_CFG31
400f32c4 a CYREG_UDB_P1_U1_CFG4
400f32c4 a CYREG_UDB_P1_U1_CFG4
400f32c5 a CYREG_UDB_P1_U1_CFG5
400f32c5 a CYREG_UDB_P1_U1_CFG5
400f32c6 a CYREG_UDB_P1_U1_CFG6
400f32c6 a CYREG_UDB_P1_U1_CFG6
400f32c7 a CYREG_UDB_P1_U1_CFG7
400f32c7 a CYREG_UDB_P1_U1_CFG7
400f32c8 a CYREG_UDB_P1_U1_CFG8
400f32c8 a CYREG_UDB_P1_U1_CFG8
400f32c9 a CYREG_UDB_P1_U1_CFG9
400f32c9 a CYREG_UDB_P1_U1_CFG9
400f32e0 a CYREG_UDB_P1_U1_DCFG0
400f32e0 a CYREG_UDB_P1_U1_DCFG0
400f32e2 a CYREG_UDB_P1_U1_DCFG1
400f32e2 a CYREG_UDB_P1_U1_DCFG1
400f32e4 a CYREG_UDB_P1_U1_DCFG2
400f32e4 a CYREG_UDB_P1_U1_DCFG2
400f32e6 a CYREG_UDB_P1_U1_DCFG3
400f32e6 a CYREG_UDB_P1_U1_DCFG3
400f32e8 a CYREG_UDB_P1_U1_DCFG4
400f32e8 a CYREG_UDB_P1_U1_DCFG4
400f32ea a CYREG_UDB_P1_U1_DCFG5
400f32ea a CYREG_UDB_P1_U1_DCFG5
400f32ec a CYREG_UDB_P1_U1_DCFG6
400f32ec a CYREG_UDB_P1_U1_DCFG6
400f32ee a CYREG_UDB_P1_U1_DCFG7
400f32ee a CYREG_UDB_P1_U1_DCFG7
400f3280 a CYREG_UDB_P1_U1_PLD_IT0
400f3280 a CYREG_UDB_P1_U1_PLD_IT0
400f3284 a CYREG_UDB_P1_U1_PLD_IT1
400f3284 a CYREG_UDB_P1_U1_PLD_IT1
400f32a8 a CYREG_UDB_P1_U1_PLD_IT10
400f32a8 a CYREG_UDB_P1_U1_PLD_IT10
400f32ac a CYREG_UDB_P1_U1_PLD_IT11
400f32ac a CYREG_UDB_P1_U1_PLD_IT11
400f3288 a CYREG_UDB_P1_U1_PLD_IT2
400f3288 a CYREG_UDB_P1_U1_PLD_IT2
400f328c a CYREG_UDB_P1_U1_PLD_IT3
400f328c a CYREG_UDB_P1_U1_PLD_IT3
400f3290 a CYREG_UDB_P1_U1_PLD_IT4
400f3290 a CYREG_UDB_P1_U1_PLD_IT4
400f3294 a CYREG_UDB_P1_U1_PLD_IT5
400f3294 a CYREG_UDB_P1_U1_PLD_IT5
400f3298 a CYREG_UDB_P1_U1_PLD_IT6
400f3298 a CYREG_UDB_P1_U1_PLD_IT6
400f329c a CYREG_UDB_P1_U1_PLD_IT7
400f329c a CYREG_UDB_P1_U1_PLD_IT7
400f32a0 a CYREG_UDB_P1_U1_PLD_IT8
400f32a0 a CYREG_UDB_P1_U1_PLD_IT8
400f32a4 a CYREG_UDB_P1_U1_PLD_IT9
400f32a4 a CYREG_UDB_P1_U1_PLD_IT9
400f32be a CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS
400f32be a CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS
400f32b8 a CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST
400f32b8 a CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST
400f32ba a CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB
400f32ba a CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB
400f32bc a CYREG_UDB_P1_U1_PLD_MC_SET_RESET
400f32bc a CYREG_UDB_P1_U1_PLD_MC_SET_RESET
400f32b0 a CYREG_UDB_P1_U1_PLD_ORT0
400f32b0 a CYREG_UDB_P1_U1_PLD_ORT0
400f32b2 a CYREG_UDB_P1_U1_PLD_ORT1
400f32b2 a CYREG_UDB_P1_U1_PLD_ORT1
400f32b4 a CYREG_UDB_P1_U1_PLD_ORT2
400f32b4 a CYREG_UDB_P1_U1_PLD_ORT2
400f32b6 a CYREG_UDB_P1_U1_PLD_ORT3
400f32b6 a CYREG_UDB_P1_U1_PLD_ORT3
400f5000 a CYREG_UDB_PA0_CFG0
400f5000 a CYREG_UDB_PA0_CFG0
400f5001 a CYREG_UDB_PA0_CFG1
400f5001 a CYREG_UDB_PA0_CFG1
400f500a a CYREG_UDB_PA0_CFG10
400f500a a CYREG_UDB_PA0_CFG10
400f500b a CYREG_UDB_PA0_CFG11
400f500b a CYREG_UDB_PA0_CFG11
400f500c a CYREG_UDB_PA0_CFG12
400f500c a CYREG_UDB_PA0_CFG12
400f500d a CYREG_UDB_PA0_CFG13
400f500d a CYREG_UDB_PA0_CFG13
400f500e a CYREG_UDB_PA0_CFG14
400f500e a CYREG_UDB_PA0_CFG14
400f5002 a CYREG_UDB_PA0_CFG2
400f5002 a CYREG_UDB_PA0_CFG2
400f5003 a CYREG_UDB_PA0_CFG3
400f5003 a CYREG_UDB_PA0_CFG3
400f5004 a CYREG_UDB_PA0_CFG4
400f5004 a CYREG_UDB_PA0_CFG4
400f5005 a CYREG_UDB_PA0_CFG5
400f5005 a CYREG_UDB_PA0_CFG5
400f5006 a CYREG_UDB_PA0_CFG6
400f5006 a CYREG_UDB_PA0_CFG6
400f5007 a CYREG_UDB_PA0_CFG7
400f5007 a CYREG_UDB_PA0_CFG7
400f5008 a CYREG_UDB_PA0_CFG8
400f5008 a CYREG_UDB_PA0_CFG8
400f5009 a CYREG_UDB_PA0_CFG9
400f5009 a CYREG_UDB_PA0_CFG9
400f5010 a CYREG_UDB_PA1_CFG0
400f5010 a CYREG_UDB_PA1_CFG0
400f5011 a CYREG_UDB_PA1_CFG1
400f5011 a CYREG_UDB_PA1_CFG1
400f501a a CYREG_UDB_PA1_CFG10
400f501a a CYREG_UDB_PA1_CFG10
400f501b a CYREG_UDB_PA1_CFG11
400f501b a CYREG_UDB_PA1_CFG11
400f501c a CYREG_UDB_PA1_CFG12
400f501c a CYREG_UDB_PA1_CFG12
400f501d a CYREG_UDB_PA1_CFG13
400f501d a CYREG_UDB_PA1_CFG13
400f501e a CYREG_UDB_PA1_CFG14
400f501e a CYREG_UDB_PA1_CFG14
400f5012 a CYREG_UDB_PA1_CFG2
400f5012 a CYREG_UDB_PA1_CFG2
400f5013 a CYREG_UDB_PA1_CFG3
400f5013 a CYREG_UDB_PA1_CFG3
400f5014 a CYREG_UDB_PA1_CFG4
400f5014 a CYREG_UDB_PA1_CFG4
400f5015 a CYREG_UDB_PA1_CFG5
400f5015 a CYREG_UDB_PA1_CFG5
400f5016 a CYREG_UDB_PA1_CFG6
400f5016 a CYREG_UDB_PA1_CFG6
400f5017 a CYREG_UDB_PA1_CFG7
400f5017 a CYREG_UDB_PA1_CFG7
400f5018 a CYREG_UDB_PA1_CFG8
400f5018 a CYREG_UDB_PA1_CFG8
400f5019 a CYREG_UDB_PA1_CFG9
400f5019 a CYREG_UDB_PA1_CFG9
400f5020 a CYREG_UDB_PA2_CFG0
400f5020 a CYREG_UDB_PA2_CFG0
400f5021 a CYREG_UDB_PA2_CFG1
400f5021 a CYREG_UDB_PA2_CFG1
400f502a a CYREG_UDB_PA2_CFG10
400f502a a CYREG_UDB_PA2_CFG10
400f502b a CYREG_UDB_PA2_CFG11
400f502b a CYREG_UDB_PA2_CFG11
400f502c a CYREG_UDB_PA2_CFG12
400f502c a CYREG_UDB_PA2_CFG12
400f502d a CYREG_UDB_PA2_CFG13
400f502d a CYREG_UDB_PA2_CFG13
400f502e a CYREG_UDB_PA2_CFG14
400f502e a CYREG_UDB_PA2_CFG14
400f5022 a CYREG_UDB_PA2_CFG2
400f5022 a CYREG_UDB_PA2_CFG2
400f5023 a CYREG_UDB_PA2_CFG3
400f5023 a CYREG_UDB_PA2_CFG3
400f5024 a CYREG_UDB_PA2_CFG4
400f5024 a CYREG_UDB_PA2_CFG4
400f5025 a CYREG_UDB_PA2_CFG5
400f5025 a CYREG_UDB_PA2_CFG5
400f5026 a CYREG_UDB_PA2_CFG6
400f5026 a CYREG_UDB_PA2_CFG6
400f5027 a CYREG_UDB_PA2_CFG7
400f5027 a CYREG_UDB_PA2_CFG7
400f5028 a CYREG_UDB_PA2_CFG8
400f5028 a CYREG_UDB_PA2_CFG8
400f5029 a CYREG_UDB_PA2_CFG9
400f5029 a CYREG_UDB_PA2_CFG9
400f5030 a CYREG_UDB_PA3_CFG0
400f5030 a CYREG_UDB_PA3_CFG0
400f5031 a CYREG_UDB_PA3_CFG1
400f5031 a CYREG_UDB_PA3_CFG1
400f503a a CYREG_UDB_PA3_CFG10
400f503a a CYREG_UDB_PA3_CFG10
400f503b a CYREG_UDB_PA3_CFG11
400f503b a CYREG_UDB_PA3_CFG11
400f503c a CYREG_UDB_PA3_CFG12
400f503c a CYREG_UDB_PA3_CFG12
400f503d a CYREG_UDB_PA3_CFG13
400f503d a CYREG_UDB_PA3_CFG13
400f503e a CYREG_UDB_PA3_CFG14
400f503e a CYREG_UDB_PA3_CFG14
400f5032 a CYREG_UDB_PA3_CFG2
400f5032 a CYREG_UDB_PA3_CFG2
400f5033 a CYREG_UDB_PA3_CFG3
400f5033 a CYREG_UDB_PA3_CFG3
400f5034 a CYREG_UDB_PA3_CFG4
400f5034 a CYREG_UDB_PA3_CFG4
400f5035 a CYREG_UDB_PA3_CFG5
400f5035 a CYREG_UDB_PA3_CFG5
400f5036 a CYREG_UDB_PA3_CFG6
400f5036 a CYREG_UDB_PA3_CFG6
400f5037 a CYREG_UDB_PA3_CFG7
400f5037 a CYREG_UDB_PA3_CFG7
400f5038 a CYREG_UDB_PA3_CFG8
400f5038 a CYREG_UDB_PA3_CFG8
400f5039 a CYREG_UDB_PA3_CFG9
400f5039 a CYREG_UDB_PA3_CFG9
400f7000 a CYREG_UDB_UDBIF_BANK_CTL
400f7000 a CYREG_UDB_UDBIF_BANK_CTL
400f701c a CYREG_UDB_UDBIF_INT_CLK_CTL
400f701c a CYREG_UDB_UDBIF_INT_CLK_CTL
400f7001 a CYREG_UDB_UDBIF_WAIT_CFG
400f7001 a CYREG_UDB_UDBIF_WAIT_CFG
400f1000 a CYREG_UDB_W16_A0_00
400f1000 a CYREG_UDB_W16_A0_00
400f1002 a CYREG_UDB_W16_A0_01
400f1002 a CYREG_UDB_W16_A0_01
400f1004 a CYREG_UDB_W16_A0_02
400f1004 a CYREG_UDB_W16_A0_02
400f1000 a CYREG_UDB_W16_A00
400f1000 a CYREG_UDB_W16_A00
400f1002 a CYREG_UDB_W16_A01
400f1002 a CYREG_UDB_W16_A01
400f1004 a CYREG_UDB_W16_A02
400f1004 a CYREG_UDB_W16_A02
400f1020 a CYREG_UDB_W16_A1_00
400f1020 a CYREG_UDB_W16_A1_00
400f1022 a CYREG_UDB_W16_A1_01
400f1022 a CYREG_UDB_W16_A1_01
400f1024 a CYREG_UDB_W16_A1_02
400f1024 a CYREG_UDB_W16_A1_02
400f1020 a CYREG_UDB_W16_A10
400f1020 a CYREG_UDB_W16_A10
400f1022 a CYREG_UDB_W16_A11
400f1022 a CYREG_UDB_W16_A11
400f1024 a CYREG_UDB_W16_A12
400f1024 a CYREG_UDB_W16_A12
400f1120 a CYREG_UDB_W16_ACTL_00
400f1120 a CYREG_UDB_W16_ACTL_00
400f1122 a CYREG_UDB_W16_ACTL_01
400f1122 a CYREG_UDB_W16_ACTL_01
400f1124 a CYREG_UDB_W16_ACTL_02
400f1124 a CYREG_UDB_W16_ACTL_02
400f1120 a CYREG_UDB_W16_ACTL0
400f1120 a CYREG_UDB_W16_ACTL0
400f1122 a CYREG_UDB_W16_ACTL1
400f1122 a CYREG_UDB_W16_ACTL1
400f1124 a CYREG_UDB_W16_ACTL2
400f1124 a CYREG_UDB_W16_ACTL2
400f10e0 a CYREG_UDB_W16_CTL_00
400f10e0 a CYREG_UDB_W16_CTL_00
400f10e2 a CYREG_UDB_W16_CTL_01
400f10e2 a CYREG_UDB_W16_CTL_01
400f10e4 a CYREG_UDB_W16_CTL_02
400f10e4 a CYREG_UDB_W16_CTL_02
400f10e0 a CYREG_UDB_W16_CTL0
400f10e0 a CYREG_UDB_W16_CTL0
400f10e2 a CYREG_UDB_W16_CTL1
400f10e2 a CYREG_UDB_W16_CTL1
400f10e4 a CYREG_UDB_W16_CTL2
400f10e4 a CYREG_UDB_W16_CTL2
400f1040 a CYREG_UDB_W16_D0_00
400f1040 a CYREG_UDB_W16_D0_00
400f1042 a CYREG_UDB_W16_D0_01
400f1042 a CYREG_UDB_W16_D0_01
400f1044 a CYREG_UDB_W16_D0_02
400f1044 a CYREG_UDB_W16_D0_02
400f1040 a CYREG_UDB_W16_D00
400f1040 a CYREG_UDB_W16_D00
400f1042 a CYREG_UDB_W16_D01
400f1042 a CYREG_UDB_W16_D01
400f1044 a CYREG_UDB_W16_D02
400f1044 a CYREG_UDB_W16_D02
400f1060 a CYREG_UDB_W16_D1_00
400f1060 a CYREG_UDB_W16_D1_00
400f1062 a CYREG_UDB_W16_D1_01
400f1062 a CYREG_UDB_W16_D1_01
400f1064 a CYREG_UDB_W16_D1_02
400f1064 a CYREG_UDB_W16_D1_02
400f1060 a CYREG_UDB_W16_D10
400f1060 a CYREG_UDB_W16_D10
400f1062 a CYREG_UDB_W16_D11
400f1062 a CYREG_UDB_W16_D11
400f1064 a CYREG_UDB_W16_D12
400f1064 a CYREG_UDB_W16_D12
400f1080 a CYREG_UDB_W16_F0_00
400f1080 a CYREG_UDB_W16_F0_00
400f1082 a CYREG_UDB_W16_F0_01
400f1082 a CYREG_UDB_W16_F0_01
400f1084 a CYREG_UDB_W16_F0_02
400f1084 a CYREG_UDB_W16_F0_02
400f1080 a CYREG_UDB_W16_F00
400f1080 a CYREG_UDB_W16_F00
400f1082 a CYREG_UDB_W16_F01
400f1082 a CYREG_UDB_W16_F01
400f1084 a CYREG_UDB_W16_F02
400f1084 a CYREG_UDB_W16_F02
400f10a0 a CYREG_UDB_W16_F1_00
400f10a0 a CYREG_UDB_W16_F1_00
400f10a2 a CYREG_UDB_W16_F1_01
400f10a2 a CYREG_UDB_W16_F1_01
400f10a4 a CYREG_UDB_W16_F1_02
400f10a4 a CYREG_UDB_W16_F1_02
400f10a0 a CYREG_UDB_W16_F10
400f10a0 a CYREG_UDB_W16_F10
400f10a2 a CYREG_UDB_W16_F11
400f10a2 a CYREG_UDB_W16_F11
400f10a4 a CYREG_UDB_W16_F12
400f10a4 a CYREG_UDB_W16_F12
400f1140 a CYREG_UDB_W16_MC_00
400f1140 a CYREG_UDB_W16_MC_00
400f1142 a CYREG_UDB_W16_MC_01
400f1142 a CYREG_UDB_W16_MC_01
400f1144 a CYREG_UDB_W16_MC_02
400f1144 a CYREG_UDB_W16_MC_02
400f1140 a CYREG_UDB_W16_MC0
400f1140 a CYREG_UDB_W16_MC0
400f1142 a CYREG_UDB_W16_MC1
400f1142 a CYREG_UDB_W16_MC1
400f1144 a CYREG_UDB_W16_MC2
400f1144 a CYREG_UDB_W16_MC2
400f1100 a CYREG_UDB_W16_MSK_00
400f1100 a CYREG_UDB_W16_MSK_00
400f1102 a CYREG_UDB_W16_MSK_01
400f1102 a CYREG_UDB_W16_MSK_01
400f1104 a CYREG_UDB_W16_MSK_02
400f1104 a CYREG_UDB_W16_MSK_02
400f1100 a CYREG_UDB_W16_MSK0
400f1100 a CYREG_UDB_W16_MSK0
400f1102 a CYREG_UDB_W16_MSK1
400f1102 a CYREG_UDB_W16_MSK1
400f1104 a CYREG_UDB_W16_MSK2
400f1104 a CYREG_UDB_W16_MSK2
400f10c0 a CYREG_UDB_W16_ST_00
400f10c0 a CYREG_UDB_W16_ST_00
400f10c2 a CYREG_UDB_W16_ST_01
400f10c2 a CYREG_UDB_W16_ST_01
400f10c4 a CYREG_UDB_W16_ST_02
400f10c4 a CYREG_UDB_W16_ST_02
400f10c0 a CYREG_UDB_W16_ST0
400f10c0 a CYREG_UDB_W16_ST0
400f10c2 a CYREG_UDB_W16_ST1
400f10c2 a CYREG_UDB_W16_ST1
400f10c4 a CYREG_UDB_W16_ST2
400f10c4 a CYREG_UDB_W16_ST2
400f2000 a CYREG_UDB_W32_A0
400f2000 a CYREG_UDB_W32_A0
400f2000 a CYREG_UDB_W32_A0_00
400f2000 a CYREG_UDB_W32_A0_00
400f2040 a CYREG_UDB_W32_A1
400f2040 a CYREG_UDB_W32_A1
400f2040 a CYREG_UDB_W32_A1_00
400f2040 a CYREG_UDB_W32_A1_00
400f2240 a CYREG_UDB_W32_ACTL
400f2240 a CYREG_UDB_W32_ACTL
400f2240 a CYREG_UDB_W32_ACTL_00
400f2240 a CYREG_UDB_W32_ACTL_00
400f21c0 a CYREG_UDB_W32_CTL
400f21c0 a CYREG_UDB_W32_CTL
400f21c0 a CYREG_UDB_W32_CTL_00
400f21c0 a CYREG_UDB_W32_CTL_00
400f2080 a CYREG_UDB_W32_D0
400f2080 a CYREG_UDB_W32_D0
400f2080 a CYREG_UDB_W32_D0_00
400f2080 a CYREG_UDB_W32_D0_00
400f20c0 a CYREG_UDB_W32_D1
400f20c0 a CYREG_UDB_W32_D1
400f20c0 a CYREG_UDB_W32_D1_00
400f20c0 a CYREG_UDB_W32_D1_00
400f2100 a CYREG_UDB_W32_F0
400f2100 a CYREG_UDB_W32_F0
400f2100 a CYREG_UDB_W32_F0_00
400f2100 a CYREG_UDB_W32_F0_00
400f2140 a CYREG_UDB_W32_F1
400f2140 a CYREG_UDB_W32_F1
400f2140 a CYREG_UDB_W32_F1_00
400f2140 a CYREG_UDB_W32_F1_00
400f2280 a CYREG_UDB_W32_MC
400f2280 a CYREG_UDB_W32_MC
400f2280 a CYREG_UDB_W32_MC_00
400f2280 a CYREG_UDB_W32_MC_00
400f2200 a CYREG_UDB_W32_MSK
400f2200 a CYREG_UDB_W32_MSK
400f2200 a CYREG_UDB_W32_MSK_00
400f2200 a CYREG_UDB_W32_MSK_00
400f2180 a CYREG_UDB_W32_ST
400f2180 a CYREG_UDB_W32_ST
400f2180 a CYREG_UDB_W32_ST_00
400f2180 a CYREG_UDB_W32_ST_00
400f0000 a CYREG_UDB_W8_A0_00
400f0000 a CYREG_UDB_W8_A0_00
400f0001 a CYREG_UDB_W8_A0_01
400f0001 a CYREG_UDB_W8_A0_01
400f0002 a CYREG_UDB_W8_A0_02
400f0002 a CYREG_UDB_W8_A0_02
400f0003 a CYREG_UDB_W8_A0_03
400f0003 a CYREG_UDB_W8_A0_03
400f0000 a CYREG_UDB_W8_A00
400f0000 a CYREG_UDB_W8_A00
400f0001 a CYREG_UDB_W8_A01
400f0001 a CYREG_UDB_W8_A01
400f0002 a CYREG_UDB_W8_A02
400f0002 a CYREG_UDB_W8_A02
400f0003 a CYREG_UDB_W8_A03
400f0003 a CYREG_UDB_W8_A03
400f0010 a CYREG_UDB_W8_A1_00
400f0010 a CYREG_UDB_W8_A1_00
400f0011 a CYREG_UDB_W8_A1_01
400f0011 a CYREG_UDB_W8_A1_01
400f0012 a CYREG_UDB_W8_A1_02
400f0012 a CYREG_UDB_W8_A1_02
400f0013 a CYREG_UDB_W8_A1_03
400f0013 a CYREG_UDB_W8_A1_03
400f0010 a CYREG_UDB_W8_A10
400f0010 a CYREG_UDB_W8_A10
400f0011 a CYREG_UDB_W8_A11
400f0011 a CYREG_UDB_W8_A11
400f0012 a CYREG_UDB_W8_A12
400f0012 a CYREG_UDB_W8_A12
400f0013 a CYREG_UDB_W8_A13
400f0013 a CYREG_UDB_W8_A13
400f0090 a CYREG_UDB_W8_ACTL_00
400f0090 a CYREG_UDB_W8_ACTL_00
400f0091 a CYREG_UDB_W8_ACTL_01
400f0091 a CYREG_UDB_W8_ACTL_01
400f0092 a CYREG_UDB_W8_ACTL_02
400f0092 a CYREG_UDB_W8_ACTL_02
400f0093 a CYREG_UDB_W8_ACTL_03
400f0093 a CYREG_UDB_W8_ACTL_03
400f0090 a CYREG_UDB_W8_ACTL0
400f0090 a CYREG_UDB_W8_ACTL0
400f0091 a CYREG_UDB_W8_ACTL1
400f0091 a CYREG_UDB_W8_ACTL1
400f0092 a CYREG_UDB_W8_ACTL2
400f0092 a CYREG_UDB_W8_ACTL2
400f0093 a CYREG_UDB_W8_ACTL3
400f0093 a CYREG_UDB_W8_ACTL3
400f0070 a CYREG_UDB_W8_CTL_00
400f0070 a CYREG_UDB_W8_CTL_00
400f0071 a CYREG_UDB_W8_CTL_01
400f0071 a CYREG_UDB_W8_CTL_01
400f0072 a CYREG_UDB_W8_CTL_02
400f0072 a CYREG_UDB_W8_CTL_02
400f0073 a CYREG_UDB_W8_CTL_03
400f0073 a CYREG_UDB_W8_CTL_03
400f0070 a CYREG_UDB_W8_CTL0
400f0070 a CYREG_UDB_W8_CTL0
400f0071 a CYREG_UDB_W8_CTL1
400f0071 a CYREG_UDB_W8_CTL1
400f0072 a CYREG_UDB_W8_CTL2
400f0072 a CYREG_UDB_W8_CTL2
400f0073 a CYREG_UDB_W8_CTL3
400f0073 a CYREG_UDB_W8_CTL3
400f0020 a CYREG_UDB_W8_D0_00
400f0020 a CYREG_UDB_W8_D0_00
400f0021 a CYREG_UDB_W8_D0_01
400f0021 a CYREG_UDB_W8_D0_01
400f0022 a CYREG_UDB_W8_D0_02
400f0022 a CYREG_UDB_W8_D0_02
400f0023 a CYREG_UDB_W8_D0_03
400f0023 a CYREG_UDB_W8_D0_03
400f0020 a CYREG_UDB_W8_D00
400f0020 a CYREG_UDB_W8_D00
400f0021 a CYREG_UDB_W8_D01
400f0021 a CYREG_UDB_W8_D01
400f0022 a CYREG_UDB_W8_D02
400f0022 a CYREG_UDB_W8_D02
400f0023 a CYREG_UDB_W8_D03
400f0023 a CYREG_UDB_W8_D03
400f0030 a CYREG_UDB_W8_D1_00
400f0030 a CYREG_UDB_W8_D1_00
400f0031 a CYREG_UDB_W8_D1_01
400f0031 a CYREG_UDB_W8_D1_01
400f0032 a CYREG_UDB_W8_D1_02
400f0032 a CYREG_UDB_W8_D1_02
400f0033 a CYREG_UDB_W8_D1_03
400f0033 a CYREG_UDB_W8_D1_03
400f0030 a CYREG_UDB_W8_D10
400f0030 a CYREG_UDB_W8_D10
400f0031 a CYREG_UDB_W8_D11
400f0031 a CYREG_UDB_W8_D11
400f0032 a CYREG_UDB_W8_D12
400f0032 a CYREG_UDB_W8_D12
400f0033 a CYREG_UDB_W8_D13
400f0033 a CYREG_UDB_W8_D13
400f0040 a CYREG_UDB_W8_F0_00
400f0040 a CYREG_UDB_W8_F0_00
400f0041 a CYREG_UDB_W8_F0_01
400f0041 a CYREG_UDB_W8_F0_01
400f0042 a CYREG_UDB_W8_F0_02
400f0042 a CYREG_UDB_W8_F0_02
400f0043 a CYREG_UDB_W8_F0_03
400f0043 a CYREG_UDB_W8_F0_03
400f0040 a CYREG_UDB_W8_F00
400f0040 a CYREG_UDB_W8_F00
400f0041 a CYREG_UDB_W8_F01
400f0041 a CYREG_UDB_W8_F01
400f0042 a CYREG_UDB_W8_F02
400f0042 a CYREG_UDB_W8_F02
400f0043 a CYREG_UDB_W8_F03
400f0043 a CYREG_UDB_W8_F03
400f0050 a CYREG_UDB_W8_F1_00
400f0050 a CYREG_UDB_W8_F1_00
400f0051 a CYREG_UDB_W8_F1_01
400f0051 a CYREG_UDB_W8_F1_01
400f0052 a CYREG_UDB_W8_F1_02
400f0052 a CYREG_UDB_W8_F1_02
400f0053 a CYREG_UDB_W8_F1_03
400f0053 a CYREG_UDB_W8_F1_03
400f0050 a CYREG_UDB_W8_F10
400f0050 a CYREG_UDB_W8_F10
400f0051 a CYREG_UDB_W8_F11
400f0051 a CYREG_UDB_W8_F11
400f0052 a CYREG_UDB_W8_F12
400f0052 a CYREG_UDB_W8_F12
400f0053 a CYREG_UDB_W8_F13
400f0053 a CYREG_UDB_W8_F13
400f00a0 a CYREG_UDB_W8_MC_00
400f00a0 a CYREG_UDB_W8_MC_00
400f00a1 a CYREG_UDB_W8_MC_01
400f00a1 a CYREG_UDB_W8_MC_01
400f00a2 a CYREG_UDB_W8_MC_02
400f00a2 a CYREG_UDB_W8_MC_02
400f00a3 a CYREG_UDB_W8_MC_03
400f00a3 a CYREG_UDB_W8_MC_03
400f00a0 a CYREG_UDB_W8_MC0
400f00a0 a CYREG_UDB_W8_MC0
400f00a1 a CYREG_UDB_W8_MC1
400f00a1 a CYREG_UDB_W8_MC1
400f00a2 a CYREG_UDB_W8_MC2
400f00a2 a CYREG_UDB_W8_MC2
400f00a3 a CYREG_UDB_W8_MC3
400f00a3 a CYREG_UDB_W8_MC3
400f0080 a CYREG_UDB_W8_MSK_00
400f0080 a CYREG_UDB_W8_MSK_00
400f0081 a CYREG_UDB_W8_MSK_01
400f0081 a CYREG_UDB_W8_MSK_01
400f0082 a CYREG_UDB_W8_MSK_02
400f0082 a CYREG_UDB_W8_MSK_02
400f0083 a CYREG_UDB_W8_MSK_03
400f0083 a CYREG_UDB_W8_MSK_03
400f0080 a CYREG_UDB_W8_MSK0
400f0080 a CYREG_UDB_W8_MSK0
400f0081 a CYREG_UDB_W8_MSK1
400f0081 a CYREG_UDB_W8_MSK1
400f0082 a CYREG_UDB_W8_MSK2
400f0082 a CYREG_UDB_W8_MSK2
400f0083 a CYREG_UDB_W8_MSK3
400f0083 a CYREG_UDB_W8_MSK3
400f0060 a CYREG_UDB_W8_ST_00
400f0060 a CYREG_UDB_W8_ST_00
400f0061 a CYREG_UDB_W8_ST_01
400f0061 a CYREG_UDB_W8_ST_01
400f0062 a CYREG_UDB_W8_ST_02
400f0062 a CYREG_UDB_W8_ST_02
400f0063 a CYREG_UDB_W8_ST_03
400f0063 a CYREG_UDB_W8_ST_03
400f0060 a CYREG_UDB_W8_ST0
400f0060 a CYREG_UDB_W8_ST0
400f0061 a CYREG_UDB_W8_ST1
400f0061 a CYREG_UDB_W8_ST1
400f0062 a CYREG_UDB_W8_ST2
400f0062 a CYREG_UDB_W8_ST2
400f0063 a CYREG_UDB_W8_ST3
400f0063 a CYREG_UDB_W8_ST3
400b020c a CYREG_WDT_CONFIG
400b020c a CYREG_WDT_CONFIG
400b0210 a CYREG_WDT_CONTROL
400b0210 a CYREG_WDT_CONTROL
400b0204 a CYREG_WDT_CTRHIGH
400b0204 a CYREG_WDT_CTRHIGH
400b0200 a CYREG_WDT_CTRLOW
400b0200 a CYREG_WDT_CTRLOW
400b0208 a CYREG_WDT_MATCH
400b0208 a CYREG_WDT_MATCH
00002710 T CySoftwareReset
000026fc T CySysClkEcoReadStatus
000028d0 T CySysClkEcoStart
20000f5c D CySysClkPumpConfig
00002aa0 T CySysClkWcoSetPowerMode
00002a60 T CySysClkWcoStart
0000276c T CySysClkWriteImoFreq
000026cc T CySysClkWriteSysclkDiv
0000259c t CySysFlashClockBackup
000025a0 t CySysFlashClockRestore
000025a4 T CySysFlashWriteRow
00002940 T CySysPmDeepSleep
00002998 T CySysPmHibernate
00002924 T CySysPmSleep
00002ca0 T CySysWdtClearInterrupt
00002bfc T CySysWdtEnable
00002b6c T CySysWdtGetEnabledStatus
00002c8c T CySysWdtGetInterruptSource
00002b20 T CySysWdtLock
00002a4c t CySysWdtLocked
00002cec T CySysWdtResetCounters
00002bc8 T CySysWdtSetClearOnMatch
00002c38 T CySysWdtSetMatch
00002b90 T CySysWdtSetMode
00002b3c T CySysWdtUnlock
00000004 a CYVAL__DBL_SEL_DSI0
00000004 a CYVAL__DBL_SEL_DSI0
00000005 a CYVAL__DBL_SEL_DSI1
00000005 a CYVAL__DBL_SEL_DSI1
00000006 a CYVAL__DBL_SEL_DSI2
00000006 a CYVAL__DBL_SEL_DSI2
00000007 a CYVAL__DBL_SEL_DSI3
00000007 a CYVAL__DBL_SEL_DSI3
00000002 a CYVAL__DBL_SEL_ECO
00000002 a CYVAL__DBL_SEL_ECO
00000001 a CYVAL__DBL_SEL_EXTCLK
00000001 a CYVAL__DBL_SEL_EXTCLK
00000000 a CYVAL__DBL_SEL_IMO
00000000 a CYVAL__DBL_SEL_IMO
00000000 a CYVAL__DEBUG_SESSION_NO_SESSION
00000000 a CYVAL__DEBUG_SESSION_NO_SESSION
00000001 a CYVAL__DEBUG_SESSION_SESSION_ACTIVE
00000001 a CYVAL__DEBUG_SESSION_SESSION_ACTIVE
00000001 a CYVAL__DFT_DIV1_DIV_BY_2
00000001 a CYVAL__DFT_DIV1_DIV_BY_2
00000002 a CYVAL__DFT_DIV1_DIV_BY_4
00000002 a CYVAL__DFT_DIV1_DIV_BY_4
00000003 a CYVAL__DFT_DIV1_DIV_BY_8
00000003 a CYVAL__DFT_DIV1_DIV_BY_8
00000000 a CYVAL__DFT_DIV1_NO_DIV
00000000 a CYVAL__DFT_DIV1_NO_DIV
00000001 a CYVAL__DFT_DIV2_DIV_BY_2
00000001 a CYVAL__DFT_DIV2_DIV_BY_2
00000002 a CYVAL__DFT_DIV2_DIV_BY_4
00000002 a CYVAL__DFT_DIV2_DIV_BY_4
00000003 a CYVAL__DFT_DIV2_DIV_BY_8
00000003 a CYVAL__DFT_DIV2_DIV_BY_8
00000000 a CYVAL__DFT_DIV2_NO_DIV
00000000 a CYVAL__DFT_DIV2_NO_DIV
00000008 a CYVAL__DFT_SEL1_DBL
00000008 a CYVAL__DFT_SEL1_DBL
00000006 a CYVAL__DFT_SEL1_DPLL_OUT
00000006 a CYVAL__DFT_SEL1_DPLL_OUT
00000007 a CYVAL__DFT_SEL1_DPLL_REF
00000007 a CYVAL__DFT_SEL1_DPLL_REF
00000004 a CYVAL__DFT_SEL1_ECO
00000004 a CYVAL__DFT_SEL1_ECO
0000000e a CYVAL__DFT_SEL1_EXTCLK
0000000e a CYVAL__DFT_SEL1_EXTCLK
0000000f a CYVAL__DFT_SEL1_HALFSYSCLK
0000000f a CYVAL__DFT_SEL1_HALFSYSCLK
0000000b a CYVAL__DFT_SEL1_HFCLK
0000000b a CYVAL__DFT_SEL1_HFCLK
00000001 a CYVAL__DFT_SEL1_ILO
00000001 a CYVAL__DFT_SEL1_ILO
00000003 a CYVAL__DFT_SEL1_IMO
00000003 a CYVAL__DFT_SEL1_IMO
00000009 a CYVAL__DFT_SEL1_IMO2X
00000009 a CYVAL__DFT_SEL1_IMO2X
0000000a a CYVAL__DFT_SEL1_IMO36
0000000a a CYVAL__DFT_SEL1_IMO36
0000000c a CYVAL__DFT_SEL1_LFCLK
0000000c a CYVAL__DFT_SEL1_LFCLK
00000000 a CYVAL__DFT_SEL1_NC
00000000 a CYVAL__DFT_SEL1_NC
00000005 a CYVAL__DFT_SEL1_PLL
00000005 a CYVAL__DFT_SEL1_PLL
0000000d a CYVAL__DFT_SEL1_SYSCLK
0000000d a CYVAL__DFT_SEL1_SYSCLK
00000002 a CYVAL__DFT_SEL1_WCO
00000002 a CYVAL__DFT_SEL1_WCO
00000008 a CYVAL__DFT_SEL2_DBL
00000008 a CYVAL__DFT_SEL2_DBL
00000006 a CYVAL__DFT_SEL2_DPLL_OUT
00000006 a CYVAL__DFT_SEL2_DPLL_OUT
00000007 a CYVAL__DFT_SEL2_DPLL_REF
00000007 a CYVAL__DFT_SEL2_DPLL_REF
00000004 a CYVAL__DFT_SEL2_ECO
00000004 a CYVAL__DFT_SEL2_ECO
0000000e a CYVAL__DFT_SEL2_EXTCLK
0000000e a CYVAL__DFT_SEL2_EXTCLK
0000000f a CYVAL__DFT_SEL2_HALFSYSCLK
0000000f a CYVAL__DFT_SEL2_HALFSYSCLK
0000000b a CYVAL__DFT_SEL2_HFCLK
0000000b a CYVAL__DFT_SEL2_HFCLK
00000001 a CYVAL__DFT_SEL2_ILO
00000001 a CYVAL__DFT_SEL2_ILO
00000003 a CYVAL__DFT_SEL2_IMO
00000003 a CYVAL__DFT_SEL2_IMO
00000009 a CYVAL__DFT_SEL2_IMO2X
00000009 a CYVAL__DFT_SEL2_IMO2X
0000000a a CYVAL__DFT_SEL2_IMO36
0000000a a CYVAL__DFT_SEL2_IMO36
0000000c a CYVAL__DFT_SEL2_LFCLK
0000000c a CYVAL__DFT_SEL2_LFCLK
00000000 a CYVAL__DFT_SEL2_NC
00000000 a CYVAL__DFT_SEL2_NC
00000005 a CYVAL__DFT_SEL2_PLL
00000005 a CYVAL__DFT_SEL2_PLL
0000000d a CYVAL__DFT_SEL2_SYSCLK
0000000d a CYVAL__DFT_SEL2_SYSCLK
00000002 a CYVAL__DFT_SEL2_WCO
00000002 a CYVAL__DFT_SEL2_WCO
00000004 a CYVAL__DIRECT_SEL_DSI0
00000004 a CYVAL__DIRECT_SEL_DSI0
00000005 a CYVAL__DIRECT_SEL_DSI1
00000005 a CYVAL__DIRECT_SEL_DSI1
00000006 a CYVAL__DIRECT_SEL_DSI2
00000006 a CYVAL__DIRECT_SEL_DSI2
00000007 a CYVAL__DIRECT_SEL_DSI3
00000007 a CYVAL__DIRECT_SEL_DSI3
00000002 a CYVAL__DIRECT_SEL_ECO
00000002 a CYVAL__DIRECT_SEL_ECO
00000001 a CYVAL__DIRECT_SEL_EXTCLK
00000001 a CYVAL__DIRECT_SEL_EXTCLK
00000000 a CYVAL__DIRECT_SEL_IMO
00000000 a CYVAL__DIRECT_SEL_IMO
00000004 a CYVAL__DPLLIN_SEL_DSI0
00000004 a CYVAL__DPLLIN_SEL_DSI0
00000005 a CYVAL__DPLLIN_SEL_DSI1
00000005 a CYVAL__DPLLIN_SEL_DSI1
00000006 a CYVAL__DPLLIN_SEL_DSI2
00000006 a CYVAL__DPLLIN_SEL_DSI2
00000007 a CYVAL__DPLLIN_SEL_DSI3
00000007 a CYVAL__DPLLIN_SEL_DSI3
00000002 a CYVAL__DPLLIN_SEL_ECO
00000002 a CYVAL__DPLLIN_SEL_ECO
00000001 a CYVAL__DPLLIN_SEL_EXTCLK
00000001 a CYVAL__DPLLIN_SEL_EXTCLK
00000000 a CYVAL__DPLLIN_SEL_IMO
00000000 a CYVAL__DPLLIN_SEL_IMO
00000000 a CYVAL__DPLLREF_SEL_DSI0
00000000 a CYVAL__DPLLREF_SEL_DSI0
00000001 a CYVAL__DPLLREF_SEL_DSI1
00000001 a CYVAL__DPLLREF_SEL_DSI1
00000002 a CYVAL__DPLLREF_SEL_DSI2
00000002 a CYVAL__DPLLREF_SEL_DSI2
00000003 a CYVAL__DPLLREF_SEL_DSI3
00000003 a CYVAL__DPLLREF_SEL_DSI3
00000001 a CYVAL__FLASHPUMP_SEL_CLK36
00000001 a CYVAL__FLASHPUMP_SEL_CLK36
00000000 a CYVAL__FLASHPUMP_SEL_GND
00000000 a CYVAL__FLASHPUMP_SEL_GND
00000001 a CYVAL__HFCLK_SEL_DBL
00000001 a CYVAL__HFCLK_SEL_DBL
00000000 a CYVAL__HFCLK_SEL_DIRECT_SEL
00000000 a CYVAL__HFCLK_SEL_DIRECT_SEL
00000002 a CYVAL__HFCLK_SEL_PLL
00000002 a CYVAL__HFCLK_SEL_PLL
00000000 a CYVAL__HIBERNATE_DEEP_SLEEP
00000000 a CYVAL__HIBERNATE_DEEP_SLEEP
00000001 a CYVAL__HIBERNATE_HIBERNATE
00000001 a CYVAL__HIBERNATE_HIBERNATE
00000001 a CYVAL__PD_MODE_COMA
00000001 a CYVAL__PD_MODE_COMA
00000000 a CYVAL__PD_MODE_SLEEP
00000000 a CYVAL__PD_MODE_SLEEP
00000003 a CYVAL__PLL_SEL_DPLL
00000003 a CYVAL__PLL_SEL_DPLL
00000004 a CYVAL__PLL_SEL_DSI0
00000004 a CYVAL__PLL_SEL_DSI0
00000005 a CYVAL__PLL_SEL_DSI1
00000005 a CYVAL__PLL_SEL_DSI1
00000006 a CYVAL__PLL_SEL_DSI2
00000006 a CYVAL__PLL_SEL_DSI2
00000007 a CYVAL__PLL_SEL_DSI3
00000007 a CYVAL__PLL_SEL_DSI3
00000002 a CYVAL__PLL_SEL_ECO
00000002 a CYVAL__PLL_SEL_ECO
00000001 a CYVAL__PLL_SEL_EXTCLK
00000001 a CYVAL__PLL_SEL_EXTCLK
00000000 a CYVAL__PLL_SEL_IMO
00000000 a CYVAL__PLL_SEL_IMO
00000001 a CYVAL__POWER_MODE_ACTIVE
00000001 a CYVAL__POWER_MODE_ACTIVE
00000003 a CYVAL__POWER_MODE_DEEP_SLEEP
00000003 a CYVAL__POWER_MODE_DEEP_SLEEP
00000004 a CYVAL__POWER_MODE_HIBERNATE
00000004 a CYVAL__POWER_MODE_HIBERNATE
00000000 a CYVAL__POWER_MODE_RESET
00000000 a CYVAL__POWER_MODE_RESET
00000002 a CYVAL__POWER_MODE_SLEEP
00000002 a CYVAL__POWER_MODE_SLEEP
00000003 a CYVAL__PUMP_SEL_CLK36
00000003 a CYVAL__PUMP_SEL_CLK36
00000002 a CYVAL__PUMP_SEL_DBL
00000002 a CYVAL__PUMP_SEL_DBL
00000004 a CYVAL__PUMP_SEL_FF1
00000004 a CYVAL__PUMP_SEL_FF1
00000000 a CYVAL__PUMP_SEL_GND
00000000 a CYVAL__PUMP_SEL_GND
00000001 a CYVAL__PUMP_SEL_IMO
00000001 a CYVAL__PUMP_SEL_IMO
00000000 a CYVAL__SATBIAS_SATURATED
00000000 a CYVAL__SATBIAS_SATURATED
00000001 a CYVAL__SATBIAS_SUBTHRESHOLD
00000001 a CYVAL__SATBIAS_SUBTHRESHOLD
00000003 a CYVAL__SS_MODE_DSI
00000003 a CYVAL__SS_MODE_DSI
00000002 a CYVAL__SS_MODE_LFSR
00000002 a CYVAL__SS_MODE_LFSR
00000000 a CYVAL__SS_MODE_OFF
00000000 a CYVAL__SS_MODE_OFF
00000001 a CYVAL__SS_MODE_TRIANGLE
00000001 a CYVAL__SS_MODE_TRIANGLE
00000000 a CYVAL__SS_RANGE_M1
00000000 a CYVAL__SS_RANGE_M1
00000001 a CYVAL__SS_RANGE_M2
00000001 a CYVAL__SS_RANGE_M2
00000002 a CYVAL__SS_RANGE_M4
00000002 a CYVAL__SS_RANGE_M4
00000007 a CYVAL__SYSCLK_DIV_DIV_BY_128
00000007 a CYVAL__SYSCLK_DIV_DIV_BY_128
00000004 a CYVAL__SYSCLK_DIV_DIV_BY_16
00000004 a CYVAL__SYSCLK_DIV_DIV_BY_16
00000001 a CYVAL__SYSCLK_DIV_DIV_BY_2
00000001 a CYVAL__SYSCLK_DIV_DIV_BY_2
00000005 a CYVAL__SYSCLK_DIV_DIV_BY_32
00000005 a CYVAL__SYSCLK_DIV_DIV_BY_32
00000002 a CYVAL__SYSCLK_DIV_DIV_BY_4
00000002 a CYVAL__SYSCLK_DIV_DIV_BY_4
00000006 a CYVAL__SYSCLK_DIV_DIV_BY_64
00000006 a CYVAL__SYSCLK_DIV_DIV_BY_64
00000003 a CYVAL__SYSCLK_DIV_DIV_BY_8
00000003 a CYVAL__SYSCLK_DIV_DIV_BY_8
00000000 a CYVAL__SYSCLK_DIV_NO_DIV
00000000 a CYVAL__SYSCLK_DIV_NO_DIV
00000001 a CYVAL__WDT_LOCK_CLR0
00000001 a CYVAL__WDT_LOCK_CLR0
00000002 a CYVAL__WDT_LOCK_CLR1
00000002 a CYVAL__WDT_LOCK_CLR1
00000000 a CYVAL__WDT_LOCK_NO_CHG
00000000 a CYVAL__WDT_LOCK_NO_CHG
00000003 a CYVAL__WDT_LOCK_SET01
00000003 a CYVAL__WDT_LOCK_SET01
00000001 a CYVAL__WDT_MODE0_INT
00000001 a CYVAL__WDT_MODE0_INT
00000003 a CYVAL__WDT_MODE0_INT_THEN_RESET
00000003 a CYVAL__WDT_MODE0_INT_THEN_RESET
00000000 a CYVAL__WDT_MODE0_NOTHING
00000000 a CYVAL__WDT_MODE0_NOTHING
00000002 a CYVAL__WDT_MODE0_RESET
00000002 a CYVAL__WDT_MODE0_RESET
00000001 a CYVAL__WDT_MODE1_INT
00000001 a CYVAL__WDT_MODE1_INT
00000003 a CYVAL__WDT_MODE1_INT_THEN_RESET
00000003 a CYVAL__WDT_MODE1_INT_THEN_RESET
00000000 a CYVAL__WDT_MODE1_NOTHING
00000000 a CYVAL__WDT_MODE1_NOTHING
00000002 a CYVAL__WDT_MODE1_RESET
00000002 a CYVAL__WDT_MODE1_RESET
00000001 a CYVAL__WDT_MODE2_INT
00000001 a CYVAL__WDT_MODE2_INT
00000000 a CYVAL__WDT_MODE2_NOTHING
00000000 a CYVAL__WDT_MODE2_NOTHING
00000001 a CYVAL_CSD_BYPASS_SEL_DIRECT_CLOCK
00000001 a CYVAL_CSD_BYPASS_SEL_DIRECT_CLOCK
00000000 a CYVAL_CSD_BYPASS_SEL_PRS_OR_DIV2
00000000 a CYVAL_CSD_BYPASS_SEL_PRS_OR_DIV2
00000000 a CYVAL_CSD_COMP_MODE_CHARGE_BUF
00000000 a CYVAL_CSD_COMP_MODE_CHARGE_BUF
00000001 a CYVAL_CSD_COMP_MODE_CHARGE_IO
00000001 a CYVAL_CSD_COMP_MODE_CHARGE_IO
00000001 a CYVAL_CSD_COMP_OUT_C_GT_VREF
00000001 a CYVAL_CSD_COMP_OUT_C_GT_VREF
00000000 a CYVAL_CSD_COMP_OUT_C_LT_VREF
00000000 a CYVAL_CSD_COMP_OUT_C_LT_VREF
00000000 a CYVAL_CSD_COMP_PIN_CHANNEL1
00000000 a CYVAL_CSD_COMP_PIN_CHANNEL1
00000001 a CYVAL_CSD_COMP_PIN_CHANNEL2
00000001 a CYVAL_CSD_COMP_PIN_CHANNEL2
00000000 a CYVAL_CSD_DDFTCOMP_REFBUFCOMP
00000000 a CYVAL_CSD_DDFTCOMP_REFBUFCOMP
00000001 a CYVAL_CSD_DDFTCOMP_SENSECOMP
00000001 a CYVAL_CSD_DDFTCOMP_SENSECOMP
00000003 a CYVAL_CSD_DDFTSEL_CLK_SAMPLE
00000003 a CYVAL_CSD_DDFTSEL_CLK_SAMPLE
00000004 a CYVAL_CSD_DDFTSEL_COMP_OUT
00000004 a CYVAL_CSD_DDFTSEL_COMP_OUT
00000001 a CYVAL_CSD_DDFTSEL_CSD_SENSE
00000001 a CYVAL_CSD_DDFTSEL_CSD_SENSE
00000002 a CYVAL_CSD_DDFTSEL_CSD_SHIELD
00000002 a CYVAL_CSD_DDFTSEL_CSD_SHIELD
00000000 a CYVAL_CSD_DDFTSEL_NORMAL
00000000 a CYVAL_CSD_DDFTSEL_NORMAL
00000000 a CYVAL_CSD_DUAL_CAP_EN_DISABLE
00000000 a CYVAL_CSD_DUAL_CAP_EN_DISABLE
00000001 a CYVAL_CSD_DUAL_CAP_EN_ENABLE
00000001 a CYVAL_CSD_DUAL_CAP_EN_ENABLE
00000001 a CYVAL_CSD_FEEDBACK_MODE_COMP
00000001 a CYVAL_CSD_FEEDBACK_MODE_COMP
00000000 a CYVAL_CSD_FEEDBACK_MODE_FLOP
00000000 a CYVAL_CSD_FEEDBACK_MODE_FLOP
00000000 a CYVAL_CSD_FILTER_ENABLE_FILTER_OFF
00000000 a CYVAL_CSD_FILTER_ENABLE_FILTER_OFF
00000001 a CYVAL_CSD_FILTER_ENABLE_FILTER_ON
00000001 a CYVAL_CSD_FILTER_ENABLE_FILTER_ON
00000003 a CYVAL_CSD_IDAC1_MODE_DSI
00000003 a CYVAL_CSD_IDAC1_MODE_DSI
00000001 a CYVAL_CSD_IDAC1_MODE_FIXED
00000001 a CYVAL_CSD_IDAC1_MODE_FIXED
00000000 a CYVAL_CSD_IDAC1_MODE_OFF
00000000 a CYVAL_CSD_IDAC1_MODE_OFF
00000002 a CYVAL_CSD_IDAC1_MODE_VARIABLE
00000002 a CYVAL_CSD_IDAC1_MODE_VARIABLE
00000000 a CYVAL_CSD_IDAC1_RANGE_4X
00000000 a CYVAL_CSD_IDAC1_RANGE_4X
00000001 a CYVAL_CSD_IDAC1_RANGE_8X
00000001 a CYVAL_CSD_IDAC1_RANGE_8X
00000003 a CYVAL_CSD_IDAC2_MODE_DSI
00000003 a CYVAL_CSD_IDAC2_MODE_DSI
00000001 a CYVAL_CSD_IDAC2_MODE_FIXED
00000001 a CYVAL_CSD_IDAC2_MODE_FIXED
00000000 a CYVAL_CSD_IDAC2_MODE_OFF
00000000 a CYVAL_CSD_IDAC2_MODE_OFF
00000002 a CYVAL_CSD_IDAC2_MODE_VARIABLE
00000002 a CYVAL_CSD_IDAC2_MODE_VARIABLE
00000000 a CYVAL_CSD_IDAC2_RANGE_4X
00000000 a CYVAL_CSD_IDAC2_RANGE_4X
00000001 a CYVAL_CSD_IDAC2_RANGE_8X
00000001 a CYVAL_CSD_IDAC2_RANGE_8X
00000001 a CYVAL_CSD_MUTUAL_CAP_MUTUALCAP
00000001 a CYVAL_CSD_MUTUAL_CAP_MUTUALCAP
00000000 a CYVAL_CSD_MUTUAL_CAP_SELFCAP
00000000 a CYVAL_CSD_MUTUAL_CAP_SELFCAP
00000001 a CYVAL_CSD_POLARITY_VDDIO
00000001 a CYVAL_CSD_POLARITY_VDDIO
00000000 a CYVAL_CSD_POLARITY_VSSIO
00000000 a CYVAL_CSD_POLARITY_VSSIO
00000001 a CYVAL_CSD_POLARITY2_VDDIO
00000001 a CYVAL_CSD_POLARITY2_VDDIO
00000000 a CYVAL_CSD_POLARITY2_VSSIO
00000000 a CYVAL_CSD_POLARITY2_VSSIO
00000001 a CYVAL_CSD_PRS_12_8_12B
00000001 a CYVAL_CSD_PRS_12_8_12B
00000000 a CYVAL_CSD_PRS_12_8_8B
00000000 a CYVAL_CSD_PRS_12_8_8B
00000000 a CYVAL_CSD_PRS_SELECT_DIV2
00000000 a CYVAL_CSD_PRS_SELECT_DIV2
00000001 a CYVAL_CSD_PRS_SELECT_PRS
00000001 a CYVAL_CSD_PRS_SELECT_PRS
00000002 a CYVAL_CSD_PWM_SEL_FIXED_HIGH
00000002 a CYVAL_CSD_PWM_SEL_FIXED_HIGH
00000003 a CYVAL_CSD_PWM_SEL_FIXED_LOW
00000003 a CYVAL_CSD_PWM_SEL_FIXED_LOW
00000000 a CYVAL_CSD_PWM_SEL_OFF
00000000 a CYVAL_CSD_PWM_SEL_OFF
00000000 a CYVAL_CSD_REBUF_OUTSEL_AMUXA
00000000 a CYVAL_CSD_REBUF_OUTSEL_AMUXA
00000001 a CYVAL_CSD_REBUF_OUTSEL_AMUXB
00000001 a CYVAL_CSD_REBUF_OUTSEL_AMUXB
00000001 a CYVAL_CSD_REFBUF_DRV_DRV_1
00000001 a CYVAL_CSD_REFBUF_DRV_DRV_1
00000002 a CYVAL_CSD_REFBUF_DRV_DRV_2
00000002 a CYVAL_CSD_REFBUF_DRV_DRV_2
00000003 a CYVAL_CSD_REFBUF_DRV_DRV_3
00000003 a CYVAL_CSD_REFBUF_DRV_DRV_3
00000000 a CYVAL_CSD_REFBUF_DRV_OFF
00000000 a CYVAL_CSD_REFBUF_DRV_OFF
00000001 a CYVAL_CSD_SENSE_COMP_BW_HIGH
00000001 a CYVAL_CSD_SENSE_COMP_BW_HIGH
00000000 a CYVAL_CSD_SENSE_COMP_BW_LOW
00000000 a CYVAL_CSD_SENSE_COMP_BW_LOW
00000001 a CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA
00000001 a CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA
00000000 a CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1
00000000 a CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1
00000003 a CYVAL_CSD_SHIELD_DELAY_10NS
00000003 a CYVAL_CSD_SHIELD_DELAY_10NS
00000002 a CYVAL_CSD_SHIELD_DELAY_50NS
00000002 a CYVAL_CSD_SHIELD_DELAY_50NS
00000000 a CYVAL_CSD_SHIELD_DELAY_OFF
00000000 a CYVAL_CSD_SHIELD_DELAY_OFF
00000003 a CYVAL_CTBM_OA0_COMPINT_BOTH
00000003 a CYVAL_CTBM_OA0_COMPINT_BOTH
00000000 a CYVAL_CTBM_OA0_COMPINT_DISABLE
00000000 a CYVAL_CTBM_OA0_COMPINT_DISABLE
00000002 a CYVAL_CTBM_OA0_COMPINT_FALLING
00000002 a CYVAL_CTBM_OA0_COMPINT_FALLING
00000001 a CYVAL_CTBM_OA0_COMPINT_RISING
00000001 a CYVAL_CTBM_OA0_COMPINT_RISING
00000003 a CYVAL_CTBM_OA0_PWR_MODE_HIGH
00000003 a CYVAL_CTBM_OA0_PWR_MODE_HIGH
00000001 a CYVAL_CTBM_OA0_PWR_MODE_LOW
00000001 a CYVAL_CTBM_OA0_PWR_MODE_LOW
00000002 a CYVAL_CTBM_OA0_PWR_MODE_MEDIUM
00000002 a CYVAL_CTBM_OA0_PWR_MODE_MEDIUM
00000000 a CYVAL_CTBM_OA0_PWR_MODE_OFF
00000000 a CYVAL_CTBM_OA0_PWR_MODE_OFF
00000003 a CYVAL_CTBM_OA1_COMPINT_BOTH
00000003 a CYVAL_CTBM_OA1_COMPINT_BOTH
00000000 a CYVAL_CTBM_OA1_COMPINT_DISABLE
00000000 a CYVAL_CTBM_OA1_COMPINT_DISABLE
00000002 a CYVAL_CTBM_OA1_COMPINT_FALLING
00000002 a CYVAL_CTBM_OA1_COMPINT_FALLING
00000001 a CYVAL_CTBM_OA1_COMPINT_RISING
00000001 a CYVAL_CTBM_OA1_COMPINT_RISING
00000006 a CYVAL_GPIO_PRT_DM0_0_1
00000006 a CYVAL_GPIO_PRT_DM0_0_1
00000002 a CYVAL_GPIO_PRT_DM0_0_PU
00000002 a CYVAL_GPIO_PRT_DM0_0_PU
00000004 a CYVAL_GPIO_PRT_DM0_0_Z
00000004 a CYVAL_GPIO_PRT_DM0_0_Z
00000001 a CYVAL_GPIO_PRT_DM0_INPUT
00000001 a CYVAL_GPIO_PRT_DM0_INPUT
00000000 a CYVAL_GPIO_PRT_DM0_OFF
00000000 a CYVAL_GPIO_PRT_DM0_OFF
00000003 a CYVAL_GPIO_PRT_DM0_PD_1
00000003 a CYVAL_GPIO_PRT_DM0_PD_1
00000007 a CYVAL_GPIO_PRT_DM0_PD_PU
00000007 a CYVAL_GPIO_PRT_DM0_PD_PU
00000005 a CYVAL_GPIO_PRT_DM0_Z_1
00000005 a CYVAL_GPIO_PRT_DM0_Z_1
00000003 a CYVAL_GPIO_PRT_EDGE0_SEL_BOTH
00000003 a CYVAL_GPIO_PRT_EDGE0_SEL_BOTH
00000000 a CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE
00000000 a CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE
00000002 a CYVAL_GPIO_PRT_EDGE0_SEL_FALLING
00000002 a CYVAL_GPIO_PRT_EDGE0_SEL_FALLING
00000001 a CYVAL_GPIO_PRT_EDGE0_SEL_RISING
00000001 a CYVAL_GPIO_PRT_EDGE0_SEL_RISING
00000003 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH
00000003 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH
00000000 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE
00000000 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE
00000002 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING
00000002 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING
00000001 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING
00000001 a CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING
00000000 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_0
00000000 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_0
00000001 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_1
00000001 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_1
00000002 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_2
00000002 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_2
00000003 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_3
00000003 a CYVAL_GPIO_PRT_PORT_SLEW_CTL_PORT_SLEW_CTL_3
00000008 a CYVAL_HSIOM_IO0_SEL_ACT_0
00000008 a CYVAL_HSIOM_IO0_SEL_ACT_0
00000009 a CYVAL_HSIOM_IO0_SEL_ACT_1
00000009 a CYVAL_HSIOM_IO0_SEL_ACT_1
0000000a a CYVAL_HSIOM_IO0_SEL_ACT_2
0000000a a CYVAL_HSIOM_IO0_SEL_ACT_2
0000000b a CYVAL_HSIOM_IO0_SEL_ACT_3
0000000b a CYVAL_HSIOM_IO0_SEL_ACT_3
00000006 a CYVAL_HSIOM_IO0_SEL_AMUXA
00000006 a CYVAL_HSIOM_IO0_SEL_AMUXA
00000007 a CYVAL_HSIOM_IO0_SEL_AMUXB
00000007 a CYVAL_HSIOM_IO0_SEL_AMUXB
00000004 a CYVAL_HSIOM_IO0_SEL_CSD_SENSE
00000004 a CYVAL_HSIOM_IO0_SEL_CSD_SENSE
00000005 a CYVAL_HSIOM_IO0_SEL_CSD_SHIELD
00000005 a CYVAL_HSIOM_IO0_SEL_CSD_SHIELD
0000000c a CYVAL_HSIOM_IO0_SEL_DS_0
0000000c a CYVAL_HSIOM_IO0_SEL_DS_0
0000000d a CYVAL_HSIOM_IO0_SEL_DS_1
0000000d a CYVAL_HSIOM_IO0_SEL_DS_1
0000000e a CYVAL_HSIOM_IO0_SEL_DS_2
0000000e a CYVAL_HSIOM_IO0_SEL_DS_2
0000000f a CYVAL_HSIOM_IO0_SEL_DS_3
0000000f a CYVAL_HSIOM_IO0_SEL_DS_3
00000002 a CYVAL_HSIOM_IO0_SEL_DSI_DSI
00000002 a CYVAL_HSIOM_IO0_SEL_DSI_DSI
00000003 a CYVAL_HSIOM_IO0_SEL_DSI_GPIO
00000003 a CYVAL_HSIOM_IO0_SEL_DSI_GPIO
00000000 a CYVAL_HSIOM_IO0_SEL_GPIO
00000000 a CYVAL_HSIOM_IO0_SEL_GPIO
00000001 a CYVAL_HSIOM_IO0_SEL_GPIO_DSI
00000001 a CYVAL_HSIOM_IO0_SEL_GPIO_DSI
0000000c a CYVAL_HSIOM_IO0_SEL_LCD_COM
0000000c a CYVAL_HSIOM_IO0_SEL_LCD_COM
0000000d a CYVAL_HSIOM_IO0_SEL_LCD_SEG
0000000d a CYVAL_HSIOM_IO0_SEL_LCD_SEG
00000003 a CYVAL_LCD_BIAS_FIFTH
00000003 a CYVAL_LCD_BIAS_FIFTH
00000002 a CYVAL_LCD_BIAS_FOURTH
00000002 a CYVAL_LCD_BIAS_FOURTH
00000000 a CYVAL_LCD_BIAS_HALF
00000000 a CYVAL_LCD_BIAS_HALF
00000001 a CYVAL_LCD_BIAS_THIRD
00000001 a CYVAL_LCD_BIAS_THIRD
00000001 a CYVAL_LCD_LCD_MODE_HS
00000001 a CYVAL_LCD_LCD_MODE_HS
00000000 a CYVAL_LCD_LCD_MODE_LS
00000000 a CYVAL_LCD_LCD_MODE_LS
00000001 a CYVAL_LCD_OP_MODE_CORRELATION
00000001 a CYVAL_LCD_OP_MODE_CORRELATION
00000000 a CYVAL_LCD_OP_MODE_PWM
00000000 a CYVAL_LCD_OP_MODE_PWM
00000000 a CYVAL_LCD_TYPE_TYPE_A
00000000 a CYVAL_LCD_TYPE_TYPE_A
00000001 a CYVAL_LCD_TYPE_TYPE_B
00000001 a CYVAL_LCD_TYPE_TYPE_B
00000003 a CYVAL_LPCOMP_INTTYPE1_BOTH
00000003 a CYVAL_LPCOMP_INTTYPE1_BOTH
00000000 a CYVAL_LPCOMP_INTTYPE1_DISABLE
00000000 a CYVAL_LPCOMP_INTTYPE1_DISABLE
00000002 a CYVAL_LPCOMP_INTTYPE1_FALLING
00000002 a CYVAL_LPCOMP_INTTYPE1_FALLING
00000001 a CYVAL_LPCOMP_INTTYPE1_RISING
00000001 a CYVAL_LPCOMP_INTTYPE1_RISING
00000003 a CYVAL_LPCOMP_INTTYPE2_BOTH
00000003 a CYVAL_LPCOMP_INTTYPE2_BOTH
00000000 a CYVAL_LPCOMP_INTTYPE2_DISABLE
00000000 a CYVAL_LPCOMP_INTTYPE2_DISABLE
00000002 a CYVAL_LPCOMP_INTTYPE2_FALLING
00000002 a CYVAL_LPCOMP_INTTYPE2_FALLING
00000001 a CYVAL_LPCOMP_INTTYPE2_RISING
00000001 a CYVAL_LPCOMP_INTTYPE2_RISING
00000001 a CYVAL_LPCOMP_MODE1_FAST
00000001 a CYVAL_LPCOMP_MODE1_FAST
00000000 a CYVAL_LPCOMP_MODE1_SLOW
00000000 a CYVAL_LPCOMP_MODE1_SLOW
00000002 a CYVAL_LPCOMP_MODE1_ULP
00000002 a CYVAL_LPCOMP_MODE1_ULP
00000001 a CYVAL_LPCOMP_MODE2_FAST
00000001 a CYVAL_LPCOMP_MODE2_FAST
00000000 a CYVAL_LPCOMP_MODE2_SLOW
00000000 a CYVAL_LPCOMP_MODE2_SLOW
00000002 a CYVAL_LPCOMP_MODE2_ULP
00000002 a CYVAL_LPCOMP_MODE2_ULP
00000001 a CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED
00000001 a CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED
00000000 a CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED
00000000 a CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED
00000001 a CYVAL_SAR_ICONT_LV_HALF_PWR
00000001 a CYVAL_SAR_ICONT_LV_HALF_PWR
00000002 a CYVAL_SAR_ICONT_LV_MORE_PWR
00000002 a CYVAL_SAR_ICONT_LV_MORE_PWR
00000000 a CYVAL_SAR_ICONT_LV_NORMAL_PWR
00000000 a CYVAL_SAR_ICONT_LV_NORMAL_PWR
00000003 a CYVAL_SAR_ICONT_LV_QUARTER_PWR
00000003 a CYVAL_SAR_ICONT_LV_QUARTER_PWR
00000006 a CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT
00000006 a CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT
00000001 a CYVAL_SAR_INJ_PORT_ADDR_CTB0
00000001 a CYVAL_SAR_INJ_PORT_ADDR_CTB0
00000002 a CYVAL_SAR_INJ_PORT_ADDR_CTB1
00000002 a CYVAL_SAR_INJ_PORT_ADDR_CTB1
00000003 a CYVAL_SAR_INJ_PORT_ADDR_CTB2
00000003 a CYVAL_SAR_INJ_PORT_ADDR_CTB2
00000004 a CYVAL_SAR_INJ_PORT_ADDR_CTB3
00000004 a CYVAL_SAR_INJ_PORT_ADDR_CTB3
00000000 a CYVAL_SAR_INJ_PORT_ADDR_SARMUX
00000000 a CYVAL_SAR_INJ_PORT_ADDR_SARMUX
00000007 a CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT
00000007 a CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT
00000000 a CYVAL_SAR_INJ_RESOLUTION_12B
00000000 a CYVAL_SAR_INJ_RESOLUTION_12B
00000001 a CYVAL_SAR_INJ_RESOLUTION_SUBRES
00000001 a CYVAL_SAR_INJ_RESOLUTION_SUBRES
00000006 a CYVAL_SAR_NEG_SEL_ACORE
00000006 a CYVAL_SAR_NEG_SEL_ACORE
00000001 a CYVAL_SAR_NEG_SEL_ART_VSSA
00000001 a CYVAL_SAR_NEG_SEL_ART_VSSA
00000002 a CYVAL_SAR_NEG_SEL_P1
00000002 a CYVAL_SAR_NEG_SEL_P1
00000003 a CYVAL_SAR_NEG_SEL_P3
00000003 a CYVAL_SAR_NEG_SEL_P3
00000004 a CYVAL_SAR_NEG_SEL_P5
00000004 a CYVAL_SAR_NEG_SEL_P5
00000005 a CYVAL_SAR_NEG_SEL_P7
00000005 a CYVAL_SAR_NEG_SEL_P7
00000007 a CYVAL_SAR_NEG_SEL_VREF
00000007 a CYVAL_SAR_NEG_SEL_VREF
00000000 a CYVAL_SAR_NEG_SEL_VSSA_KELVIN
00000000 a CYVAL_SAR_NEG_SEL_VSSA_KELVIN
00000006 a CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1
00000006 a CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1
00000005 a CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2
00000005 a CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2
00000001 a CYVAL_SAR_PORT_ADDR_CTB0
00000001 a CYVAL_SAR_PORT_ADDR_CTB0
00000002 a CYVAL_SAR_PORT_ADDR_CTB1
00000002 a CYVAL_SAR_PORT_ADDR_CTB1
00000003 a CYVAL_SAR_PORT_ADDR_CTB2
00000003 a CYVAL_SAR_PORT_ADDR_CTB2
00000004 a CYVAL_SAR_PORT_ADDR_CTB3
00000004 a CYVAL_SAR_PORT_ADDR_CTB3
00000000 a CYVAL_SAR_PORT_ADDR_SARMUX
00000000 a CYVAL_SAR_PORT_ADDR_SARMUX
00000007 a CYVAL_SAR_PORT_ADDR_SARMUX_VIRT
00000007 a CYVAL_SAR_PORT_ADDR_SARMUX_VIRT
00000001 a CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR
00000001 a CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR
00000000 a CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR
00000000 a CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR
00000003 a CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR
00000003 a CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR
00000002 a CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR
00000002 a CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR
00000002 a CYVAL_SAR_RANGE_COND_ABOVE
00000002 a CYVAL_SAR_RANGE_COND_ABOVE
00000000 a CYVAL_SAR_RANGE_COND_BELOW
00000000 a CYVAL_SAR_RANGE_COND_BELOW
00000001 a CYVAL_SAR_RANGE_COND_INSIDE
00000001 a CYVAL_SAR_RANGE_COND_INSIDE
00000003 a CYVAL_SAR_RANGE_COND_OUTSIDE
00000003 a CYVAL_SAR_RANGE_COND_OUTSIDE
00000000 a CYVAL_SAR_RESOLUTION_MAXRES
00000000 a CYVAL_SAR_RESOLUTION_MAXRES
00000001 a CYVAL_SAR_RESOLUTION_SUBRES
00000001 a CYVAL_SAR_RESOLUTION_SUBRES
00000001 a CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED
00000001 a CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED
00000000 a CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED
00000000 a CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED
00000001 a CYVAL_SAR_SUB_RESOLUTION_10B
00000001 a CYVAL_SAR_SUB_RESOLUTION_10B
00000000 a CYVAL_SAR_SUB_RESOLUTION_8B
00000000 a CYVAL_SAR_SUB_RESOLUTION_8B
00000004 a CYVAL_SAR_VREF_SEL_VBGR
00000004 a CYVAL_SAR_VREF_SEL_VBGR
00000007 a CYVAL_SAR_VREF_SEL_VDDA
00000007 a CYVAL_SAR_VREF_SEL_VDDA
00000006 a CYVAL_SAR_VREF_SEL_VDDA_DIV_2
00000006 a CYVAL_SAR_VREF_SEL_VDDA_DIV_2
00000003 a CYVAL_SAR_VREF_SEL_VREF_AROUTE
00000003 a CYVAL_SAR_VREF_SEL_VREF_AROUTE
00000005 a CYVAL_SAR_VREF_SEL_VREF_EXT
00000005 a CYVAL_SAR_VREF_SEL_VREF_EXT
00000000 a CYVAL_SAR_VREF_SEL_VREF0
00000000 a CYVAL_SAR_VREF_SEL_VREF0
00000001 a CYVAL_SAR_VREF_SEL_VREF1
00000001 a CYVAL_SAR_VREF_SEL_VREF1
00000002 a CYVAL_SAR_VREF_SEL_VREF2
00000002 a CYVAL_SAR_VREF_SEL_VREF2
00000001 a CYVAL_SAR_WOUND_RESOLUTION_10BIT
00000001 a CYVAL_SAR_WOUND_RESOLUTION_10BIT
00000000 a CYVAL_SAR_WOUND_RESOLUTION_12BIT
00000000 a CYVAL_SAR_WOUND_RESOLUTION_12BIT
00000002 a CYVAL_SAR_WOUND_RESOLUTION_8BIT
00000002 a CYVAL_SAR_WOUND_RESOLUTION_8BIT
00000003 a CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO
00000003 a CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO
00000000 a CYVAL_SCB_MODE_I2C
00000000 a CYVAL_SCB_MODE_I2C
00000001 a CYVAL_SCB_MODE_SPI
00000001 a CYVAL_SCB_MODE_SPI
00000002 a CYVAL_SCB_MODE_UART
00000002 a CYVAL_SCB_MODE_UART
00000003 a CYVAL_SFLASH_PROT_LEVEL_KILL
00000003 a CYVAL_SFLASH_PROT_LEVEL_KILL
00000000 a CYVAL_SFLASH_PROT_LEVEL_OPEN
00000000 a CYVAL_SFLASH_PROT_LEVEL_OPEN
00000002 a CYVAL_SFLASH_PROT_LEVEL_PROTECTED
00000002 a CYVAL_SFLASH_PROT_LEVEL_PROTECTED
00000001 a CYVAL_SFLASH_PROT_LEVEL_VIRGIN
00000001 a CYVAL_SFLASH_PROT_LEVEL_VIRGIN
00000002 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES
00000002 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES
00000001 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE
00000001 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE
00000003 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET
00000003 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET
00000000 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE
00000000 a CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE
00000001 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR
00000001 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR
00000002 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT
00000002 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT
00000003 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE
00000003 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE
00000000 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET
00000000 a CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET
00000002 a CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES
00000002 a CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES
00000001 a CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE
00000001 a CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE
00000003 a CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET
00000003 a CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET
00000000 a CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE
00000000 a CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE
00000000 a CYVAL_TCPWM_CNT_GENERIC_DIVBY1
00000000 a CYVAL_TCPWM_CNT_GENERIC_DIVBY1
00000007 a CYVAL_TCPWM_CNT_GENERIC_DIVBY128
00000007 a CYVAL_TCPWM_CNT_GENERIC_DIVBY128
00000004 a CYVAL_TCPWM_CNT_GENERIC_DIVBY16
00000004 a CYVAL_TCPWM_CNT_GENERIC_DIVBY16
00000001 a CYVAL_TCPWM_CNT_GENERIC_DIVBY2
00000001 a CYVAL_TCPWM_CNT_GENERIC_DIVBY2
00000005 a CYVAL_TCPWM_CNT_GENERIC_DIVBY32
00000005 a CYVAL_TCPWM_CNT_GENERIC_DIVBY32
00000002 a CYVAL_TCPWM_CNT_GENERIC_DIVBY4
00000002 a CYVAL_TCPWM_CNT_GENERIC_DIVBY4
00000006 a CYVAL_TCPWM_CNT_GENERIC_DIVBY64
00000006 a CYVAL_TCPWM_CNT_GENERIC_DIVBY64
00000003 a CYVAL_TCPWM_CNT_GENERIC_DIVBY8
00000003 a CYVAL_TCPWM_CNT_GENERIC_DIVBY8
00000002 a CYVAL_TCPWM_CNT_MODE_CAPTURE
00000002 a CYVAL_TCPWM_CNT_MODE_CAPTURE
00000004 a CYVAL_TCPWM_CNT_MODE_PWM
00000004 a CYVAL_TCPWM_CNT_MODE_PWM
00000005 a CYVAL_TCPWM_CNT_MODE_PWM_DT
00000005 a CYVAL_TCPWM_CNT_MODE_PWM_DT
00000006 a CYVAL_TCPWM_CNT_MODE_PWM_PR
00000006 a CYVAL_TCPWM_CNT_MODE_PWM_PR
00000003 a CYVAL_TCPWM_CNT_MODE_QUAD
00000003 a CYVAL_TCPWM_CNT_MODE_QUAD
00000000 a CYVAL_TCPWM_CNT_MODE_TIMER
00000000 a CYVAL_TCPWM_CNT_MODE_TIMER
00000001 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR
00000001 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR
00000002 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT
00000002 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT
00000003 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE
00000003 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE
00000000 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET
00000000 a CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET
00000002 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT
00000002 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT
00000001 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT
00000001 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT
00000000 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1
00000000 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1
00000001 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2
00000001 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2
00000002 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4
00000002 a CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4
00000002 a CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES
00000002 a CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES
00000001 a CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE
00000001 a CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE
00000003 a CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET
00000003 a CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET
00000000 a CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE
00000000 a CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE
00000002 a CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES
00000002 a CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES
00000001 a CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE
00000001 a CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE
00000003 a CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET
00000003 a CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET
00000000 a CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE
00000000 a CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE
00000002 a CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES
00000002 a CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES
00000001 a CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE
00000001 a CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE
00000003 a CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET
00000003 a CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET
00000000 a CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE
00000000 a CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE
00000001 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR
00000001 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR
00000002 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT
00000002 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT
00000003 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE
00000003 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE
00000000 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET
00000000 a CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET
00000001 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN
00000001 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN
00000000 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP
00000000 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP
00000002 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1
00000002 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1
00000003 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2
00000003 a CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2
00000001 a CYVAL_TST_ADFT_MUX_SEL_0A_IN1
00000001 a CYVAL_TST_ADFT_MUX_SEL_0A_IN1
00000002 a CYVAL_TST_ADFT_MUX_SEL_0A_IN2
00000002 a CYVAL_TST_ADFT_MUX_SEL_0A_IN2
00000003 a CYVAL_TST_ADFT_MUX_SEL_0A_IN3
00000003 a CYVAL_TST_ADFT_MUX_SEL_0A_IN3
00000004 a CYVAL_TST_ADFT_MUX_SEL_0A_IN4
00000004 a CYVAL_TST_ADFT_MUX_SEL_0A_IN4
00000005 a CYVAL_TST_ADFT_MUX_SEL_0A_IN5
00000005 a CYVAL_TST_ADFT_MUX_SEL_0A_IN5
00000006 a CYVAL_TST_ADFT_MUX_SEL_0A_IN6
00000006 a CYVAL_TST_ADFT_MUX_SEL_0A_IN6
00000000 a CYVAL_TST_ADFT_MUX_SEL_0A_NC0
00000000 a CYVAL_TST_ADFT_MUX_SEL_0A_NC0
00000007 a CYVAL_TST_ADFT_MUX_SEL_0A_NC7
00000007 a CYVAL_TST_ADFT_MUX_SEL_0A_NC7
00000000 a CYVAL_UDB_BCTL0_BCEN_DISABLE
00000000 a CYVAL_UDB_BCTL0_BCEN_DISABLE
00000001 a CYVAL_UDB_BCTL0_BCEN_ENABLE
00000001 a CYVAL_UDB_BCTL0_BCEN_ENABLE
00000000 a CYVAL_UDB_BCTL0_BCEN_Q_DISABLE
00000000 a CYVAL_UDB_BCTL0_BCEN_Q_DISABLE
00000001 a CYVAL_UDB_BCTL0_BCEN_Q_ENABLE
00000001 a CYVAL_UDB_BCTL0_BCEN_Q_ENABLE
00000002 a CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT
00000002 a CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES
00000000 a CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES
00000001 a CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT
00000001 a CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT
00000003 a CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT
00000000 a CYVAL_UDB_BCTL0_DCEN_DISABLE
00000000 a CYVAL_UDB_BCTL0_DCEN_DISABLE
00000001 a CYVAL_UDB_BCTL0_DCEN_ENABLE
00000001 a CYVAL_UDB_BCTL0_DCEN_ENABLE
00000000 a CYVAL_UDB_BCTL0_DCEN_Q_DISABLE
00000000 a CYVAL_UDB_BCTL0_DCEN_Q_DISABLE
00000001 a CYVAL_UDB_BCTL0_DCEN_Q_ENABLE
00000001 a CYVAL_UDB_BCTL0_DCEN_Q_ENABLE
00000000 a CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE
00000000 a CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE
00000001 a CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE
00000001 a CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE
00000000 a CYVAL_UDB_BCTL0_DRV_DISABLE
00000000 a CYVAL_UDB_BCTL0_DRV_DISABLE
00000001 a CYVAL_UDB_BCTL0_DRV_ENABLE
00000001 a CYVAL_UDB_BCTL0_DRV_ENABLE
00000000 a CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE
00000000 a CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE
00000001 a CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE
00000001 a CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE
00000000 a CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE
00000000 a CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE
00000001 a CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE
00000001 a CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE
00000000 a CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE
00000000 a CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE
00000001 a CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE
00000001 a CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE
00000000 a CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE
00000000 a CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE
00000001 a CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE
00000001 a CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE
00000000 a CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB
00000000 a CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB
00000001 a CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB
00000001 a CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB
00000000 a CYVAL_UDB_CAT16_CNT_START_DISABLE
00000000 a CYVAL_UDB_CAT16_CNT_START_DISABLE
00000001 a CYVAL_UDB_CAT16_CNT_START_ENABLE
00000001 a CYVAL_UDB_CAT16_CNT_START_ENABLE
00000001 a CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR
00000001 a CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR
00000000 a CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL
00000000 a CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL
00000001 a CYVAL_UDB_CAT16_FIFO0_LVL_MID
00000001 a CYVAL_UDB_CAT16_FIFO0_LVL_MID
00000000 a CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL
00000000 a CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL
00000001 a CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR
00000001 a CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR
00000000 a CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL
00000000 a CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL
00000001 a CYVAL_UDB_CAT16_FIFO1_LVL_MID
00000001 a CYVAL_UDB_CAT16_FIFO1_LVL_MID
00000000 a CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL
00000000 a CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL
00000000 a CYVAL_UDB_CAT16_INT_EN_DISABLE
00000000 a CYVAL_UDB_CAT16_INT_EN_DISABLE
00000001 a CYVAL_UDB_CAT16_INT_EN_ENABLE
00000001 a CYVAL_UDB_CAT16_INT_EN_ENABLE
00000000 a CYVAL_UDB_INT_MODE_CFG_LEVEL
00000000 a CYVAL_UDB_INT_MODE_CFG_LEVEL
00000001 a CYVAL_UDB_INT_MODE_CFG_PULSE
00000001 a CYVAL_UDB_INT_MODE_CFG_PULSE
00000001 a CYVAL_UDB_P_U_A0_WR_SRC_ALU
00000001 a CYVAL_UDB_P_U_A0_WR_SRC_ALU
00000002 a CYVAL_UDB_P_U_A0_WR_SRC_D0
00000002 a CYVAL_UDB_P_U_A0_WR_SRC_D0
00000003 a CYVAL_UDB_P_U_A0_WR_SRC_F0
00000003 a CYVAL_UDB_P_U_A0_WR_SRC_F0
00000000 a CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE
00000000 a CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE
00000001 a CYVAL_UDB_P_U_A1_WR_SRC_ALU
00000001 a CYVAL_UDB_P_U_A1_WR_SRC_ALU
00000002 a CYVAL_UDB_P_U_A1_WR_SRC_D1
00000002 a CYVAL_UDB_P_U_A1_WR_SRC_D1
00000003 a CYVAL_UDB_P_U_A1_WR_SRC_F1
00000003 a CYVAL_UDB_P_U_A1_WR_SRC_F1
00000000 a CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE
00000000 a CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE
00000001 a CYVAL_UDB_P_U_ALT_CNT_ALT_MODE
00000001 a CYVAL_UDB_P_U_ALT_CNT_ALT_MODE
00000000 a CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE
00000000 a CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE
00000001 a CYVAL_UDB_P_U_ALT_RES_ALTERNATE
00000001 a CYVAL_UDB_P_U_ALT_RES_ALTERNATE
00000000 a CYVAL_UDB_P_U_ALT_RES_COMPATIBLE
00000000 a CYVAL_UDB_P_U_ALT_RES_COMPATIBLE
00000000 a CYVAL_UDB_P_U_AMASK_EN_DISABLE
00000000 a CYVAL_UDB_P_U_AMASK_EN_DISABLE
00000001 a CYVAL_UDB_P_U_AMASK_EN_ENABLE
00000001 a CYVAL_UDB_P_U_AMASK_EN_ENABLE
00000000 a CYVAL_UDB_P_U_CFB_EN_DISABLE
00000000 a CYVAL_UDB_P_U_CFB_EN_DISABLE
00000001 a CYVAL_UDB_P_U_CFB_EN_ENABLE
00000001 a CYVAL_UDB_P_U_CFB_EN_ENABLE
00000000 a CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE
00000000 a CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE
00000001 a CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE
00000001 a CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE
00000000 a CYVAL_UDB_P_U_CHAIN_FB_DISABLE
00000000 a CYVAL_UDB_P_U_CHAIN_FB_DISABLE
00000001 a CYVAL_UDB_P_U_CHAIN_FB_ENABLE
00000001 a CYVAL_UDB_P_U_CHAIN_FB_ENABLE
00000000 a CYVAL_UDB_P_U_CHAIN0_DISABLE
00000000 a CYVAL_UDB_P_U_CHAIN0_DISABLE
00000001 a CYVAL_UDB_P_U_CHAIN0_ENABLE
00000001 a CYVAL_UDB_P_U_CHAIN0_ENABLE
00000000 a CYVAL_UDB_P_U_CHAIN1_DISABLE
00000000 a CYVAL_UDB_P_U_CHAIN1_DISABLE
00000001 a CYVAL_UDB_P_U_CHAIN1_ENABLE
00000001 a CYVAL_UDB_P_U_CHAIN1_ENABLE
00000001 a CYVAL_UDB_P_U_CI_MUX_DP_IN0
00000001 a CYVAL_UDB_P_U_CI_MUX_DP_IN0
00000002 a CYVAL_UDB_P_U_CI_MUX_DP_IN1
00000002 a CYVAL_UDB_P_U_CI_MUX_DP_IN1
00000003 a CYVAL_UDB_P_U_CI_MUX_DP_IN2
00000003 a CYVAL_UDB_P_U_CI_MUX_DP_IN2
00000004 a CYVAL_UDB_P_U_CI_MUX_DP_IN3
00000004 a CYVAL_UDB_P_U_CI_MUX_DP_IN3
00000005 a CYVAL_UDB_P_U_CI_MUX_DP_IN4
00000005 a CYVAL_UDB_P_U_CI_MUX_DP_IN4
00000006 a CYVAL_UDB_P_U_CI_MUX_DP_IN5
00000006 a CYVAL_UDB_P_U_CI_MUX_DP_IN5
00000000 a CYVAL_UDB_P_U_CI_MUX_OFF
00000000 a CYVAL_UDB_P_U_CI_MUX_OFF
00000007 a CYVAL_UDB_P_U_CI_MUX_RESERVED
00000007 a CYVAL_UDB_P_U_CI_MUX_RESERVED
00000000 a CYVAL_UDB_P_U_CI_SEL_CFG_A
00000000 a CYVAL_UDB_P_U_CI_SEL_CFG_A
00000001 a CYVAL_UDB_P_U_CI_SEL_CFG_B
00000001 a CYVAL_UDB_P_U_CI_SEL_CFG_B
00000003 a CYVAL_UDB_P_U_CI_SELA_CHAIN
00000003 a CYVAL_UDB_P_U_CI_SELA_CHAIN
00000000 a CYVAL_UDB_P_U_CI_SELA_DEFAULT
00000000 a CYVAL_UDB_P_U_CI_SELA_DEFAULT
00000001 a CYVAL_UDB_P_U_CI_SELA_REGISTERED
00000001 a CYVAL_UDB_P_U_CI_SELA_REGISTERED
00000002 a CYVAL_UDB_P_U_CI_SELA_ROUTE
00000002 a CYVAL_UDB_P_U_CI_SELA_ROUTE
00000003 a CYVAL_UDB_P_U_CI_SELB_CHAIN
00000003 a CYVAL_UDB_P_U_CI_SELB_CHAIN
00000000 a CYVAL_UDB_P_U_CI_SELB_DEFAULT
00000000 a CYVAL_UDB_P_U_CI_SELB_DEFAULT
00000001 a CYVAL_UDB_P_U_CI_SELB_REGISTERED
00000001 a CYVAL_UDB_P_U_CI_SELB_REGISTERED
00000002 a CYVAL_UDB_P_U_CI_SELB_ROUTE
00000002 a CYVAL_UDB_P_U_CI_SELB_ROUTE
00000000 a CYVAL_UDB_P_U_CMASK0_EN_DISABLE
00000000 a CYVAL_UDB_P_U_CMASK0_EN_DISABLE
00000001 a CYVAL_UDB_P_U_CMASK0_EN_ENABLE
00000001 a CYVAL_UDB_P_U_CMASK0_EN_ENABLE
00000000 a CYVAL_UDB_P_U_CMASK1_EN_DISABLE
00000000 a CYVAL_UDB_P_U_CMASK1_EN_DISABLE
00000001 a CYVAL_UDB_P_U_CMASK1_EN_ENABLE
00000001 a CYVAL_UDB_P_U_CMASK1_EN_ENABLE
00000000 a CYVAL_UDB_P_U_CMP_SEL_CFG_A
00000000 a CYVAL_UDB_P_U_CMP_SEL_CFG_A
00000001 a CYVAL_UDB_P_U_CMP_SEL_CFG_B
00000001 a CYVAL_UDB_P_U_CMP_SEL_CFG_B
00000003 a CYVAL_UDB_P_U_CMP_SELA_A0_A0
00000003 a CYVAL_UDB_P_U_CMP_SELA_A0_A0
00000002 a CYVAL_UDB_P_U_CMP_SELA_A0_D1
00000002 a CYVAL_UDB_P_U_CMP_SELA_A0_D1
00000001 a CYVAL_UDB_P_U_CMP_SELA_A1_A0
00000001 a CYVAL_UDB_P_U_CMP_SELA_A1_A0
00000000 a CYVAL_UDB_P_U_CMP_SELA_A1_D1
00000000 a CYVAL_UDB_P_U_CMP_SELA_A1_D1
00000003 a CYVAL_UDB_P_U_CMP_SELB_A0_A0
00000003 a CYVAL_UDB_P_U_CMP_SELB_A0_A0
00000002 a CYVAL_UDB_P_U_CMP_SELB_A0_D1
00000002 a CYVAL_UDB_P_U_CMP_SELB_A0_D1
00000001 a CYVAL_UDB_P_U_CMP_SELB_A1_A0
00000001 a CYVAL_UDB_P_U_CMP_SELB_A1_A0
00000000 a CYVAL_UDB_P_U_CMP_SELB_A1_D1
00000000 a CYVAL_UDB_P_U_CMP_SELB_A1_D1
00000000 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4
00000000 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4
00000001 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5
00000001 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5
00000002 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6
00000002 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6
00000003 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO
00000003 a CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO
00000000 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0
00000000 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0
00000001 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1
00000001 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1
00000002 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2
00000002 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2
00000003 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3
00000003 a CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3
00000000 a CYVAL_UDB_P_U_CTL_MD0_DIRECT
00000000 a CYVAL_UDB_P_U_CTL_MD0_DIRECT
00000002 a CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC
00000002 a CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC
00000003 a CYVAL_UDB_P_U_CTL_MD0_PULSE
00000003 a CYVAL_UDB_P_U_CTL_MD0_PULSE
00000001 a CYVAL_UDB_P_U_CTL_MD0_SYNC
00000001 a CYVAL_UDB_P_U_CTL_MD0_SYNC
00000000 a CYVAL_UDB_P_U_CTL_MD1_DIRECT
00000000 a CYVAL_UDB_P_U_CTL_MD1_DIRECT
00000002 a CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC
00000002 a CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC
00000003 a CYVAL_UDB_P_U_CTL_MD1_PULSE
00000003 a CYVAL_UDB_P_U_CTL_MD1_PULSE
00000001 a CYVAL_UDB_P_U_CTL_MD1_SYNC
00000001 a CYVAL_UDB_P_U_CTL_MD1_SYNC
00000001 a CYVAL_UDB_P_U_D0_LD_DP_IN0
00000001 a CYVAL_UDB_P_U_D0_LD_DP_IN0
00000002 a CYVAL_UDB_P_U_D0_LD_DP_IN1
00000002 a CYVAL_UDB_P_U_D0_LD_DP_IN1
00000003 a CYVAL_UDB_P_U_D0_LD_DP_IN2
00000003 a CYVAL_UDB_P_U_D0_LD_DP_IN2
00000004 a CYVAL_UDB_P_U_D0_LD_DP_IN3
00000004 a CYVAL_UDB_P_U_D0_LD_DP_IN3
00000005 a CYVAL_UDB_P_U_D0_LD_DP_IN4
00000005 a CYVAL_UDB_P_U_D0_LD_DP_IN4
00000006 a CYVAL_UDB_P_U_D0_LD_DP_IN5
00000006 a CYVAL_UDB_P_U_D0_LD_DP_IN5
00000000 a CYVAL_UDB_P_U_D0_LD_OFF
00000000 a CYVAL_UDB_P_U_D0_LD_OFF
00000007 a CYVAL_UDB_P_U_D0_LD_RESERVED
00000007 a CYVAL_UDB_P_U_D0_LD_RESERVED
00000001 a CYVAL_UDB_P_U_D1_LD_DP_IN0
00000001 a CYVAL_UDB_P_U_D1_LD_DP_IN0
00000002 a CYVAL_UDB_P_U_D1_LD_DP_IN1
00000002 a CYVAL_UDB_P_U_D1_LD_DP_IN1
00000003 a CYVAL_UDB_P_U_D1_LD_DP_IN2
00000003 a CYVAL_UDB_P_U_D1_LD_DP_IN2
00000004 a CYVAL_UDB_P_U_D1_LD_DP_IN3
00000004 a CYVAL_UDB_P_U_D1_LD_DP_IN3
00000005 a CYVAL_UDB_P_U_D1_LD_DP_IN4
00000005 a CYVAL_UDB_P_U_D1_LD_DP_IN4
00000006 a CYVAL_UDB_P_U_D1_LD_DP_IN5
00000006 a CYVAL_UDB_P_U_D1_LD_DP_IN5
00000000 a CYVAL_UDB_P_U_D1_LD_OFF
00000000 a CYVAL_UDB_P_U_D1_LD_OFF
00000007 a CYVAL_UDB_P_U_D1_LD_RESERVED
00000007 a CYVAL_UDB_P_U_D1_LD_RESERVED
00000000 a CYVAL_UDB_P_U_DEF_SI_DEFAULT_0
00000000 a CYVAL_UDB_P_U_DEF_SI_DEFAULT_0
00000001 a CYVAL_UDB_P_U_DEF_SI_DEFAULT_1
00000001 a CYVAL_UDB_P_U_DEF_SI_DEFAULT_1
00000008 a CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK
00000008 a CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK
00000000 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK0
00000000 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK0
00000001 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK1
00000001 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK1
00000002 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK2
00000002 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK2
00000003 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK3
00000003 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK3
00000004 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK4
00000004 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK4
00000005 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK5
00000005 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK5
00000006 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK6
00000006 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK6
00000007 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK7
00000007 a CYVAL_UDB_P_U_DP_CK_SEL_GCLK7
00000009 a CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK
00000009 a CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK
00000001 a CYVAL_UDB_P_U_DP_RES_POL_INVERT
00000001 a CYVAL_UDB_P_U_DP_RES_POL_INVERT
00000000 a CYVAL_UDB_P_U_DP_RES_POL_NOINV
00000000 a CYVAL_UDB_P_U_DP_RES_POL_NOINV
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS
00000001 a CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE
00000000 a CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE
00000000 a CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE
00000000 a CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE
00000001 a CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE
00000001 a CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE
00000000 a CYVAL_UDB_P_U_EN_RES_DP_DISABLE
00000000 a CYVAL_UDB_P_U_EN_RES_DP_DISABLE
00000001 a CYVAL_UDB_P_U_EN_RES_DP_ENABLE
00000001 a CYVAL_UDB_P_U_EN_RES_DP_ENABLE
00000001 a CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED
00000001 a CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED
00000000 a CYVAL_UDB_P_U_EN_RES_STAT_NEGATED
00000000 a CYVAL_UDB_P_U_EN_RES_STAT_NEGATED
00000000 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0
00000000 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0
00000001 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1
00000001 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1
00000002 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2
00000002 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2
00000003 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3
00000003 a CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3
00000001 a CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL
00000001 a CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL
00000000 a CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL
00000000 a CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL
00000000 a CYVAL_UDB_P_U_EXT_SYNC_DISABLE
00000000 a CYVAL_UDB_P_U_EXT_SYNC_DISABLE
00000001 a CYVAL_UDB_P_U_EXT_SYNC_ENABLE
00000001 a CYVAL_UDB_P_U_EXT_SYNC_ENABLE
00000001 a CYVAL_UDB_P_U_F0_CK_INV_INVERT
00000001 a CYVAL_UDB_P_U_F0_CK_INV_INVERT
00000000 a CYVAL_UDB_P_U_F0_CK_INV_NORMAL
00000000 a CYVAL_UDB_P_U_F0_CK_INV_NORMAL
00000001 a CYVAL_UDB_P_U_F0_DYN_DYNAMIC
00000001 a CYVAL_UDB_P_U_F0_DYN_DYNAMIC
00000000 a CYVAL_UDB_P_U_F0_DYN_STATIC
00000000 a CYVAL_UDB_P_U_F0_DYN_STATIC
00000000 a CYVAL_UDB_P_U_F0_INSEL_INPUT
00000000 a CYVAL_UDB_P_U_F0_INSEL_INPUT
00000001 a CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0
00000001 a CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0
00000002 a CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1
00000002 a CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1
00000003 a CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU
00000003 a CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU
00000001 a CYVAL_UDB_P_U_F0_LD_DP_IN0
00000001 a CYVAL_UDB_P_U_F0_LD_DP_IN0
00000002 a CYVAL_UDB_P_U_F0_LD_DP_IN1
00000002 a CYVAL_UDB_P_U_F0_LD_DP_IN1
00000003 a CYVAL_UDB_P_U_F0_LD_DP_IN2
00000003 a CYVAL_UDB_P_U_F0_LD_DP_IN2
00000004 a CYVAL_UDB_P_U_F0_LD_DP_IN3
00000004 a CYVAL_UDB_P_U_F0_LD_DP_IN3
00000005 a CYVAL_UDB_P_U_F0_LD_DP_IN4
00000005 a CYVAL_UDB_P_U_F0_LD_DP_IN4
00000006 a CYVAL_UDB_P_U_F0_LD_DP_IN5
00000006 a CYVAL_UDB_P_U_F0_LD_DP_IN5
00000000 a CYVAL_UDB_P_U_F0_LD_OFF
00000000 a CYVAL_UDB_P_U_F0_LD_OFF
00000007 a CYVAL_UDB_P_U_F0_LD_RESERVED
00000007 a CYVAL_UDB_P_U_F0_LD_RESERVED
00000001 a CYVAL_UDB_P_U_F1_CK_INV_INVERT
00000001 a CYVAL_UDB_P_U_F1_CK_INV_INVERT
00000000 a CYVAL_UDB_P_U_F1_CK_INV_NORMAL
00000000 a CYVAL_UDB_P_U_F1_CK_INV_NORMAL
00000001 a CYVAL_UDB_P_U_F1_DYN_DYNAMIC
00000001 a CYVAL_UDB_P_U_F1_DYN_DYNAMIC
00000000 a CYVAL_UDB_P_U_F1_DYN_STATIC
00000000 a CYVAL_UDB_P_U_F1_DYN_STATIC
00000000 a CYVAL_UDB_P_U_F1_INSEL_INPUT
00000000 a CYVAL_UDB_P_U_F1_INSEL_INPUT
00000001 a CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0
00000001 a CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0
00000002 a CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1
00000002 a CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1
00000003 a CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU
00000003 a CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU
00000001 a CYVAL_UDB_P_U_F1_LD_DP_IN0
00000001 a CYVAL_UDB_P_U_F1_LD_DP_IN0
00000002 a CYVAL_UDB_P_U_F1_LD_DP_IN1
00000002 a CYVAL_UDB_P_U_F1_LD_DP_IN1
00000003 a CYVAL_UDB_P_U_F1_LD_DP_IN2
00000003 a CYVAL_UDB_P_U_F1_LD_DP_IN2
00000004 a CYVAL_UDB_P_U_F1_LD_DP_IN3
00000004 a CYVAL_UDB_P_U_F1_LD_DP_IN3
00000005 a CYVAL_UDB_P_U_F1_LD_DP_IN4
00000005 a CYVAL_UDB_P_U_F1_LD_DP_IN4
00000006 a CYVAL_UDB_P_U_F1_LD_DP_IN5
00000006 a CYVAL_UDB_P_U_F1_LD_DP_IN5
00000000 a CYVAL_UDB_P_U_F1_LD_OFF
00000000 a CYVAL_UDB_P_U_F1_LD_OFF
00000007 a CYVAL_UDB_P_U_F1_LD_RESERVED
00000007 a CYVAL_UDB_P_U_F1_LD_RESERVED
00000000 a CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE
00000000 a CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE
00000001 a CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE
00000001 a CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE
00000000 a CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE
00000000 a CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE
00000001 a CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE
00000001 a CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE
00000000 a CYVAL_UDB_P_U_FIFO_CAP_DISABLE
00000000 a CYVAL_UDB_P_U_FIFO_CAP_DISABLE
00000001 a CYVAL_UDB_P_U_FIFO_CAP_ENABLE
00000001 a CYVAL_UDB_P_U_FIFO_CAP_ENABLE
00000001 a CYVAL_UDB_P_U_FIFO_EDGE_EDGE
00000001 a CYVAL_UDB_P_U_FIFO_EDGE_EDGE
00000000 a CYVAL_UDB_P_U_FIFO_EDGE_LEVEL
00000000 a CYVAL_UDB_P_U_FIFO_EDGE_LEVEL
00000000 a CYVAL_UDB_P_U_FIFO_FAST_DISABLE
00000000 a CYVAL_UDB_P_U_FIFO_FAST_DISABLE
00000001 a CYVAL_UDB_P_U_FIFO_FAST_ENABLE
00000001 a CYVAL_UDB_P_U_FIFO_FAST_ENABLE
00000003 a CYVAL_UDB_P_U_FUNC_ADD
00000003 a CYVAL_UDB_P_U_FUNC_ADD
00000006 a CYVAL_UDB_P_U_FUNC_AND
00000006 a CYVAL_UDB_P_U_FUNC_AND
00000002 a CYVAL_UDB_P_U_FUNC_DEC_A
00000002 a CYVAL_UDB_P_U_FUNC_DEC_A
00000001 a CYVAL_UDB_P_U_FUNC_INC_A
00000001 a CYVAL_UDB_P_U_FUNC_INC_A
00000007 a CYVAL_UDB_P_U_FUNC_OR
00000007 a CYVAL_UDB_P_U_FUNC_OR
00000000 a CYVAL_UDB_P_U_FUNC_PASS
00000000 a CYVAL_UDB_P_U_FUNC_PASS
00000004 a CYVAL_UDB_P_U_FUNC_SUB
00000004 a CYVAL_UDB_P_U_FUNC_SUB
00000005 a CYVAL_UDB_P_U_FUNC_XOR
00000005 a CYVAL_UDB_P_U_FUNC_XOR
00000000 a CYVAL_UDB_P_U_GUDB_WR_DISABLE
00000000 a CYVAL_UDB_P_U_GUDB_WR_DISABLE
00000001 a CYVAL_UDB_P_U_GUDB_WR_ENABLE
00000001 a CYVAL_UDB_P_U_GUDB_WR_ENABLE
00000000 a CYVAL_UDB_P_U_MSB_EN_DISABLE
00000000 a CYVAL_UDB_P_U_MSB_EN_DISABLE
00000001 a CYVAL_UDB_P_U_MSB_EN_ENABLE
00000001 a CYVAL_UDB_P_U_MSB_EN_ENABLE
00000000 a CYVAL_UDB_P_U_MSB_SEL_BIT0
00000000 a CYVAL_UDB_P_U_MSB_SEL_BIT0
00000001 a CYVAL_UDB_P_U_MSB_SEL_BIT1
00000001 a CYVAL_UDB_P_U_MSB_SEL_BIT1
00000002 a CYVAL_UDB_P_U_MSB_SEL_BIT2
00000002 a CYVAL_UDB_P_U_MSB_SEL_BIT2
00000003 a CYVAL_UDB_P_U_MSB_SEL_BIT3
00000003 a CYVAL_UDB_P_U_MSB_SEL_BIT3
00000004 a CYVAL_UDB_P_U_MSB_SEL_BIT4
00000004 a CYVAL_UDB_P_U_MSB_SEL_BIT4
00000005 a CYVAL_UDB_P_U_MSB_SEL_BIT5
00000005 a CYVAL_UDB_P_U_MSB_SEL_BIT5
00000006 a CYVAL_UDB_P_U_MSB_SEL_BIT6
00000006 a CYVAL_UDB_P_U_MSB_SEL_BIT6
00000007 a CYVAL_UDB_P_U_MSB_SEL_BIT7
00000007 a CYVAL_UDB_P_U_MSB_SEL_BIT7
00000000 a CYVAL_UDB_P_U_MSB_SI_DEFAULT
00000000 a CYVAL_UDB_P_U_MSB_SI_DEFAULT
00000001 a CYVAL_UDB_P_U_MSB_SI_MSB
00000001 a CYVAL_UDB_P_U_MSB_SI_MSB
00000001 a CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_OUT_SYNC_REGISTERED
00000000 a CYVAL_UDB_P_U_OUT_SYNC_REGISTERED
00000000 a CYVAL_UDB_P_U_OUT0_CE0
00000000 a CYVAL_UDB_P_U_OUT0_CE0
00000004 a CYVAL_UDB_P_U_OUT0_CE1
00000004 a CYVAL_UDB_P_U_OUT0_CE1
00000001 a CYVAL_UDB_P_U_OUT0_CL0
00000001 a CYVAL_UDB_P_U_OUT0_CL0
00000005 a CYVAL_UDB_P_U_OUT0_CL1
00000005 a CYVAL_UDB_P_U_OUT0_CL1
0000000a a CYVAL_UDB_P_U_OUT0_CMSBO
0000000a a CYVAL_UDB_P_U_OUT0_CMSBO
00000009 a CYVAL_UDB_P_U_OUT0_CO_MSB
00000009 a CYVAL_UDB_P_U_OUT0_CO_MSB
0000000c a CYVAL_UDB_P_U_OUT0_F0_BLK_STAT
0000000c a CYVAL_UDB_P_U_OUT0_F0_BLK_STAT
0000000e a CYVAL_UDB_P_U_OUT0_F0_BUS_STAT
0000000e a CYVAL_UDB_P_U_OUT0_F0_BUS_STAT
0000000d a CYVAL_UDB_P_U_OUT0_F1_BLK_STAT
0000000d a CYVAL_UDB_P_U_OUT0_F1_BLK_STAT
0000000f a CYVAL_UDB_P_U_OUT0_F1_BUS_STAT
0000000f a CYVAL_UDB_P_U_OUT0_F1_BUS_STAT
00000003 a CYVAL_UDB_P_U_OUT0_FF0
00000003 a CYVAL_UDB_P_U_OUT0_FF0
00000007 a CYVAL_UDB_P_U_OUT0_FF1
00000007 a CYVAL_UDB_P_U_OUT0_FF1
00000008 a CYVAL_UDB_P_U_OUT0_OV_MSB
00000008 a CYVAL_UDB_P_U_OUT0_OV_MSB
0000000b a CYVAL_UDB_P_U_OUT0_SO
0000000b a CYVAL_UDB_P_U_OUT0_SO
00000002 a CYVAL_UDB_P_U_OUT0_Z0
00000002 a CYVAL_UDB_P_U_OUT0_Z0
00000006 a CYVAL_UDB_P_U_OUT0_Z1
00000006 a CYVAL_UDB_P_U_OUT0_Z1
00000000 a CYVAL_UDB_P_U_OUT1_CE0
00000000 a CYVAL_UDB_P_U_OUT1_CE0
00000004 a CYVAL_UDB_P_U_OUT1_CE1
00000004 a CYVAL_UDB_P_U_OUT1_CE1
00000001 a CYVAL_UDB_P_U_OUT1_CL0
00000001 a CYVAL_UDB_P_U_OUT1_CL0
00000005 a CYVAL_UDB_P_U_OUT1_CL1
00000005 a CYVAL_UDB_P_U_OUT1_CL1
0000000a a CYVAL_UDB_P_U_OUT1_CMSBO
0000000a a CYVAL_UDB_P_U_OUT1_CMSBO
00000009 a CYVAL_UDB_P_U_OUT1_CO_MSB
00000009 a CYVAL_UDB_P_U_OUT1_CO_MSB
0000000c a CYVAL_UDB_P_U_OUT1_F0_BLK_STAT
0000000c a CYVAL_UDB_P_U_OUT1_F0_BLK_STAT
0000000e a CYVAL_UDB_P_U_OUT1_F0_BUS_STAT
0000000e a CYVAL_UDB_P_U_OUT1_F0_BUS_STAT
0000000d a CYVAL_UDB_P_U_OUT1_F1_BLK_STAT
0000000d a CYVAL_UDB_P_U_OUT1_F1_BLK_STAT
0000000f a CYVAL_UDB_P_U_OUT1_F1_BUS_STAT
0000000f a CYVAL_UDB_P_U_OUT1_F1_BUS_STAT
00000003 a CYVAL_UDB_P_U_OUT1_FF0
00000003 a CYVAL_UDB_P_U_OUT1_FF0
00000007 a CYVAL_UDB_P_U_OUT1_FF1
00000007 a CYVAL_UDB_P_U_OUT1_FF1
00000008 a CYVAL_UDB_P_U_OUT1_OV_MSB
00000008 a CYVAL_UDB_P_U_OUT1_OV_MSB
0000000b a CYVAL_UDB_P_U_OUT1_SO
0000000b a CYVAL_UDB_P_U_OUT1_SO
00000002 a CYVAL_UDB_P_U_OUT1_Z0
00000002 a CYVAL_UDB_P_U_OUT1_Z0
00000006 a CYVAL_UDB_P_U_OUT1_Z1
00000006 a CYVAL_UDB_P_U_OUT1_Z1
00000000 a CYVAL_UDB_P_U_OUT2_CE0
00000000 a CYVAL_UDB_P_U_OUT2_CE0
00000004 a CYVAL_UDB_P_U_OUT2_CE1
00000004 a CYVAL_UDB_P_U_OUT2_CE1
00000001 a CYVAL_UDB_P_U_OUT2_CL0
00000001 a CYVAL_UDB_P_U_OUT2_CL0
00000005 a CYVAL_UDB_P_U_OUT2_CL1
00000005 a CYVAL_UDB_P_U_OUT2_CL1
0000000a a CYVAL_UDB_P_U_OUT2_CMSBO
0000000a a CYVAL_UDB_P_U_OUT2_CMSBO
00000009 a CYVAL_UDB_P_U_OUT2_CO_MSB
00000009 a CYVAL_UDB_P_U_OUT2_CO_MSB
0000000c a CYVAL_UDB_P_U_OUT2_F0_BLK_STAT
0000000c a CYVAL_UDB_P_U_OUT2_F0_BLK_STAT
0000000e a CYVAL_UDB_P_U_OUT2_F0_BUS_STAT
0000000e a CYVAL_UDB_P_U_OUT2_F0_BUS_STAT
0000000d a CYVAL_UDB_P_U_OUT2_F1_BLK_STAT
0000000d a CYVAL_UDB_P_U_OUT2_F1_BLK_STAT
0000000f a CYVAL_UDB_P_U_OUT2_F1_BUS_STAT
0000000f a CYVAL_UDB_P_U_OUT2_F1_BUS_STAT
00000003 a CYVAL_UDB_P_U_OUT2_FF0
00000003 a CYVAL_UDB_P_U_OUT2_FF0
00000007 a CYVAL_UDB_P_U_OUT2_FF1
00000007 a CYVAL_UDB_P_U_OUT2_FF1
00000008 a CYVAL_UDB_P_U_OUT2_OV_MSB
00000008 a CYVAL_UDB_P_U_OUT2_OV_MSB
0000000b a CYVAL_UDB_P_U_OUT2_SO
0000000b a CYVAL_UDB_P_U_OUT2_SO
00000002 a CYVAL_UDB_P_U_OUT2_Z0
00000002 a CYVAL_UDB_P_U_OUT2_Z0
00000006 a CYVAL_UDB_P_U_OUT2_Z1
00000006 a CYVAL_UDB_P_U_OUT2_Z1
00000000 a CYVAL_UDB_P_U_OUT3_CE0
00000000 a CYVAL_UDB_P_U_OUT3_CE0
00000004 a CYVAL_UDB_P_U_OUT3_CE1
00000004 a CYVAL_UDB_P_U_OUT3_CE1
00000001 a CYVAL_UDB_P_U_OUT3_CL0
00000001 a CYVAL_UDB_P_U_OUT3_CL0
00000005 a CYVAL_UDB_P_U_OUT3_CL1
00000005 a CYVAL_UDB_P_U_OUT3_CL1
0000000a a CYVAL_UDB_P_U_OUT3_CMSBO
0000000a a CYVAL_UDB_P_U_OUT3_CMSBO
00000009 a CYVAL_UDB_P_U_OUT3_CO_MSB
00000009 a CYVAL_UDB_P_U_OUT3_CO_MSB
0000000c a CYVAL_UDB_P_U_OUT3_F0_BLK_STAT
0000000c a CYVAL_UDB_P_U_OUT3_F0_BLK_STAT
0000000e a CYVAL_UDB_P_U_OUT3_F0_BUS_STAT
0000000e a CYVAL_UDB_P_U_OUT3_F0_BUS_STAT
0000000d a CYVAL_UDB_P_U_OUT3_F1_BLK_STAT
0000000d a CYVAL_UDB_P_U_OUT3_F1_BLK_STAT
0000000f a CYVAL_UDB_P_U_OUT3_F1_BUS_STAT
0000000f a CYVAL_UDB_P_U_OUT3_F1_BUS_STAT
00000003 a CYVAL_UDB_P_U_OUT3_FF0
00000003 a CYVAL_UDB_P_U_OUT3_FF0
00000007 a CYVAL_UDB_P_U_OUT3_FF1
00000007 a CYVAL_UDB_P_U_OUT3_FF1
00000008 a CYVAL_UDB_P_U_OUT3_OV_MSB
00000008 a CYVAL_UDB_P_U_OUT3_OV_MSB
0000000b a CYVAL_UDB_P_U_OUT3_SO
0000000b a CYVAL_UDB_P_U_OUT3_SO
00000002 a CYVAL_UDB_P_U_OUT3_Z0
00000002 a CYVAL_UDB_P_U_OUT3_Z0
00000006 a CYVAL_UDB_P_U_OUT3_Z1
00000006 a CYVAL_UDB_P_U_OUT3_Z1
00000000 a CYVAL_UDB_P_U_OUT4_CE0
00000000 a CYVAL_UDB_P_U_OUT4_CE0
00000004 a CYVAL_UDB_P_U_OUT4_CE1
00000004 a CYVAL_UDB_P_U_OUT4_CE1
00000001 a CYVAL_UDB_P_U_OUT4_CL0
00000001 a CYVAL_UDB_P_U_OUT4_CL0
00000005 a CYVAL_UDB_P_U_OUT4_CL1
00000005 a CYVAL_UDB_P_U_OUT4_CL1
0000000a a CYVAL_UDB_P_U_OUT4_CMSBO
0000000a a CYVAL_UDB_P_U_OUT4_CMSBO
00000009 a CYVAL_UDB_P_U_OUT4_CO_MSB
00000009 a CYVAL_UDB_P_U_OUT4_CO_MSB
0000000c a CYVAL_UDB_P_U_OUT4_F0_BLK_STAT
0000000c a CYVAL_UDB_P_U_OUT4_F0_BLK_STAT
0000000e a CYVAL_UDB_P_U_OUT4_F0_BUS_STAT
0000000e a CYVAL_UDB_P_U_OUT4_F0_BUS_STAT
0000000d a CYVAL_UDB_P_U_OUT4_F1_BLK_STAT
0000000d a CYVAL_UDB_P_U_OUT4_F1_BLK_STAT
0000000f a CYVAL_UDB_P_U_OUT4_F1_BUS_STAT
0000000f a CYVAL_UDB_P_U_OUT4_F1_BUS_STAT
00000003 a CYVAL_UDB_P_U_OUT4_FF0
00000003 a CYVAL_UDB_P_U_OUT4_FF0
00000007 a CYVAL_UDB_P_U_OUT4_FF1
00000007 a CYVAL_UDB_P_U_OUT4_FF1
00000008 a CYVAL_UDB_P_U_OUT4_OV_MSB
00000008 a CYVAL_UDB_P_U_OUT4_OV_MSB
0000000b a CYVAL_UDB_P_U_OUT4_SO
0000000b a CYVAL_UDB_P_U_OUT4_SO
00000002 a CYVAL_UDB_P_U_OUT4_Z0
00000002 a CYVAL_UDB_P_U_OUT4_Z0
00000006 a CYVAL_UDB_P_U_OUT4_Z1
00000006 a CYVAL_UDB_P_U_OUT4_Z1
00000000 a CYVAL_UDB_P_U_OUT5_CE0
00000000 a CYVAL_UDB_P_U_OUT5_CE0
00000004 a CYVAL_UDB_P_U_OUT5_CE1
00000004 a CYVAL_UDB_P_U_OUT5_CE1
00000001 a CYVAL_UDB_P_U_OUT5_CL0
00000001 a CYVAL_UDB_P_U_OUT5_CL0
00000005 a CYVAL_UDB_P_U_OUT5_CL1
00000005 a CYVAL_UDB_P_U_OUT5_CL1
0000000a a CYVAL_UDB_P_U_OUT5_CMSBO
0000000a a CYVAL_UDB_P_U_OUT5_CMSBO
00000009 a CYVAL_UDB_P_U_OUT5_CO_MSB
00000009 a CYVAL_UDB_P_U_OUT5_CO_MSB
0000000c a CYVAL_UDB_P_U_OUT5_F0_BLK_STAT
0000000c a CYVAL_UDB_P_U_OUT5_F0_BLK_STAT
0000000e a CYVAL_UDB_P_U_OUT5_F0_BUS_STAT
0000000e a CYVAL_UDB_P_U_OUT5_F0_BUS_STAT
0000000d a CYVAL_UDB_P_U_OUT5_F1_BLK_STAT
0000000d a CYVAL_UDB_P_U_OUT5_F1_BLK_STAT
0000000f a CYVAL_UDB_P_U_OUT5_F1_BUS_STAT
0000000f a CYVAL_UDB_P_U_OUT5_F1_BUS_STAT
00000003 a CYVAL_UDB_P_U_OUT5_FF0
00000003 a CYVAL_UDB_P_U_OUT5_FF0
00000007 a CYVAL_UDB_P_U_OUT5_FF1
00000007 a CYVAL_UDB_P_U_OUT5_FF1
00000008 a CYVAL_UDB_P_U_OUT5_OV_MSB
00000008 a CYVAL_UDB_P_U_OUT5_OV_MSB
0000000b a CYVAL_UDB_P_U_OUT5_SO
0000000b a CYVAL_UDB_P_U_OUT5_SO
00000002 a CYVAL_UDB_P_U_OUT5_Z0
00000002 a CYVAL_UDB_P_U_OUT5_Z0
00000006 a CYVAL_UDB_P_U_OUT5_Z1
00000006 a CYVAL_UDB_P_U_OUT5_Z1
00000000 a CYVAL_UDB_P_U_PI_DYN_DISABLE
00000000 a CYVAL_UDB_P_U_PI_DYN_DISABLE
00000001 a CYVAL_UDB_P_U_PI_DYN_ENABLE
00000001 a CYVAL_UDB_P_U_PI_DYN_ENABLE
00000000 a CYVAL_UDB_P_U_PI_SEL_NORMAL
00000000 a CYVAL_UDB_P_U_PI_SEL_NORMAL
00000001 a CYVAL_UDB_P_U_PI_SEL_PARALLEL
00000001 a CYVAL_UDB_P_U_PI_SEL_PARALLEL
00000008 a CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK
00000008 a CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK
00000000 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0
00000000 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0
00000001 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1
00000001 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1
00000002 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2
00000002 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2
00000003 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3
00000003 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3
00000004 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4
00000004 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4
00000005 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5
00000005 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5
00000006 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6
00000006 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6
00000007 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7
00000007 a CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7
00000009 a CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK
00000009 a CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK
00000001 a CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD0_RES_POL_INVERT
00000001 a CYVAL_UDB_P_U_PLD0_RES_POL_INVERT
00000000 a CYVAL_UDB_P_U_PLD0_RES_POL_NOINV
00000000 a CYVAL_UDB_P_U_PLD0_RES_POL_NOINV
00000008 a CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK
00000008 a CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK
00000000 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0
00000000 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0
00000001 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1
00000001 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1
00000002 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2
00000002 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2
00000003 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3
00000003 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3
00000004 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4
00000004 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4
00000005 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5
00000005 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5
00000006 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6
00000006 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6
00000007 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7
00000007 a CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7
00000009 a CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK
00000009 a CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK
00000001 a CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL
00000001 a CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL
00000000 a CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER
00000000 a CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED
00000001 a CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED
00000000 a CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE
00000000 a CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE
00000001 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY
00000001 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY
00000000 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF
00000000 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF
00000002 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H
00000002 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H
00000003 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L
00000003 a CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L
00000001 a CYVAL_UDB_P_U_PLD1_RES_POL_INVERT
00000001 a CYVAL_UDB_P_U_PLD1_RES_POL_INVERT
00000000 a CYVAL_UDB_P_U_PLD1_RES_POL_NOINV
00000000 a CYVAL_UDB_P_U_PLD1_RES_POL_NOINV
00000001 a CYVAL_UDB_P_U_RAD0_DP_IN0
00000001 a CYVAL_UDB_P_U_RAD0_DP_IN0
00000002 a CYVAL_UDB_P_U_RAD0_DP_IN1
00000002 a CYVAL_UDB_P_U_RAD0_DP_IN1
00000003 a CYVAL_UDB_P_U_RAD0_DP_IN2
00000003 a CYVAL_UDB_P_U_RAD0_DP_IN2
00000004 a CYVAL_UDB_P_U_RAD0_DP_IN3
00000004 a CYVAL_UDB_P_U_RAD0_DP_IN3
00000005 a CYVAL_UDB_P_U_RAD0_DP_IN4
00000005 a CYVAL_UDB_P_U_RAD0_DP_IN4
00000006 a CYVAL_UDB_P_U_RAD0_DP_IN5
00000006 a CYVAL_UDB_P_U_RAD0_DP_IN5
00000000 a CYVAL_UDB_P_U_RAD0_OFF
00000000 a CYVAL_UDB_P_U_RAD0_OFF
00000007 a CYVAL_UDB_P_U_RAD0_RESERVED
00000007 a CYVAL_UDB_P_U_RAD0_RESERVED
00000001 a CYVAL_UDB_P_U_RAD1_DP_IN0
00000001 a CYVAL_UDB_P_U_RAD1_DP_IN0
00000002 a CYVAL_UDB_P_U_RAD1_DP_IN1
00000002 a CYVAL_UDB_P_U_RAD1_DP_IN1
00000003 a CYVAL_UDB_P_U_RAD1_DP_IN2
00000003 a CYVAL_UDB_P_U_RAD1_DP_IN2
00000004 a CYVAL_UDB_P_U_RAD1_DP_IN3
00000004 a CYVAL_UDB_P_U_RAD1_DP_IN3
00000005 a CYVAL_UDB_P_U_RAD1_DP_IN4
00000005 a CYVAL_UDB_P_U_RAD1_DP_IN4
00000006 a CYVAL_UDB_P_U_RAD1_DP_IN5
00000006 a CYVAL_UDB_P_U_RAD1_DP_IN5
00000000 a CYVAL_UDB_P_U_RAD1_OFF
00000000 a CYVAL_UDB_P_U_RAD1_OFF
00000007 a CYVAL_UDB_P_U_RAD1_RESERVED
00000007 a CYVAL_UDB_P_U_RAD1_RESERVED
00000001 a CYVAL_UDB_P_U_RAD2_DP_IN0
00000001 a CYVAL_UDB_P_U_RAD2_DP_IN0
00000002 a CYVAL_UDB_P_U_RAD2_DP_IN1
00000002 a CYVAL_UDB_P_U_RAD2_DP_IN1
00000003 a CYVAL_UDB_P_U_RAD2_DP_IN2
00000003 a CYVAL_UDB_P_U_RAD2_DP_IN2
00000004 a CYVAL_UDB_P_U_RAD2_DP_IN3
00000004 a CYVAL_UDB_P_U_RAD2_DP_IN3
00000005 a CYVAL_UDB_P_U_RAD2_DP_IN4
00000005 a CYVAL_UDB_P_U_RAD2_DP_IN4
00000006 a CYVAL_UDB_P_U_RAD2_DP_IN5
00000006 a CYVAL_UDB_P_U_RAD2_DP_IN5
00000000 a CYVAL_UDB_P_U_RAD2_OFF
00000000 a CYVAL_UDB_P_U_RAD2_OFF
00000007 a CYVAL_UDB_P_U_RAD2_RESERVED
00000007 a CYVAL_UDB_P_U_RAD2_RESERVED
00000001 a CYVAL_UDB_P_U_RC_EN_INV_INVERT
00000001 a CYVAL_UDB_P_U_RC_EN_INV_INVERT
00000000 a CYVAL_UDB_P_U_RC_EN_INV_NOINV
00000000 a CYVAL_UDB_P_U_RC_EN_INV_NOINV
00000003 a CYVAL_UDB_P_U_RC_EN_MODE_LEVEL
00000003 a CYVAL_UDB_P_U_RC_EN_MODE_LEVEL
00000000 a CYVAL_UDB_P_U_RC_EN_MODE_OFF
00000000 a CYVAL_UDB_P_U_RC_EN_MODE_OFF
00000001 a CYVAL_UDB_P_U_RC_EN_MODE_ON
00000001 a CYVAL_UDB_P_U_RC_EN_MODE_ON
00000002 a CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE
00000002 a CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE
00000000 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0
00000000 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0
00000001 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1
00000001 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1
00000002 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2
00000002 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2
00000003 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3
00000003 a CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3
00000001 a CYVAL_UDB_P_U_RC_INV_INVERT
00000001 a CYVAL_UDB_P_U_RC_INV_INVERT
00000000 a CYVAL_UDB_P_U_RC_INV_NOINV
00000000 a CYVAL_UDB_P_U_RC_INV_NOINV
00000001 a CYVAL_UDB_P_U_RES_POL_ASSERTED
00000001 a CYVAL_UDB_P_U_RES_POL_ASSERTED
00000000 a CYVAL_UDB_P_U_RES_POL_NEGATED
00000000 a CYVAL_UDB_P_U_RES_POL_NEGATED
00000000 a CYVAL_UDB_P_U_RES_SEL_RC_IN0
00000000 a CYVAL_UDB_P_U_RES_SEL_RC_IN0
00000001 a CYVAL_UDB_P_U_RES_SEL_RC_IN1
00000001 a CYVAL_UDB_P_U_RES_SEL_RC_IN1
00000002 a CYVAL_UDB_P_U_RES_SEL_RC_IN2
00000002 a CYVAL_UDB_P_U_RES_SEL_RC_IN2
00000003 a CYVAL_UDB_P_U_RES_SEL_RC_IN3
00000003 a CYVAL_UDB_P_U_RES_SEL_RC_IN3
00000000 a CYVAL_UDB_P_U_ROUTE_EN_DISABLE
00000000 a CYVAL_UDB_P_U_ROUTE_EN_DISABLE
00000001 a CYVAL_UDB_P_U_ROUTE_EN_ROUTED
00000001 a CYVAL_UDB_P_U_ROUTE_EN_ROUTED
00000000 a CYVAL_UDB_P_U_ROUTE_LD_DISABLE
00000000 a CYVAL_UDB_P_U_ROUTE_LD_DISABLE
00000001 a CYVAL_UDB_P_U_ROUTE_LD_ROUTED
00000001 a CYVAL_UDB_P_U_ROUTE_LD_ROUTED
00000008 a CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK
00000008 a CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK
00000000 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK0
00000000 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK0
00000001 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK1
00000001 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK1
00000002 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK2
00000002 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK2
00000003 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK3
00000003 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK3
00000004 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK4
00000004 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK4
00000005 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK5
00000005 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK5
00000006 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK6
00000006 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK6
00000007 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK7
00000007 a CYVAL_UDB_P_U_SC_CK_SEL_GCLK7
00000009 a CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK
00000009 a CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK
00000000 a CYVAL_UDB_P_U_SC_EXT_RES_DISABLED
00000000 a CYVAL_UDB_P_U_SC_EXT_RES_DISABLED
00000001 a CYVAL_UDB_P_U_SC_EXT_RES_ENABLED
00000001 a CYVAL_UDB_P_U_SC_EXT_RES_ENABLED
00000001 a CYVAL_UDB_P_U_SC_INT_MD_INT_MODE
00000001 a CYVAL_UDB_P_U_SC_INT_MD_INT_MODE
00000000 a CYVAL_UDB_P_U_SC_INT_MD_NORMAL
00000000 a CYVAL_UDB_P_U_SC_INT_MD_NORMAL
00000000 a CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL
00000000 a CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL
00000002 a CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER
00000002 a CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER
00000001 a CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL
00000001 a CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL
00000003 a CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED
00000003 a CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED
00000001 a CYVAL_UDB_P_U_SC_RES_POL_INVERT
00000001 a CYVAL_UDB_P_U_SC_RES_POL_INVERT
00000000 a CYVAL_UDB_P_U_SC_RES_POL_NOINV
00000000 a CYVAL_UDB_P_U_SC_RES_POL_NOINV
00000000 a CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL
00000000 a CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL
00000001 a CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE
00000001 a CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE
00000001 a CYVAL_UDB_P_U_SHIFT_LEFT
00000001 a CYVAL_UDB_P_U_SHIFT_LEFT
00000000 a CYVAL_UDB_P_U_SHIFT_NOSHIFT
00000000 a CYVAL_UDB_P_U_SHIFT_NOSHIFT
00000002 a CYVAL_UDB_P_U_SHIFT_RIGHT
00000002 a CYVAL_UDB_P_U_SHIFT_RIGHT
00000000 a CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB
00000000 a CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB
00000001 a CYVAL_UDB_P_U_SHIFT_SEL_SOR
00000001 a CYVAL_UDB_P_U_SHIFT_SEL_SOR
00000003 a CYVAL_UDB_P_U_SHIFT_SWAP
00000003 a CYVAL_UDB_P_U_SHIFT_SWAP
00000001 a CYVAL_UDB_P_U_SI_MUX_DP_IN0
00000001 a CYVAL_UDB_P_U_SI_MUX_DP_IN0
00000002 a CYVAL_UDB_P_U_SI_MUX_DP_IN1
00000002 a CYVAL_UDB_P_U_SI_MUX_DP_IN1
00000003 a CYVAL_UDB_P_U_SI_MUX_DP_IN2
00000003 a CYVAL_UDB_P_U_SI_MUX_DP_IN2
00000004 a CYVAL_UDB_P_U_SI_MUX_DP_IN3
00000004 a CYVAL_UDB_P_U_SI_MUX_DP_IN3
00000005 a CYVAL_UDB_P_U_SI_MUX_DP_IN4
00000005 a CYVAL_UDB_P_U_SI_MUX_DP_IN4
00000006 a CYVAL_UDB_P_U_SI_MUX_DP_IN5
00000006 a CYVAL_UDB_P_U_SI_MUX_DP_IN5
00000000 a CYVAL_UDB_P_U_SI_MUX_OFF
00000000 a CYVAL_UDB_P_U_SI_MUX_OFF
00000007 a CYVAL_UDB_P_U_SI_MUX_RESERVED
00000007 a CYVAL_UDB_P_U_SI_MUX_RESERVED
00000000 a CYVAL_UDB_P_U_SI_SEL_CFG_A
00000000 a CYVAL_UDB_P_U_SI_SEL_CFG_A
00000001 a CYVAL_UDB_P_U_SI_SEL_CFG_B
00000001 a CYVAL_UDB_P_U_SI_SEL_CFG_B
00000003 a CYVAL_UDB_P_U_SI_SELA_CHAIN
00000003 a CYVAL_UDB_P_U_SI_SELA_CHAIN
00000000 a CYVAL_UDB_P_U_SI_SELA_DEFAULT
00000000 a CYVAL_UDB_P_U_SI_SELA_DEFAULT
00000001 a CYVAL_UDB_P_U_SI_SELA_REGISTERED
00000001 a CYVAL_UDB_P_U_SI_SELA_REGISTERED
00000002 a CYVAL_UDB_P_U_SI_SELA_ROUTE
00000002 a CYVAL_UDB_P_U_SI_SELA_ROUTE
00000003 a CYVAL_UDB_P_U_SI_SELB_CHAIN
00000003 a CYVAL_UDB_P_U_SI_SELB_CHAIN
00000000 a CYVAL_UDB_P_U_SI_SELB_DEFAULT
00000000 a CYVAL_UDB_P_U_SI_SELB_DEFAULT
00000001 a CYVAL_UDB_P_U_SI_SELB_REGISTERED
00000001 a CYVAL_UDB_P_U_SI_SELB_REGISTERED
00000002 a CYVAL_UDB_P_U_SI_SELB_ROUTE
00000002 a CYVAL_UDB_P_U_SI_SELB_ROUTE
00000000 a CYVAL_UDB_P_U_SRC_A_A0
00000000 a CYVAL_UDB_P_U_SRC_A_A0
00000001 a CYVAL_UDB_P_U_SRC_A_A1
00000001 a CYVAL_UDB_P_U_SRC_A_A1
00000002 a CYVAL_UDB_P_U_SRC_B_A0
00000002 a CYVAL_UDB_P_U_SRC_B_A0
00000003 a CYVAL_UDB_P_U_SRC_B_A1
00000003 a CYVAL_UDB_P_U_SRC_B_A1
00000000 a CYVAL_UDB_P_U_SRC_B_D0
00000000 a CYVAL_UDB_P_U_SRC_B_D0
00000001 a CYVAL_UDB_P_U_SRC_B_D1
00000001 a CYVAL_UDB_P_U_SRC_B_D1
00000001 a CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE
00000001 a CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE
00000000 a CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT
00000000 a CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT
00000001 a CYVAL_UDB_PA_CLKIN_EN_INV_INV
00000001 a CYVAL_UDB_PA_CLKIN_EN_INV_INV
00000000 a CYVAL_UDB_PA_CLKIN_EN_INV_NOINV
00000000 a CYVAL_UDB_PA_CLKIN_EN_INV_NOINV
00000003 a CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL
00000003 a CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL
00000000 a CYVAL_UDB_PA_CLKIN_EN_MODE_OFF
00000000 a CYVAL_UDB_PA_CLKIN_EN_MODE_OFF
00000001 a CYVAL_UDB_PA_CLKIN_EN_MODE_ON
00000001 a CYVAL_UDB_PA_CLKIN_EN_MODE_ON
00000002 a CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE
00000002 a CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE
00000001 a CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0
00000001 a CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0
00000002 a CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1
00000002 a CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1
00000003 a CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2
00000003 a CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2
00000000 a CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC
00000000 a CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC
00000001 a CYVAL_UDB_PA_CLKIN_INV_INV
00000001 a CYVAL_UDB_PA_CLKIN_INV_INV
00000000 a CYVAL_UDB_PA_CLKIN_INV_NOINV
00000000 a CYVAL_UDB_PA_CLKIN_INV_NOINV
00000009 a CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP
00000009 a CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP
0000000d a CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0
0000000d a CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0
0000000e a CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1
0000000e a CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1
0000000f a CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2
0000000f a CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2
00000000 a CYVAL_UDB_PA_CLKIN_SEL_GCLK0
00000000 a CYVAL_UDB_PA_CLKIN_SEL_GCLK0
00000001 a CYVAL_UDB_PA_CLKIN_SEL_GCLK1
00000001 a CYVAL_UDB_PA_CLKIN_SEL_GCLK1
00000002 a CYVAL_UDB_PA_CLKIN_SEL_GCLK2
00000002 a CYVAL_UDB_PA_CLKIN_SEL_GCLK2
00000003 a CYVAL_UDB_PA_CLKIN_SEL_GCLK3
00000003 a CYVAL_UDB_PA_CLKIN_SEL_GCLK3
00000004 a CYVAL_UDB_PA_CLKIN_SEL_GCLK4
00000004 a CYVAL_UDB_PA_CLKIN_SEL_GCLK4
00000005 a CYVAL_UDB_PA_CLKIN_SEL_GCLK5
00000005 a CYVAL_UDB_PA_CLKIN_SEL_GCLK5
00000006 a CYVAL_UDB_PA_CLKIN_SEL_GCLK6
00000006 a CYVAL_UDB_PA_CLKIN_SEL_GCLK6
00000007 a CYVAL_UDB_PA_CLKIN_SEL_GCLK7
00000007 a CYVAL_UDB_PA_CLKIN_SEL_GCLK7
0000000c a CYVAL_UDB_PA_CLKIN_SEL_PIN_RC
0000000c a CYVAL_UDB_PA_CLKIN_SEL_PIN_RC
00000001 a CYVAL_UDB_PA_CLKOUT_EN_INV_INV
00000001 a CYVAL_UDB_PA_CLKOUT_EN_INV_INV
00000000 a CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV
00000000 a CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV
00000003 a CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL
00000003 a CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL
00000000 a CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF
00000000 a CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF
00000001 a CYVAL_UDB_PA_CLKOUT_EN_MODE_ON
00000001 a CYVAL_UDB_PA_CLKOUT_EN_MODE_ON
00000002 a CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE
00000002 a CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE
00000001 a CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0
00000001 a CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0
00000002 a CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1
00000002 a CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1
00000003 a CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2
00000003 a CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2
00000000 a CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC
00000000 a CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC
00000001 a CYVAL_UDB_PA_CLKOUT_INV_INV
00000001 a CYVAL_UDB_PA_CLKOUT_INV_INV
00000000 a CYVAL_UDB_PA_CLKOUT_INV_NOINV
00000000 a CYVAL_UDB_PA_CLKOUT_INV_NOINV
00000009 a CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP
00000009 a CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP
0000000d a CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0
0000000d a CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0
0000000e a CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1
0000000e a CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1
0000000f a CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2
0000000f a CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2
00000000 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK0
00000000 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK0
00000001 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK1
00000001 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK1
00000002 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK2
00000002 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK2
00000003 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK3
00000003 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK3
00000004 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK4
00000004 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK4
00000005 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK5
00000005 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK5
00000006 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK6
00000006 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK6
00000007 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK7
00000007 a CYVAL_UDB_PA_CLKOUT_SEL_GCLK7
0000000c a CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC
0000000c a CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC
00000000 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3
00000000 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0
00000000 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0
00000001 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1
00000001 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1
00000002 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2
00000002 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2
00000003 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3
00000003 a CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3
00000002 a CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC0_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC0_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC1_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC1_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC2_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC2_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC3_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC3_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC4_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC4_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC5_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC5_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC6_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC6_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT
00000002 a CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC
00000002 a CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC
00000003 a CYVAL_UDB_PA_IN_SYNC7_RSVD
00000003 a CYVAL_UDB_PA_IN_SYNC7_RSVD
00000001 a CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC
00000001 a CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC
00000000 a CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT
00000000 a CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT
00000000 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3
00000000 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0
00000000 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0
00000001 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1
00000001 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1
00000002 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2
00000002 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2
00000003 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3
00000003 a CYVAL_UDB_PA_OE_SYNC0_CONSTANT0
00000003 a CYVAL_UDB_PA_OE_SYNC0_CONSTANT0
00000002 a CYVAL_UDB_PA_OE_SYNC0_CONSTANT1
00000002 a CYVAL_UDB_PA_OE_SYNC0_CONSTANT1
00000001 a CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC
00000001 a CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC
00000000 a CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT
00000000 a CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT
00000003 a CYVAL_UDB_PA_OE_SYNC1_CONSTANT0
00000003 a CYVAL_UDB_PA_OE_SYNC1_CONSTANT0
00000002 a CYVAL_UDB_PA_OE_SYNC1_CONSTANT1
00000002 a CYVAL_UDB_PA_OE_SYNC1_CONSTANT1
00000001 a CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC
00000001 a CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC
00000000 a CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT
00000000 a CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT
00000003 a CYVAL_UDB_PA_OE_SYNC2_CONSTANT0
00000003 a CYVAL_UDB_PA_OE_SYNC2_CONSTANT0
00000002 a CYVAL_UDB_PA_OE_SYNC2_CONSTANT1
00000002 a CYVAL_UDB_PA_OE_SYNC2_CONSTANT1
00000001 a CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC
00000001 a CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC
00000000 a CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT
00000000 a CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT
00000003 a CYVAL_UDB_PA_OE_SYNC3_CONSTANT0
00000003 a CYVAL_UDB_PA_OE_SYNC3_CONSTANT0
00000002 a CYVAL_UDB_PA_OE_SYNC3_CONSTANT1
00000002 a CYVAL_UDB_PA_OE_SYNC3_CONSTANT1
00000001 a CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC
00000001 a CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC
00000000 a CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT
00000000 a CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC0_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC0_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC1_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC1_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC2_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC2_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC3_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC3_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC4_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC4_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC5_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC5_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC6_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC6_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT
00000002 a CYVAL_UDB_PA_OUT_SYNC7_CLOCK
00000002 a CYVAL_UDB_PA_OUT_SYNC7_CLOCK
00000003 a CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV
00000003 a CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV
00000001 a CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC
00000001 a CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC
00000000 a CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT
00000000 a CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT
00000000 a CYVAL_UDB_PA_PIN_SEL_PIN0
00000000 a CYVAL_UDB_PA_PIN_SEL_PIN0
00000001 a CYVAL_UDB_PA_PIN_SEL_PIN1
00000001 a CYVAL_UDB_PA_PIN_SEL_PIN1
00000002 a CYVAL_UDB_PA_PIN_SEL_PIN2
00000002 a CYVAL_UDB_PA_PIN_SEL_PIN2
00000003 a CYVAL_UDB_PA_PIN_SEL_PIN3
00000003 a CYVAL_UDB_PA_PIN_SEL_PIN3
00000004 a CYVAL_UDB_PA_PIN_SEL_PIN4
00000004 a CYVAL_UDB_PA_PIN_SEL_PIN4
00000005 a CYVAL_UDB_PA_PIN_SEL_PIN5
00000005 a CYVAL_UDB_PA_PIN_SEL_PIN5
00000006 a CYVAL_UDB_PA_PIN_SEL_PIN6
00000006 a CYVAL_UDB_PA_PIN_SEL_PIN6
00000007 a CYVAL_UDB_PA_PIN_SEL_PIN7
00000007 a CYVAL_UDB_PA_PIN_SEL_PIN7
00000000 a CYVAL_UDB_PA_RES_IN_EN_DISABLE
00000000 a CYVAL_UDB_PA_RES_IN_EN_DISABLE
00000001 a CYVAL_UDB_PA_RES_IN_EN_ENABLE
00000001 a CYVAL_UDB_PA_RES_IN_EN_ENABLE
00000001 a CYVAL_UDB_PA_RES_IN_INV_INV
00000001 a CYVAL_UDB_PA_RES_IN_INV_INV
00000000 a CYVAL_UDB_PA_RES_IN_INV_NOINV
00000000 a CYVAL_UDB_PA_RES_IN_INV_NOINV
00000001 a CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0
00000001 a CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0
00000002 a CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1
00000002 a CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1
00000003 a CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2
00000003 a CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2
00000000 a CYVAL_UDB_PA_RES_IN_SEL_PIN_RC
00000000 a CYVAL_UDB_PA_RES_IN_SEL_PIN_RC
00000000 a CYVAL_UDB_PA_RES_OE_EN_DISABLE
00000000 a CYVAL_UDB_PA_RES_OE_EN_DISABLE
00000001 a CYVAL_UDB_PA_RES_OE_EN_ENABLE
00000001 a CYVAL_UDB_PA_RES_OE_EN_ENABLE
00000000 a CYVAL_UDB_PA_RES_OUT_EN_DISABLE
00000000 a CYVAL_UDB_PA_RES_OUT_EN_DISABLE
00000001 a CYVAL_UDB_PA_RES_OUT_EN_ENABLE
00000001 a CYVAL_UDB_PA_RES_OUT_EN_ENABLE
00000001 a CYVAL_UDB_PA_RES_OUT_INV_INV
00000001 a CYVAL_UDB_PA_RES_OUT_INV_INV
00000000 a CYVAL_UDB_PA_RES_OUT_INV_NOINV
00000000 a CYVAL_UDB_PA_RES_OUT_INV_NOINV
00000001 a CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0
00000001 a CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0
00000002 a CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1
00000002 a CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1
00000003 a CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2
00000003 a CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2
00000000 a CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC
00000000 a CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC
00000000 a CYVAL_UDB_UDBIF_BANK_EN_DISABLE
00000000 a CYVAL_UDB_UDBIF_BANK_EN_DISABLE
00000001 a CYVAL_UDB_UDBIF_BANK_EN_ENABLE
00000001 a CYVAL_UDB_UDBIF_BANK_EN_ENABLE
00000001 a CYVAL_UDB_UDBIF_DIS_COR_DISABLE
00000001 a CYVAL_UDB_UDBIF_DIS_COR_DISABLE
00000000 a CYVAL_UDB_UDBIF_DIS_COR_NORMAL
00000000 a CYVAL_UDB_UDBIF_DIS_COR_NORMAL
00000000 a CYVAL_UDB_UDBIF_GLBL_WR_DISABLE
00000000 a CYVAL_UDB_UDBIF_GLBL_WR_DISABLE
00000001 a CYVAL_UDB_UDBIF_GLBL_WR_ENABLE
00000001 a CYVAL_UDB_UDBIF_GLBL_WR_ENABLE
00000001 a CYVAL_UDB_UDBIF_LOCK_LOCKED
00000001 a CYVAL_UDB_UDBIF_LOCK_LOCKED
00000000 a CYVAL_UDB_UDBIF_LOCK_MUTABLE
00000000 a CYVAL_UDB_UDBIF_LOCK_MUTABLE
00000000 a CYVAL_UDB_UDBIF_PIPE_BYPASS
00000000 a CYVAL_UDB_UDBIF_PIPE_BYPASS
00000001 a CYVAL_UDB_UDBIF_PIPE_PIPELINED
00000001 a CYVAL_UDB_UDBIF_PIPE_PIPELINED
00000000 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS
00000000 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS
00000001 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS
00000001 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS
00000003 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT
00000003 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT
00000002 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS
00000002 a CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS
00000000 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT
00000000 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT
00000002 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS
00000002 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS
00000001 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS
00000001 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS
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00000003 a CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS
00000000 a CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE
00000000 a CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE
00000001 a CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE
00000001 a CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE
00000000 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT
00000000 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT
00000002 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS
00000002 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS
00000001 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS
00000001 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS
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00000003 a CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS
00000000 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT
00000000 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT
00000002 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS
00000002 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS
00000001 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS
00000001 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS
00000003 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS
00000003 a CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS
00000000 a CYVAL_UDB_W16_CNT_START_LS_DISABLE
00000000 a CYVAL_UDB_W16_CNT_START_LS_DISABLE
00000001 a CYVAL_UDB_W16_CNT_START_LS_ENABLE
00000001 a CYVAL_UDB_W16_CNT_START_LS_ENABLE
00000000 a CYVAL_UDB_W16_CNT_START_MS_DISABLE
00000000 a CYVAL_UDB_W16_CNT_START_MS_DISABLE
00000001 a CYVAL_UDB_W16_CNT_START_MS_ENABLE
00000001 a CYVAL_UDB_W16_CNT_START_MS_ENABLE
00000001 a CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR
00000001 a CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR
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00000000 a CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR
00000001 a CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR
00000000 a CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO0_LVL_LS_MID
00000001 a CYVAL_UDB_W16_FIFO0_LVL_LS_MID
00000000 a CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO0_LVL_MS_MID
00000001 a CYVAL_UDB_W16_FIFO0_LVL_MS_MID
00000000 a CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR
00000001 a CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR
00000000 a CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR
00000001 a CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR
00000000 a CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO1_LVL_LS_MID
00000001 a CYVAL_UDB_W16_FIFO1_LVL_LS_MID
00000000 a CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL
00000001 a CYVAL_UDB_W16_FIFO1_LVL_MS_MID
00000001 a CYVAL_UDB_W16_FIFO1_LVL_MS_MID
00000000 a CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL
00000000 a CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL
00000000 a CYVAL_UDB_W16_INT_EN_LS_DISABLE
00000000 a CYVAL_UDB_W16_INT_EN_LS_DISABLE
00000001 a CYVAL_UDB_W16_INT_EN_LS_ENABLE
00000001 a CYVAL_UDB_W16_INT_EN_LS_ENABLE
00000000 a CYVAL_UDB_W16_INT_EN_MS_DISABLE
00000000 a CYVAL_UDB_W16_INT_EN_MS_DISABLE
00000001 a CYVAL_UDB_W16_INT_EN_MS_ENABLE
00000001 a CYVAL_UDB_W16_INT_EN_MS_ENABLE
00000000 a CYVAL_UDB_W32_CNT_START_0_DISABLE
00000000 a CYVAL_UDB_W32_CNT_START_0_DISABLE
00000001 a CYVAL_UDB_W32_CNT_START_0_ENABLE
00000001 a CYVAL_UDB_W32_CNT_START_0_ENABLE
00000000 a CYVAL_UDB_W32_CNT_START_1_DISABLE
00000000 a CYVAL_UDB_W32_CNT_START_1_DISABLE
00000001 a CYVAL_UDB_W32_CNT_START_1_ENABLE
00000001 a CYVAL_UDB_W32_CNT_START_1_ENABLE
00000000 a CYVAL_UDB_W32_CNT_START_2_DISABLE
00000000 a CYVAL_UDB_W32_CNT_START_2_DISABLE
00000001 a CYVAL_UDB_W32_CNT_START_2_ENABLE
00000001 a CYVAL_UDB_W32_CNT_START_2_ENABLE
00000000 a CYVAL_UDB_W32_CNT_START_3_DISABLE
00000000 a CYVAL_UDB_W32_CNT_START_3_DISABLE
00000001 a CYVAL_UDB_W32_CNT_START_3_ENABLE
00000001 a CYVAL_UDB_W32_CNT_START_3_ENABLE
00000001 a CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR
00000001 a CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR
00000000 a CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR
00000001 a CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR
00000000 a CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR
00000001 a CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR
00000000 a CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR
00000001 a CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR
00000000 a CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_LVL_0_MID
00000001 a CYVAL_UDB_W32_FIFO0_LVL_0_MID
00000000 a CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_LVL_1_MID
00000001 a CYVAL_UDB_W32_FIFO0_LVL_1_MID
00000000 a CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_LVL_2_MID
00000001 a CYVAL_UDB_W32_FIFO0_LVL_2_MID
00000000 a CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL
00000001 a CYVAL_UDB_W32_FIFO0_LVL_3_MID
00000001 a CYVAL_UDB_W32_FIFO0_LVL_3_MID
00000000 a CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL
00000000 a CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR
00000001 a CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR
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00000000 a CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR
00000001 a CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR
00000000 a CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL
00000000 a CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR
00000001 a CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR
00000000 a CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL
00000000 a CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR
00000001 a CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR
00000000 a CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL
00000000 a CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_LVL_0_MID
00000001 a CYVAL_UDB_W32_FIFO1_LVL_0_MID
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00000000 a CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_LVL_1_MID
00000001 a CYVAL_UDB_W32_FIFO1_LVL_1_MID
00000000 a CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL
00000000 a CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_LVL_2_MID
00000001 a CYVAL_UDB_W32_FIFO1_LVL_2_MID
00000000 a CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL
00000000 a CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL
00000001 a CYVAL_UDB_W32_FIFO1_LVL_3_MID
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00000000 a CYVAL_UDB_W32_INT_EN_0_DISABLE
00000000 a CYVAL_UDB_W32_INT_EN_0_DISABLE
00000001 a CYVAL_UDB_W32_INT_EN_0_ENABLE
00000001 a CYVAL_UDB_W32_INT_EN_0_ENABLE
00000000 a CYVAL_UDB_W32_INT_EN_1_DISABLE
00000000 a CYVAL_UDB_W32_INT_EN_1_DISABLE
00000001 a CYVAL_UDB_W32_INT_EN_1_ENABLE
00000001 a CYVAL_UDB_W32_INT_EN_1_ENABLE
00000000 a CYVAL_UDB_W32_INT_EN_2_DISABLE
00000000 a CYVAL_UDB_W32_INT_EN_2_DISABLE
00000001 a CYVAL_UDB_W32_INT_EN_2_ENABLE
00000001 a CYVAL_UDB_W32_INT_EN_2_ENABLE
00000000 a CYVAL_UDB_W32_INT_EN_3_DISABLE
00000000 a CYVAL_UDB_W32_INT_EN_3_DISABLE
00000001 a CYVAL_UDB_W32_INT_EN_3_ENABLE
00000001 a CYVAL_UDB_W32_INT_EN_3_ENABLE
00000000 a CYVAL_UDB_W8_CNT_START_DISABLE
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00000000 a CYVAL_UDB_W8_FIFO0_LVL_NORMAL
00000001 a CYVAL_UDB_W8_FIFO1_CLR_CLEAR
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00000000 a CYVAL_UDB_W8_INT_EN_DISABLE
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00000001 a UART_tx__PORT
40040104 a UART_tx__PS
40040104 a UART_tx__PS
00000005 a UART_tx__SHIFT
00000005 a UART_tx__SHIFT
20001048 d UpdAdvData
20001020 D UpdAdvData
2000104c d UpdScanRspData
20001024 D UpdScanRspData
20001010 d UsrEvtMsk
e000e180 a Wakeup_Interrupt__INTC_CLR_EN_REG
e000e180 a Wakeup_Interrupt__INTC_CLR_EN_REG
e000e280 a Wakeup_Interrupt__INTC_CLR_PD_REG
e000e280 a Wakeup_Interrupt__INTC_CLR_PD_REG
00000004 a Wakeup_Interrupt__INTC_MASK
00000004 a Wakeup_Interrupt__INTC_MASK
00000002 a Wakeup_Interrupt__INTC_NUMBER
00000002 a Wakeup_Interrupt__INTC_NUMBER
00c00000 a Wakeup_Interrupt__INTC_PRIOR_MASK
00c00000 a Wakeup_Interrupt__INTC_PRIOR_MASK
00000003 a Wakeup_Interrupt__INTC_PRIOR_NUM
00000003 a Wakeup_Interrupt__INTC_PRIOR_NUM
e000e400 a Wakeup_Interrupt__INTC_PRIOR_REG
e000e400 a Wakeup_Interrupt__INTC_PRIOR_REG
e000e100 a Wakeup_Interrupt__INTC_SET_EN_REG
e000e100 a Wakeup_Interrupt__INTC_SET_EN_REG
e000e200 a Wakeup_Interrupt__INTC_SET_PD_REG
e000e200 a Wakeup_Interrupt__INTC_SET_PD_REG
000007ec T Wakeup_Interrupt_ClearPending
000007c4 T Wakeup_Interrupt_Disable
000007b8 T Wakeup_Interrupt_Enable
00000784 T Wakeup_Interrupt_Interrupt
00000794 T Wakeup_Interrupt_SetPriority
00000788 T Wakeup_Interrupt_SetVector
000007d0 T Wakeup_Interrupt_Start
e000e180 a WDT_Interrupt__INTC_CLR_EN_REG
e000e180 a WDT_Interrupt__INTC_CLR_EN_REG
e000e280 a WDT_Interrupt__INTC_CLR_PD_REG
e000e280 a WDT_Interrupt__INTC_CLR_PD_REG
00000100 a WDT_Interrupt__INTC_MASK
00000100 a WDT_Interrupt__INTC_MASK
00000008 a WDT_Interrupt__INTC_NUMBER
00000008 a WDT_Interrupt__INTC_NUMBER
000000c0 a WDT_Interrupt__INTC_PRIOR_MASK
000000c0 a WDT_Interrupt__INTC_PRIOR_MASK
00000003 a WDT_Interrupt__INTC_PRIOR_NUM
00000003 a WDT_Interrupt__INTC_PRIOR_NUM
e000e408 a WDT_Interrupt__INTC_PRIOR_REG
e000e408 a WDT_Interrupt__INTC_PRIOR_REG
e000e100 a WDT_Interrupt__INTC_SET_EN_REG
e000e100 a WDT_Interrupt__INTC_SET_EN_REG
e000e200 a WDT_Interrupt__INTC_SET_PD_REG
e000e200 a WDT_Interrupt__INTC_SET_PD_REG
00000758 T WDT_Interrupt_Disable
00000748 T WDT_Interrupt_Enable
00000728 T WDT_Interrupt_SetPriority
0000071c T WDT_Interrupt_SetVector
00000768 T WDT_Interrupt_StartEx
000004f8 T WDT_Start
0001376c T write_task_bt_init
00013788 T write_task_bt_shutdown
000137d0 T write_task_enqueue
0001385c T write_task_init
000138a8 T write_task_start_routine
000003c4 T WriteAttrServChanged
200011f8 D wt_bh_counter
200022c8 b wt_internal_queue
20002310 b wt_queues
000138e4 T wt_service_queue
200011f4 D wt_state
200022ec b wt_user_api_queue
