# Static Timing Analysis

Project : | BLE_OTA_FixedStack_Bootloader01
Build Time : | 07/30/19 12:30:14
Device : | CY8C4248LQI-BL583
Temperature : | -40C - 85C
VDDA_1 : | 3.30
VDDA_CTB : | 3.30
VDDD_0 : | 3.30
VDDIO_0 : | 3.30
VDDIO_1 : | 3.30
VDDIO_2 : | 3.30
VDDR_BGLS : | 3.30
VDDR_HF : | 3.30
VDDR_HLS : | 3.30
VDDR_LF : | 3.30
VDDR_SYN : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyECO | CyECO | 24.000 MHz | 24.000 MHz | N/A |
CyHFCLK | CyHFCLK | 48.000 MHz | 48.000 MHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 48.000 MHz | 48.000 MHz | N/A |
CyLFCLK | CyLFCLK | 32.768 kHz | 32.768 kHz | N/A |
CyRouted1 | CyRouted1 | 48.000 MHz | 48.000 MHz | N/A |
CySYSCLK | CySYSCLK | 24.000 MHz | 24.000 MHz | N/A |
CyWCO | CyWCO | 32.768 kHz | 32.768 kHz | N/A |