Static Timing Analysis

Project : BLE_Controlled_motor_speed
Build Time : 07/30/18 16:05:48
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock(FFB) Clock(FFB) 12.000 MHz 12.000 MHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFClk CyHFClk 48.000 MHz 48.000 MHz N/A
Clock CyHFClk 12.000 MHz 12.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFClk CyLFClk 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySysClk CySysClk 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Clock To Output Section
+ Clock(FFB)
Source Destination Delay (ns)
\PWM:cy_m0s8_tcpwm_1\/line motor(0)_PAD 16.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,3) 1 \PWM:cy_m0s8_tcpwm_1\ \PWM:cy_m0s8_tcpwm_1\/clock \PWM:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_39 \PWM:cy_m0s8_tcpwm_1\/line motor(0)/pin_input 1.000
iocell1 P3[6] 1 motor(0) motor(0)/pin_input motor(0)/pad_out 15.420
Route 1 motor(0)_PAD motor(0)/pad_out motor(0)_PAD 0.000
Clock Clock path delay 0.000