Static Timing Analysis

Project : Design01
Build Time : 05/13/16 17:52:15
Device : CY8C4248BZI-L489
Temperature : -40C - 85C
VBUS : 5.00
VDDA_0 : 3.30
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_3 : 3.30
VDDIO_4 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK CyHFCLK 115.385 kHz 115.385 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 187.500 kHz 187.500 kHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 115.385 kHz 115.385 kHz N/A