Static Timing Analysis

Project : CapSense_CSD_P4_Proximity_Design01
Build Time : 02/12/19 11:13:17
Device : CY8C4247AZI-M485
Temperature : -40C - 85C
VDDA_0 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDD_0 : 3.30
VDDD_1 : 3.30
VDDIO : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_SampleClk(FFB) CapSense_SampleClk(FFB) 94.118 kHz 94.118 kHz N/A
CapSense_SenseClk(FFB) CapSense_SenseClk(FFB) 94.118 kHz 94.118 kHz N/A
Clock_2(FFB) Clock_2(FFB) 12.000 MHz 12.000 MHz N/A
Clock_PWM(FFB) Clock_PWM(FFB) 12.000 MHz 12.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
CapSense_SampleClk CyHFCLK 94.118 kHz 94.118 kHz N/A
CapSense_SenseClk CyHFCLK 94.118 kHz 94.118 kHz N/A
Clock_PWM CyHFCLK 12.000 MHz 12.000 MHz N/A
Clock_2 CyHFCLK 12.000 MHz 12.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ Clock_2(FFB)
Source Destination Delay (ns)
\PWM_1:cy_m0s8_tcpwm_1\/line Pin_1(0)_PAD 19.710
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_1:cy_m0s8_tcpwm_1\ \PWM_1:cy_m0s8_tcpwm_1\/clock \PWM_1:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_96 \PWM_1:cy_m0s8_tcpwm_1\/line Pin_1(0)/pin_input 1.000
iocell6 P2[6] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 18.710
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_PWM(FFB)
Source Destination Delay (ns)
\PRSm:cy_m0s8_tcpwm_1\/line Pin_LED(0)_PAD 21.472
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PRSm:cy_m0s8_tcpwm_1\ \PRSm:cy_m0s8_tcpwm_1\/clock \PRSm:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_80 \PRSm:cy_m0s8_tcpwm_1\/line Pin_LED(0)/pin_input 5.992
iocell4 P0[6] 1 Pin_LED(0) Pin_LED(0)/pin_input Pin_LED(0)/pad_out 15.480
Route 1 Pin_LED(0)_PAD Pin_LED(0)/pad_out Pin_LED(0)_PAD 0.000
Clock Clock path delay 0.000