Static Timing Analysis

Project : PSoCandPYTHON
Build Time : 11/13/17 07:34:07
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 135.428 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\USB:nrqSync:genblk1[6]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 135.428 MHz 7.384 34.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[6]:INST\ \USB:nrqSync:genblk1[6]:INST\/clock \USB:nrqSync:genblk1[6]:INST\/out 1.020
Route 1 \USB:Net_2040_6\ \USB:nrqSync:genblk1[6]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 5.864
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[5]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 135.722 MHz 7.368 34.299
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[5]:INST\ \USB:nrqSync:genblk1[5]:INST\/clock \USB:nrqSync:genblk1[5]:INST\/out 1.020
Route 1 \USB:Net_2040_5\ \USB:nrqSync:genblk1[5]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 5.848
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[4]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 135.888 MHz 7.359 34.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[4]:INST\ \USB:nrqSync:genblk1[4]:INST\/clock \USB:nrqSync:genblk1[4]:INST\/out 1.020
Route 1 \USB:Net_2040_4\ \USB:nrqSync:genblk1[4]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 5.839
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 187.161 MHz 5.343 36.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/clock \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt 2.550
Route 1 \USB:EPs_1_to_7_dma_complete\ \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.293
statusicell2 U(1,4) 1 \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[3]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 224.719 MHz 4.450 37.217
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[3]:INST\ \USB:nrqSync:genblk1[3]:INST\/clock \USB:nrqSync:genblk1[3]:INST\/out 1.020
Route 1 \USB:Net_2040_3\ \USB:nrqSync:genblk1[3]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 2.930
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[2]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 224.820 MHz 4.448 37.219
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[2]:INST\ \USB:nrqSync:genblk1[2]:INST\/clock \USB:nrqSync:genblk1[2]:INST\/out 1.020
Route 1 \USB:Net_2040_2\ \USB:nrqSync:genblk1[2]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 2.928
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[0]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 225.632 MHz 4.432 37.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[0]:INST\ \USB:nrqSync:genblk1[0]:INST\/clock \USB:nrqSync:genblk1[0]:INST\/out 1.020
Route 1 \USB:Net_2040_0\ \USB:nrqSync:genblk1[0]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.912
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[1]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 225.683 MHz 4.431 37.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[1]:INST\ \USB:nrqSync:genblk1[1]:INST\/clock \USB:nrqSync:genblk1[1]:INST\/out 1.020
Route 1 \USB:Net_2040_1\ \USB:nrqSync:genblk1[1]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.911
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
\USB:nrqSync:genblk1[7]:INST\/out \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 225.734 MHz 4.430 37.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[7]:INST\ \USB:nrqSync:genblk1[7]:INST\/clock \USB:nrqSync:genblk1[7]:INST\/out 1.020
Route 1 \USB:Net_2040_7\ \USB:nrqSync:genblk1[7]:INST\/out \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.910
statusicell2 U(1,4) 1 \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\USB:nrqSync:genblk1[7]:INST\/out \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 1.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[7]:INST\ \USB:nrqSync:genblk1[7]:INST\/clock \USB:nrqSync:genblk1[7]:INST\/out 0.350
Route 1 \USB:Net_2040_7\ \USB:nrqSync:genblk1[7]:INST\/out \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.910
statusicell2 U(1,4) 1 \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[1]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 1.261
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[1]:INST\ \USB:nrqSync:genblk1[1]:INST\/clock \USB:nrqSync:genblk1[1]:INST\/out 0.350
Route 1 \USB:Net_2040_1\ \USB:nrqSync:genblk1[1]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_1 2.911
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[0]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 1.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[0]:INST\ \USB:nrqSync:genblk1[0]:INST\/clock \USB:nrqSync:genblk1[0]:INST\/out 0.350
Route 1 \USB:Net_2040_0\ \USB:nrqSync:genblk1[0]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.912
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[2]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 1.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[2]:INST\ \USB:nrqSync:genblk1[2]:INST\/clock \USB:nrqSync:genblk1[2]:INST\/out 0.350
Route 1 \USB:Net_2040_2\ \USB:nrqSync:genblk1[2]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_2 2.928
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[3]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 1.280
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[3]:INST\ \USB:nrqSync:genblk1[3]:INST\/clock \USB:nrqSync:genblk1[3]:INST\/out 0.350
Route 1 \USB:Net_2040_3\ \USB:nrqSync:genblk1[3]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_3 2.930
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/clock \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt 2.550
Route 1 \USB:EPs_1_to_7_dma_complete\ \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/interrupt \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\/status_0 2.293
statusicell2 U(1,4) 1 \USB:EP8_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[4]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 4.189
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[4]:INST\ \USB:nrqSync:genblk1[4]:INST\/clock \USB:nrqSync:genblk1[4]:INST\/out 0.350
Route 1 \USB:Net_2040_4\ \USB:nrqSync:genblk1[4]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_4 5.839
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[5]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 4.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,3) 1 \USB:nrqSync:genblk1[5]:INST\ \USB:nrqSync:genblk1[5]:INST\/clock \USB:nrqSync:genblk1[5]:INST\/out 0.350
Route 1 \USB:Net_2040_5\ \USB:nrqSync:genblk1[5]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_5 5.848
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000
\USB:nrqSync:genblk1[6]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 4.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \USB:nrqSync:genblk1[6]:INST\ \USB:nrqSync:genblk1[6]:INST\/clock \USB:nrqSync:genblk1[6]:INST\/out 0.350
Route 1 \USB:Net_2040_6\ \USB:nrqSync:genblk1[6]:INST\/out \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\/status_6 5.864
statusicell1 U(0,4) 1 \USB:EP17_DMA_Done_SR:sts_intr:sts_reg\ HOLD -2.000
Clock Skew 0.000