Static Timing Analysis

Project : CapSense
Build Time : 06/07/13 15:09:09
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CapSense_IntClock CyMASTER_CLK 12.000 MHz 12.000 MHz 23.519 MHz
timer_clock CyMASTER_CLK 100.000  Hz 100.000  Hz 28.378 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 41.943 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 23.519 MHz 42.519 40.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:int\/main_0 3.409
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_0 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cnt_enable\/main_1 2.790
macrocell14 U(2,1) 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/main_1 \CapSense:MeasureCH0:cnt_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/q \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 2.295
macrocell16 U(2,1) 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_1\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 2.302
datapathcell3 U(2,1) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 23.524 MHz 42.510 40.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:int\/main_0 3.409
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_0 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cnt_enable\/main_1 2.790
macrocell14 U(2,1) 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/main_1 \CapSense:MeasureCH0:cnt_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/q \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 2.295
macrocell17 U(2,1) 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 \CapSense:MeasureCH0:cs_addr_cnt_2\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 2.293
datapathcell3 U(2,1) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 23.524 MHz 42.509 40.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:int\/main_0 3.409
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_0 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cnt_enable\/main_1 2.790
macrocell14 U(2,1) 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/main_1 \CapSense:MeasureCH0:cnt_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/q \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 2.295
macrocell15 U(2,1) 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 2.292
datapathcell3 U(2,1) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 23.633 MHz 42.313 41.020
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:int\/main_1 3.233
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_1 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cnt_enable\/main_1 2.790
macrocell14 U(2,1) 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/main_1 \CapSense:MeasureCH0:cnt_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/q \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 2.295
macrocell16 U(2,1) 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_1\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_1\ \CapSense:MeasureCH0:cs_addr_cnt_1\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_1 2.302
datapathcell3 U(2,1) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 23.638 MHz 42.304 41.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:int\/main_1 3.233
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_1 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cnt_enable\/main_1 2.790
macrocell14 U(2,1) 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/main_1 \CapSense:MeasureCH0:cnt_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/q \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 2.295
macrocell17 U(2,1) 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/main_1 \CapSense:MeasureCH0:cs_addr_cnt_2\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_2\ \CapSense:MeasureCH0:cs_addr_cnt_2\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_2 2.293
datapathcell3 U(2,1) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 23.639 MHz 42.303 41.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:int\/main_1 3.233
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_1 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cnt_enable\/main_1 2.790
macrocell14 U(2,1) 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/main_1 \CapSense:MeasureCH0:cnt_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:cnt_enable\ \CapSense:MeasureCH0:cnt_enable\/q \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 2.295
macrocell15 U(2,1) 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/main_2 \CapSense:MeasureCH0:cs_addr_cnt_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_cnt_0\ \CapSense:MeasureCH0:cs_addr_cnt_0\/q \CapSense:MeasureCH0:UDB:Counter:u0\/cs_addr_0 2.292
datapathcell3 U(2,1) 1 \CapSense:MeasureCH0:UDB:Counter:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 26.465 MHz 37.786 45.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:int\/main_0 3.409
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_0 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cs_addr_win_1\/main_2 3.702
macrocell19 U(2,2) 1 \CapSense:MeasureCH0:cs_addr_win_1\ \CapSense:MeasureCH0:cs_addr_win_1\/main_2 \CapSense:MeasureCH0:cs_addr_win_1\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_win_1\ \CapSense:MeasureCH0:cs_addr_win_1\/q \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 2.302
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 26.471 MHz 37.777 45.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb 3.850
Route 1 \CapSense:MeasureCH0:zw0\ \CapSense:MeasureCH0:UDB:Window:u0\/z0_comb \CapSense:MeasureCH0:int\/main_0 3.409
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_0 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cs_addr_win_0\/main_2 3.702
macrocell18 U(2,2) 1 \CapSense:MeasureCH0:cs_addr_win_0\ \CapSense:MeasureCH0:cs_addr_win_0\/main_2 \CapSense:MeasureCH0:cs_addr_win_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_win_0\ \CapSense:MeasureCH0:cs_addr_win_0\/q \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 2.293
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 26.610 MHz 37.580 45.753
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:int\/main_1 3.233
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_1 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cs_addr_win_1\/main_2 3.702
macrocell19 U(2,2) 1 \CapSense:MeasureCH0:cs_addr_win_1\ \CapSense:MeasureCH0:cs_addr_win_1\/main_2 \CapSense:MeasureCH0:cs_addr_win_1\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_win_1\ \CapSense:MeasureCH0:cs_addr_win_1\/q \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_1 2.302
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ SETUP 11.530
Clock Skew 0.000
\CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 26.616 MHz 37.571 45.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ \CapSense:MeasureCH0:UDB:Window:u0\/clock \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb 3.820
Route 1 \CapSense:MeasureCH0:zw1\ \CapSense:MeasureCH0:UDB:Window:u0\/z1_comb \CapSense:MeasureCH0:int\/main_1 3.233
macrocell21 U(2,1) 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/main_1 \CapSense:MeasureCH0:int\/q 3.350
Route 1 \CapSense:MeasureCH0:int\ \CapSense:MeasureCH0:int\/q \CapSense:MeasureCH0:win_enable\/main_1 2.943
macrocell22 U(2,1) 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/main_1 \CapSense:MeasureCH0:win_enable\/q 3.350
Route 1 \CapSense:MeasureCH0:win_enable\ \CapSense:MeasureCH0:win_enable\/q \CapSense:MeasureCH0:cs_addr_win_0\/main_2 3.702
macrocell18 U(2,2) 1 \CapSense:MeasureCH0:cs_addr_win_0\ \CapSense:MeasureCH0:cs_addr_win_0\/main_2 \CapSense:MeasureCH0:cs_addr_win_0\/q 3.350
Route 1 \CapSense:MeasureCH0:cs_addr_win_0\ \CapSense:MeasureCH0:cs_addr_win_0\/q \CapSense:MeasureCH0:UDB:Window:u0\/cs_addr_0 2.293
datapathcell4 U(2,2) 1 \CapSense:MeasureCH0:UDB:Window:u0\ SETUP 11.530
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 41.943 MHz 23.842 17.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 3.152
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 48.704 MHz 20.532 21.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 3.152
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 48.752 MHz 20.512 21.155
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 3.132
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_2 55.142 MHz 18.135 23.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_2 4.035
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 11.520
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 57.964 MHz 17.252 24.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 3.152
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 58.032 MHz 17.232 24.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 3.132
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 175.377 MHz 5.702 35.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 3.122
statusicell1 U(3,0) 1 \Timer_1:TimerUDB:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 1e+007ns(100  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 28.378 MHz 35.239 9999964.761
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:timer_enable\/main_0 2.906
macrocell36 U(2,0) 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/main_0 \Timer_1:TimerUDB:timer_enable\/q 3.350
Route 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/q \Timer_1:TimerUDB:trig_reg\/main_0 2.224
macrocell37 U(2,0) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_1 2.719
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 31.319 MHz 31.929 9999968.071
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:timer_enable\/main_0 2.906
macrocell36 U(2,0) 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/main_0 \Timer_1:TimerUDB:timer_enable\/q 3.350
Route 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/q \Timer_1:TimerUDB:trig_reg\/main_0 2.224
macrocell37 U(2,0) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_1 2.719
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 31.328 MHz 31.920 9999968.080
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:timer_enable\/main_0 2.906
macrocell36 U(2,0) 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/main_0 \Timer_1:TimerUDB:timer_enable\/q 3.350
Route 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/q \Timer_1:TimerUDB:trig_reg\/main_0 2.224
macrocell37 U(2,0) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_1 2.710
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_1 \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_1 33.829 MHz 29.560 9999970.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:timer_enable\/main_0 2.906
macrocell36 U(2,0) 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/main_0 \Timer_1:TimerUDB:timer_enable\/q 3.350
Route 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/q \Timer_1:TimerUDB:trig_reg\/main_0 2.224
macrocell37 U(2,0) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_1 3.630
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_1 34.905 MHz 28.649 9999971.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:timer_enable\/main_0 2.906
macrocell36 U(2,0) 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/main_0 \Timer_1:TimerUDB:timer_enable\/q 3.350
Route 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/q \Timer_1:TimerUDB:trig_reg\/main_0 2.224
macrocell37 U(2,0) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_1 2.719
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_1 34.916 MHz 28.640 9999971.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:timer_enable\/main_0 2.906
macrocell36 U(2,0) 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/main_0 \Timer_1:TimerUDB:timer_enable\/q 3.350
Route 1 \Timer_1:TimerUDB:timer_enable\ \Timer_1:TimerUDB:timer_enable\/q \Timer_1:TimerUDB:trig_reg\/main_0 2.224
macrocell37 U(2,0) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_1 2.710
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u0\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 35.280 MHz 28.345 9999971.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/clock \Timer_1:TimerUDB:sT24:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/z0 \Timer_1:TimerUDB:sT24:timerdp:u1\/z0i 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0i \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 3.525
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 37.154 MHz 26.915 9999973.085
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/clock \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 3.525
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 39.239 MHz 25.485 9999974.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/clock \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 3.850
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 3.525
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u0\/z0 \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 39.944 MHz 25.035 9999974.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/clock \Timer_1:TimerUDB:sT24:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/z0 \Timer_1:TimerUDB:sT24:timerdp:u1\/z0i 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0i \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 3.525
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\CapSense:ClockGen:clock_detect_reg\/q \CapSense:ClockGen:sC8:PRSdp:u0\/cs_addr_0 3.562
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,3) 1 \CapSense:ClockGen:clock_detect_reg\ \CapSense:ClockGen:clock_detect_reg\/clock_0 \CapSense:ClockGen:clock_detect_reg\/q 1.250
Route 1 \CapSense:ClockGen:clock_detect_reg\ \CapSense:ClockGen:clock_detect_reg\/q \CapSense:ClockGen:sC8:PRSdp:u0\/cs_addr_0 2.312
datapathcell2 U(3,3) 1 \CapSense:ClockGen:sC8:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:tmp_ppulse_reg\/q \CapSense:ClockGen:tmp_ppulse_dly\/main_0 4.154
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,2) 1 \CapSense:ClockGen:tmp_ppulse_reg\ \CapSense:ClockGen:tmp_ppulse_reg\/clock_0 \CapSense:ClockGen:tmp_ppulse_reg\/q 1.250
Route 1 \CapSense:ClockGen:tmp_ppulse_reg\ \CapSense:ClockGen:tmp_ppulse_reg\/q \CapSense:ClockGen:tmp_ppulse_dly\/main_0 2.904
macrocell9 U(3,3) 1 \CapSense:ClockGen:tmp_ppulse_dly\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:sC8:PRSdp:u0\/cs_addr_2 4.523
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:sC8:PRSdp:u0\/cs_addr_2 3.273
datapathcell2 U(3,3) 1 \CapSense:ClockGen:sC8:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 4.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 3.286
count7cell U(3,3) 1 \CapSense:ClockGen:ScanSpeed\ REMOVAL 0.000
Clock Skew 0.000
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:UDB:PrescalerDp:u0\/cs_addr_0 5.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:UDB:PrescalerDp:u0\/cs_addr_0 4.163
datapathcell1 U(3,2) 1 \CapSense:ClockGen:UDB:PrescalerDp:u0\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:UDB:PrescalerDp:u0\/z0_comb \CapSense:ClockGen:UDB:PrescalerDp:u0\/cs_addr_1 5.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,2) 1 \CapSense:ClockGen:UDB:PrescalerDp:u0\ \CapSense:ClockGen:UDB:PrescalerDp:u0\/clock \CapSense:ClockGen:UDB:PrescalerDp:u0\/z0_comb 3.270
datapathcell1 U(3,2) 1 \CapSense:ClockGen:UDB:PrescalerDp:u0\ \CapSense:ClockGen:UDB:PrescalerDp:u0\/z0_comb \CapSense:ClockGen:UDB:PrescalerDp:u0\/cs_addr_1 2.282
datapathcell1 U(3,2) 1 \CapSense:ClockGen:UDB:PrescalerDp:u0\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_2\/q \CapSense:MeasureCH0:wndState_2\/main_0 9.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,3) 1 \CapSense:MeasureCH0:wndState_2\ \CapSense:MeasureCH0:wndState_2\/clock_0 \CapSense:MeasureCH0:wndState_2\/q 1.250
Route 1 \CapSense:MeasureCH0:wndState_2\ \CapSense:MeasureCH0:wndState_2\/q \CapSense:MeasureCH0:wndState_2\\D\/main_3 2.307
macrocell28 U(2,3) 1 \CapSense:MeasureCH0:wndState_2\\D\ \CapSense:MeasureCH0:wndState_2\\D\/main_3 \CapSense:MeasureCH0:wndState_2\\D\/q 3.350
Route 1 \CapSense:MeasureCH0:wndState_2\\D\ \CapSense:MeasureCH0:wndState_2\\D\/q \CapSense:MeasureCH0:wndState_2\/main_0 2.287
macrocell27 U(2,3) 1 \CapSense:MeasureCH0:wndState_2\ HOLD 0.000
Clock Skew 0.000
\CapSense:ClockGen:tmp_ppulse_dly\/q \CapSense:ClockGen:clock_detect_reg\/main_0 9.204
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,3) 1 \CapSense:ClockGen:tmp_ppulse_dly\ \CapSense:ClockGen:tmp_ppulse_dly\/clock_0 \CapSense:ClockGen:tmp_ppulse_dly\/q 1.250
Route 1 \CapSense:ClockGen:tmp_ppulse_dly\ \CapSense:ClockGen:tmp_ppulse_dly\/q \CapSense:ClockGen:clock_detect\/main_1 2.310
macrocell2 U(3,3) 1 \CapSense:ClockGen:clock_detect\ \CapSense:ClockGen:clock_detect\/main_1 \CapSense:ClockGen:clock_detect\/q 3.350
Route 1 \CapSense:ClockGen:clock_detect\ \CapSense:ClockGen:clock_detect\/q \CapSense:ClockGen:clock_detect_reg\/main_0 2.294
macrocell3 U(3,3) 1 \CapSense:ClockGen:clock_detect_reg\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_1\/q \CapSense:Net_1603\/main_0 9.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,2) 1 \CapSense:MeasureCH0:wndState_1\ \CapSense:MeasureCH0:wndState_1\/clock_0 \CapSense:MeasureCH0:wndState_1\/q 1.250
Route 1 \CapSense:MeasureCH0:wndState_1\ \CapSense:MeasureCH0:wndState_1\/q \CapSense:MeasureCH0:wndState_3\\D\/main_3 2.601
macrocell29 U(2,2) 1 \CapSense:MeasureCH0:wndState_3\\D\ \CapSense:MeasureCH0:wndState_3\\D\/main_3 \CapSense:MeasureCH0:wndState_3\\D\/q 3.350
Route 1 \CapSense:MeasureCH0:wndState_3\\D\ \CapSense:MeasureCH0:wndState_3\\D\/q \CapSense:Net_1603\/main_0 2.296
macrocell31 U(2,2) 1 \CapSense:Net_1603\ HOLD 0.000
Clock Skew 0.000
\CapSense:MeasureCH0:wndState_1\/q \CapSense:MeasureCH0:wndState_1\/main_0 9.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,2) 1 \CapSense:MeasureCH0:wndState_1\ \CapSense:MeasureCH0:wndState_1\/clock_0 \CapSense:MeasureCH0:wndState_1\/q 1.250
Route 1 \CapSense:MeasureCH0:wndState_1\ \CapSense:MeasureCH0:wndState_1\/q \CapSense:MeasureCH0:wndState_1\\D\/main_4 2.601
macrocell26 U(2,2) 1 \CapSense:MeasureCH0:wndState_1\\D\ \CapSense:MeasureCH0:wndState_1\\D\/main_4 \CapSense:MeasureCH0:wndState_1\\D\/q 3.350
Route 1 \CapSense:MeasureCH0:wndState_1\\D\ \CapSense:MeasureCH0:wndState_1\\D\/q \CapSense:MeasureCH0:wndState_1\/main_0 2.300
macrocell25 U(2,2) 1 \CapSense:MeasureCH0:wndState_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 5.162
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 3.122
statusicell1 U(3,0) 1 \Timer_1:TimerUDB:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 5.172
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 3.132
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 5.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 3.152
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_2 6.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_2 4.035
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 14.882
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 3.132
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_2 \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 14.902
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 3.152
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 17.522
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 3.152
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/clock \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/clock \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:hwEnable_reg\/main_0 4.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:hwEnable_reg\/main_0 2.892
macrocell34 U(2,0) 1 \Timer_1:TimerUDB:hwEnable_reg\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_0 5.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/clock \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 3.270
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_0 2.302
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/clock \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u1\/ci 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/ci \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT24:timerdp:u2\/ci 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_0 6.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/clock \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 1.740
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 2.740
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_0 2.302
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 6.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/clock \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 3.525
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_0 6.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/clock \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u1\/cs_addr_0 3.525
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u0\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_0 7.992
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ \Timer_1:TimerUDB:sT24:timerdp:u0\/clock \Timer_1:TimerUDB:sT24:timerdp:u0\/z0 1.740
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u0\/z0 \Timer_1:TimerUDB:sT24:timerdp:u1\/z0i 0.000
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0i \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 1.210
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 2.740
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u2\/cs_addr_0 2.302
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 8.005
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u1\ \Timer_1:TimerUDB:sT24:timerdp:u1\/clock \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 1.740
Route 1 \Timer_1:TimerUDB:sT24:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT24:timerdp:u1\/z0 \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i 0.000
datapathcell7 U(3,1) 1 \Timer_1:TimerUDB:sT24:timerdp:u2\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0i \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb 2.740
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT24:timerdp:u2\/z0_comb \Timer_1:TimerUDB:sT24:timerdp:u0\/cs_addr_0 3.525
datapathcell5 U(2,0) 1 \Timer_1:TimerUDB:sT24:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 220.459 MHz 4.536 78.797
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 3.286
count7cell U(3,3) 1 \CapSense:ClockGen:ScanSpeed\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 175.377 MHz 5.702 35.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 3.122
statusicell1 U(3,0) 1 \Timer_1:TimerUDB:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 4.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,3) 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/clock_0 \CapSense:ClockGen:inter_reset\/q 1.250
Route 1 \CapSense:ClockGen:inter_reset\ \CapSense:ClockGen:inter_reset\/q \CapSense:ClockGen:ScanSpeed\/reset 3.286
count7cell U(3,3) 1 \CapSense:ClockGen:ScanSpeed\ REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 5.162
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_82 \Control_Reg_1:Sync:ctrl_reg\/control_0 \Timer_1:TimerUDB:rstSts:stsreg\/reset 3.122
statusicell1 U(3,0) 1 \Timer_1:TimerUDB:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000