Static Timing Analysis

Project :	UART_Tx01
Build Time :	07/05/16 11:21:11
Device :	CY8C5868AXI-LP035
Temperature :	-40C - 85/125C
VDDA :	5.50
VDDABUF :	5.50
VDDD :	5.50
VDDIO0 :	5.50
VDDIO1 :	5.50
VDDIO2 :	5.50
VDDIO3 :	5.50
VUSB :	5.50
Voltage :	5.5

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+ Timing Violation Section

No Timing Violations

+ Clock Summary Section

Clock	Domain	Nominal Frequency	Required Frequency	Maximum Frequency	Violation
CyILO	CyILO	1.000 kHz	1.000 kHz	N/A
CyIMO	CyIMO	3.000 MHz	3.000 MHz	N/A
CyMASTER_CLK	CyMASTER_CLK	24.000 MHz	24.000 MHz	N/A
CyBUS_CLK	CyMASTER_CLK	24.000 MHz	24.000 MHz	N/A
Clock_1	CyMASTER_CLK	461.538 kHz	461.538 kHz	61.170 MHz
CyPLL_OUT	CyPLL_OUT	24.000 MHz	24.000 MHz	N/A

+ Register to Register Section

+ Setup Subsection

+ Source Clock : Clock_1 : Positive edge(Required Frequency 461.538 kHz)

+ Destination Clock : Clock_1 : Positive edge(Required Frequency 461.538 kHz)

Path Delay Requirement : 2166.67ns(461.538 kHz)

Source

Destination

FMax

Delay (ns)

Slack (ns)

Violation

\UART_1:BUART:tx_state_0\/q

\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0

61.170 MHz

16.348

2150.319

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell8	U(2,4)	1	\UART_1:BUART:tx_state_0\	\UART_1:BUART:tx_state_0\/clock_0	\UART_1:BUART:tx_state_0\/q	1.250
Route		1	\UART_1:BUART:tx_state_0\	\UART_1:BUART:tx_state_0\/q	\UART_1:BUART:tx_bitclk_enable_pre\/main_1	3.448
macrocell3	U(2,4)	1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/main_1	\UART_1:BUART:tx_bitclk_enable_pre\/q	3.350
Route		1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/q	\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0	2.290
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\		SETUP	6.010
Clock					Skew	0.000

\UART_1:BUART:tx_state_1\/q

\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0

61.870 MHz

16.163

2150.504

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell7	U(3,4)	1	\UART_1:BUART:tx_state_1\	\UART_1:BUART:tx_state_1\/clock_0	\UART_1:BUART:tx_state_1\/q	1.250
Route		1	\UART_1:BUART:tx_state_1\	\UART_1:BUART:tx_state_1\/q	\UART_1:BUART:tx_bitclk_enable_pre\/main_0	3.263
macrocell3	U(2,4)	1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/main_0	\UART_1:BUART:tx_bitclk_enable_pre\/q	3.350
Route		1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/q	\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0	2.290
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\		SETUP	6.010
Clock					Skew	0.000

\UART_1:BUART:tx_state_2\/q

\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0

62.606 MHz

15.973

2150.694

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/clock_0	\UART_1:BUART:tx_state_2\/q	1.250
Route		1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/q	\UART_1:BUART:tx_bitclk_enable_pre\/main_2	3.073
macrocell3	U(2,4)	1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/main_2	\UART_1:BUART:tx_bitclk_enable_pre\/q	3.350
Route		1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/q	\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0	2.290
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\		SETUP	6.010
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0

\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0

62.885 MHz

15.902

2150.765

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0	1.940
Route		1	\UART_1:BUART:txbitcount_0\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0	\UART_1:BUART:tx_bitclk_enable_pre\/main_5	2.312
macrocell3	U(2,4)	1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/main_5	\UART_1:BUART:tx_bitclk_enable_pre\/q	3.350
Route		1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/q	\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0	2.290
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\		SETUP	6.010
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1

\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0

62.893 MHz

15.900

2150.767

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1	1.940
Route		1	\UART_1:BUART:txbitcount_1\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1	\UART_1:BUART:tx_bitclk_enable_pre\/main_4	2.310
macrocell3	U(2,4)	1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/main_4	\UART_1:BUART:tx_bitclk_enable_pre\/q	3.350
Route		1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/q	\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0	2.290
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\		SETUP	6.010
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2

\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0

62.901 MHz

15.898

2150.769

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2	1.940
Route		1	\UART_1:BUART:txbitcount_2\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2	\UART_1:BUART:tx_bitclk_enable_pre\/main_3	2.308
macrocell3	U(2,4)	1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/main_3	\UART_1:BUART:tx_bitclk_enable_pre\/q	3.350
Route		1	\UART_1:BUART:tx_bitclk_enable_pre\	\UART_1:BUART:tx_bitclk_enable_pre\/q	\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0	2.290
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\		SETUP	6.010
Clock					Skew	0.000

\UART_1:BUART:tx_state_0\/q

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load

63.670 MHz

15.706

2150.961

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell8	U(2,4)	1	\UART_1:BUART:tx_state_0\	\UART_1:BUART:tx_state_0\/clock_0	\UART_1:BUART:tx_state_0\/q	1.250
Route		1	\UART_1:BUART:tx_state_0\	\UART_1:BUART:tx_state_0\/q	\UART_1:BUART:counter_load\/main_1	3.429
macrocell2	U(3,4)	1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/main_1	\UART_1:BUART:counter_load\/q	3.350
Route		1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/q	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load	2.317
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\		SETUP	5.360
Clock					Skew	0.000

\UART_1:BUART:tx_bitclk\/q

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load

64.309 MHz

15.550

2151.117

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell10	U(2,4)	1	\UART_1:BUART:tx_bitclk\	\UART_1:BUART:tx_bitclk\/clock_0	\UART_1:BUART:tx_bitclk\/q	1.250
Route		1	\UART_1:BUART:tx_bitclk\	\UART_1:BUART:tx_bitclk\/q	\UART_1:BUART:counter_load\/main_3	3.273
macrocell2	U(3,4)	1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/main_3	\UART_1:BUART:counter_load\/q	3.350
Route		1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/q	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load	2.317
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\		SETUP	5.360
Clock					Skew	0.000

\UART_1:BUART:tx_state_1\/q

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load

64.350 MHz

15.540

2151.127

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell7	U(3,4)	1	\UART_1:BUART:tx_state_1\	\UART_1:BUART:tx_state_1\/clock_0	\UART_1:BUART:tx_state_1\/q	1.250
Route		1	\UART_1:BUART:tx_state_1\	\UART_1:BUART:tx_state_1\/q	\UART_1:BUART:counter_load\/main_0	3.263
macrocell2	U(3,4)	1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/main_0	\UART_1:BUART:counter_load\/q	3.350
Route		1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/q	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load	2.317
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\		SETUP	5.360
Clock					Skew	0.000

\UART_1:BUART:tx_state_2\/q

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load

65.151 MHz

15.349

2151.318

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/clock_0	\UART_1:BUART:tx_state_2\/q	1.250
Route		1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/q	\UART_1:BUART:counter_load\/main_2	3.072
macrocell2	U(3,4)	1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/main_2	\UART_1:BUART:counter_load\/q	3.350
Route		1	\UART_1:BUART:counter_load\	\UART_1:BUART:counter_load\/q	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load	2.317
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\		SETUP	5.360
Clock					Skew	0.000

+ Hold Subsection

+ Source Clock : Clock_1 : Positive edge

+ Destination Clock : Clock_1 : Positive edge

Source

Destination

Slack (ns)

Violation

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2

\UART_1:BUART:tx_bitclk\/main_3

2.928

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2	0.620
Route		1	\UART_1:BUART:txbitcount_2\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2	\UART_1:BUART:tx_bitclk\/main_3	2.308
macrocell10	U(2,4)	1	\UART_1:BUART:tx_bitclk\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1

\UART_1:BUART:tx_bitclk\/main_4

2.930

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1	0.620
Route		1	\UART_1:BUART:txbitcount_1\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1	\UART_1:BUART:tx_bitclk\/main_4	2.310
macrocell10	U(2,4)	1	\UART_1:BUART:tx_bitclk\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0

\UART_1:BUART:tx_bitclk\/main_5

2.932

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0	0.620
Route		1	\UART_1:BUART:txbitcount_0\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0	\UART_1:BUART:tx_bitclk\/main_5	2.312
macrocell10	U(2,4)	1	\UART_1:BUART:tx_bitclk\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc

\UART_1:BUART:tx_state_1\/main_4

3.314

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc	0.650
Route		1	\UART_1:BUART:tx_counter_tc\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc	\UART_1:BUART:tx_state_1\/main_4	2.664
macrocell7	U(3,4)	1	\UART_1:BUART:tx_state_1\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc

\UART_1:BUART:txn\/main_6

3.318

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc	0.650
Route		1	\UART_1:BUART:tx_counter_tc\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc	\UART_1:BUART:txn\/main_6	2.668
macrocell6	U(2,4)	1	\UART_1:BUART:txn\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc

\UART_1:BUART:tx_state_2\/main_4

3.318

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
count7cell	U(2,4)	1	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc	0.650
Route		1	\UART_1:BUART:tx_counter_tc\	\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/tc	\UART_1:BUART:tx_state_2\/main_4	2.668
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:sTX:TxShifter:u0\/so_comb

\UART_1:BUART:txn\/main_3

3.816

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
datapathcell1	U(2,4)	1	\UART_1:BUART:sTX:TxShifter:u0\	\UART_1:BUART:sTX:TxShifter:u0\/clock	\UART_1:BUART:sTX:TxShifter:u0\/so_comb	1.510
Route		1	\UART_1:BUART:tx_shift_out\	\UART_1:BUART:sTX:TxShifter:u0\/so_comb	\UART_1:BUART:txn\/main_3	2.306
macrocell6	U(2,4)	1	\UART_1:BUART:txn\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:txn\/q

\UART_1:BUART:txn\/main_0

3.830

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell6	U(2,4)	1	\UART_1:BUART:txn\	\UART_1:BUART:txn\/clock_0	\UART_1:BUART:txn\/q	1.250
macrocell6	U(2,4)	1	\UART_1:BUART:txn\	\UART_1:BUART:txn\/q	\UART_1:BUART:txn\/main_0	2.580
macrocell6	U(2,4)	1	\UART_1:BUART:txn\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:tx_state_2\/q

\UART_1:BUART:txn\/main_4

4.180

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/clock_0	\UART_1:BUART:tx_state_2\/q	1.250
Route		1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/q	\UART_1:BUART:txn\/main_4	2.930
macrocell6	U(2,4)	1	\UART_1:BUART:txn\		HOLD	0.000
Clock					Skew	0.000

\UART_1:BUART:tx_state_2\/q

\UART_1:BUART:tx_state_2\/main_2

4.180

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/clock_0	\UART_1:BUART:tx_state_2\/q	1.250
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\	\UART_1:BUART:tx_state_2\/q	\UART_1:BUART:tx_state_2\/main_2	2.930
macrocell9	U(2,4)	1	\UART_1:BUART:tx_state_2\		HOLD	0.000
Clock					Skew	0.000

+ Clock To Output Section

Source

Destination

Delay (ns)

\UART_1:BUART:txn\/q

TX(0)_PAD

28.437

Type	Location	Fanout	Instance/Net	Source	Dest	Delay (ns)
macrocell6	U(2,4)	1	\UART_1:BUART:txn\	\UART_1:BUART:txn\/clock_0	\UART_1:BUART:txn\/q	1.250
Route		1	\UART_1:BUART:txn\	\UART_1:BUART:txn\/q	Net_29/main_0	2.590
macrocell1	U(3,4)	1	Net_29	Net_29/main_0	Net_29/q	3.350
Route		1	Net_29	Net_29/q	TX(0)/pin_input	5.445
iocell8	P0[1]	1	TX(0)	TX(0)/pin_input	TX(0)/pad_out	15.802
Route		1	TX(0)_PAD	TX(0)/pad_out	TX(0)_PAD	0.000
Clock					Clock path delay	0.000