Static Timing Analysis

Project : 17bit_demal_DMA
Build Time : 06/16/21 21:21:38
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 64.000 MHz 64.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 64.000 MHz 64.000 MHz N/A
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz 119.818 MHz
Clock_1 CyMASTER_CLK 12.000 MHz 12.800 MHz 62.716 MHz
ADC_DelSig_theACLK CyMASTER_CLK 1.391 MHz 1.391 MHz N/A
CyPLL_OUT CyPLL_OUT 64.000 MHz 64.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 78.125ns(12.8 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 62.716 MHz 15.945 62.180
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \Delay_PWM:PWMUDB:tc_i\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.085
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\Delay_PWM:PWMUDB:runmode_enable\/q \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 64.675 MHz 15.462 62.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \Delay_PWM:PWMUDB:runmode_enable\ \Delay_PWM:PWMUDB:runmode_enable\/clock_0 \Delay_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \Delay_PWM:PWMUDB:runmode_enable\ \Delay_PWM:PWMUDB:runmode_enable\/q \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 4.852
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 67.866 MHz 14.735 63.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \Delay_PWM:PWMUDB:tc_i\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.085
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:genblk8:stsreg\/status_2 78.315 MHz 12.769 65.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \Delay_PWM:PWMUDB:tc_i\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:status_2\/main_1 3.099
macrocell2 U(2,1) 1 \Delay_PWM:PWMUDB:status_2\ \Delay_PWM:PWMUDB:status_2\/main_1 \Delay_PWM:PWMUDB:status_2\/q 3.350
Route 1 \Delay_PWM:PWMUDB:status_2\ \Delay_PWM:PWMUDB:status_2\/q \Delay_PWM:PWMUDB:genblk8:stsreg\/status_2 2.320
statusicell1 U(2,1) 1 \Delay_PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 79.083 MHz 12.645 65.480
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \Delay_PWM:PWMUDB:tc_i\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.085
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 80.096 MHz 12.485 65.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.z0__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/z0 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0i \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 2.925
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ SETUP 6.060
Clock Skew 0.000
\Delay_PWM:PWMUDB:runmode_enable\/q \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 82.223 MHz 12.162 65.963
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \Delay_PWM:PWMUDB:runmode_enable\ \Delay_PWM:PWMUDB:runmode_enable\/clock_0 \Delay_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \Delay_PWM:PWMUDB:runmode_enable\ \Delay_PWM:PWMUDB:runmode_enable\/q \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 4.852
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:genblk8:stsreg\/status_2 86.513 MHz 11.559 66.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \Delay_PWM:PWMUDB:tc_i\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:status_2\/main_1 3.099
macrocell2 U(2,1) 1 \Delay_PWM:PWMUDB:status_2\ \Delay_PWM:PWMUDB:status_2\/main_1 \Delay_PWM:PWMUDB:status_2\/q 3.350
Route 1 \Delay_PWM:PWMUDB:status_2\ \Delay_PWM:PWMUDB:status_2\/q \Delay_PWM:PWMUDB:genblk8:stsreg\/status_2 2.320
statusicell1 U(2,1) 1 \Delay_PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 87.451 MHz 11.435 66.690
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \Delay_PWM:PWMUDB:tc_i\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.085
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 88.692 MHz 11.275 66.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/z0_comb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 2.925
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ SETUP 6.060
Clock Skew 0.000
Path Delay Requirement : 15.625ns(64 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Start_Reg:Sync:ctrl_reg\/control_0 \EdgeDetect:last\/main_0 119.818 MHz 8.346 7.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 \EdgeDetect:last\/main_0 2.786
macrocell11 U(2,1) 1 \EdgeDetect:last\ SETUP 3.510
Clock Skew 0.000
\Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:trig_last\/main_2 119.818 MHz 8.346 7.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:trig_last\/main_2 2.786
macrocell12 U(2,1) 1 \Delay_PWM:PWMUDB:trig_last\ SETUP 3.510
Clock Skew 0.000
\Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:runmode_enable\/main_2 119.818 MHz 8.346 7.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:runmode_enable\/main_2 2.786
macrocell13 U(2,1) 1 \Delay_PWM:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 2.140
Route 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \Delay_PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:genblk1:ctrlreg\/control_7 \Delay_PWM:PWMUDB:runmode_enable\/main_3 2.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \Delay_PWM:PWMUDB:genblk1:ctrlreg\ \Delay_PWM:PWMUDB:genblk1:ctrlreg\/clock \Delay_PWM:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \Delay_PWM:PWMUDB:control_7\ \Delay_PWM:PWMUDB:genblk1:ctrlreg\/control_7 \Delay_PWM:PWMUDB:runmode_enable\/main_3 2.348
macrocell13 U(2,1) 1 \Delay_PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out Net_71_1/clk_en 2.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.350
Route 1 Net_12 \Sync_2:genblk1[0]:INST\/out Net_71_1/clk_en 2.615
macrocell9 U(3,2) 1 Net_71_1 HOLD 0.000
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out Net_71_0/clk_en 2.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,2) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 0.350
Route 1 Net_12 \Sync_2:genblk1[0]:INST\/out Net_71_0/clk_en 2.615
macrocell10 U(3,2) 1 Net_71_0 HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb \Delay_PWM:PWMUDB:prevCompare1\/main_0 3.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb 0.720
Route 1 \Delay_PWM:PWMUDB:cmp1_eq\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb \Delay_PWM:PWMUDB:prevCompare1\/main_0 2.298
macrocell14 U(2,1) 1 \Delay_PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb \Delay_PWM:PWMUDB:status_0\/main_1 3.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb 0.720
Route 1 \Delay_PWM:PWMUDB:cmp1_eq\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb \Delay_PWM:PWMUDB:status_0\/main_1 2.298
macrocell15 U(2,1) 1 \Delay_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb Net_332/main_1 3.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb 0.720
Route 1 \Delay_PWM:PWMUDB:cmp1_eq\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/ce0_comb Net_332/main_1 2.298
macrocell16 U(2,1) 1 Net_332 HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb \Delay_PWM:PWMUDB:prevCompare1\/main_1 3.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb 0.780
Route 1 \Delay_PWM:PWMUDB:cmp1_less\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb \Delay_PWM:PWMUDB:prevCompare1\/main_1 2.292
macrocell14 U(2,1) 1 \Delay_PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb \Delay_PWM:PWMUDB:status_0\/main_2 3.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb 0.780
Route 1 \Delay_PWM:PWMUDB:cmp1_less\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb \Delay_PWM:PWMUDB:status_0\/main_2 2.292
macrocell15 U(2,1) 1 \Delay_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb Net_332/main_2 3.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \Delay_PWM:PWMUDB:sP16:pwmdp:u1\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/clock \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb 0.780
Route 1 \Delay_PWM:PWMUDB:cmp1_less\ \Delay_PWM:PWMUDB:sP16:pwmdp:u1\/cl0_comb Net_332/main_2 2.292
macrocell16 U(2,1) 1 Net_332 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Start_Reg:Sync:ctrl_reg\/control_0 \EdgeDetect:last\/main_0 3.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 \EdgeDetect:last\/main_0 2.786
macrocell11 U(2,1) 1 \EdgeDetect:last\ HOLD 0.000
Clock Skew 0.000
\Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:trig_last\/main_2 3.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:trig_last\/main_2 2.786
macrocell12 U(2,1) 1 \Delay_PWM:PWMUDB:trig_last\ HOLD 0.000
Clock Skew 0.000
\Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:runmode_enable\/main_2 3.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 \Delay_PWM:PWMUDB:runmode_enable\/main_2 2.786
macrocell13 U(2,1) 1 \Delay_PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_332/q SOC(0)_PAD 28.874
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,1) 1 Net_332 Net_332/clock_0 Net_332/q 1.250
Route 1 Net_332 Net_332/q Net_341/main_1 2.297
macrocell3 U(2,1) 1 Net_341 Net_341/main_1 Net_341/q 3.350
Route 1 Net_341 Net_341/q SOC(0)/pin_input 7.386
iocell2 P3[6] 1 SOC(0) SOC(0)/pin_input SOC(0)/pad_out 14.591
Route 1 SOC(0)_PAD SOC(0)/pad_out SOC(0)_PAD 0.000
Clock Clock path delay 0.000
Net_71_1/q LUT1(0)_PAD 25.209
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,2) 1 Net_71_1 Net_71_1/clock_0 Net_71_1/q 1.250
Route 1 Net_71_1 Net_71_1/q LUT1(0)/pin_input 8.578
iocell7 P1[7] 1 LUT1(0) LUT1(0)/pin_input LUT1(0)/pad_out 15.381
Route 1 LUT1(0)_PAD LUT1(0)/pad_out LUT1(0)_PAD 0.000
Clock Clock path delay 0.000
Net_71_0/q LUT0(0)_PAD 24.891
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,2) 1 Net_71_0 Net_71_0/clock_0 Net_71_0/q 1.250
Route 1 Net_71_0 Net_71_0/q LUT0(0)/pin_input 8.570
iocell6 P1[6] 1 LUT0(0) LUT0(0)/pin_input LUT0(0)/pad_out 15.071
Route 1 LUT0(0)_PAD LUT0(0)/pad_out LUT0(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\Start_Reg:Sync:ctrl_reg\/control_0 SOC(0)_PAD 30.167
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \Start_Reg:Sync:ctrl_reg\ \Start_Reg:Sync:ctrl_reg\/busclk \Start_Reg:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_140 \Start_Reg:Sync:ctrl_reg\/control_0 Net_341/main_0 2.790
macrocell3 U(2,1) 1 Net_341 Net_341/main_0 Net_341/q 3.350
Route 1 Net_341 Net_341/q SOC(0)/pin_input 7.386
iocell2 P3[6] 1 SOC(0) SOC(0)/pin_input SOC(0)/pad_out 14.591
Route 1 SOC(0)_PAD SOC(0)/pad_out SOC(0)_PAD 0.000
Clock Clock path delay 0.000
+ \ADC_DelSig:DSM\/dec_clock
Source Destination Delay (ns)
\ADC_DelSig:DEC\/interrupt EOC(0)_PAD 20.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
decimatorcell F(Decimator,0) 1 \ADC_DelSig:DEC\ \ADC_DelSig:DEC\/aclock \ADC_DelSig:DEC\/interrupt 1.000
Route 1 Net_98 \ADC_DelSig:DEC\/interrupt EOC(0)/pin_input 3.975
iocell3 P3[7] 1 EOC(0) EOC(0)/pin_input EOC(0)/pad_out 15.161
Route 1 EOC(0)_PAD EOC(0)/pad_out EOC(0)_PAD 0.000
Clock Clock path delay 0.000