Static Timing Analysis

Project : TFT_Test
Build Time : 07/09/14 15:14:39
Device : CY8C5868LTI-LP039
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyMASTER_CLK 24.000 MHz 24.000 MHz 56.796 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\MyTFTIntf_1:GraphLcd8:Lsb\/z0_comb \MyTFTIntf_1:StsReg\/status_1 56.796 MHz 17.607 24.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/z0_comb 3.850
Route 1 \MyTFTIntf_1:z0_detect\ \MyTFTIntf_1:GraphLcd8:Lsb\/z0_comb \MyTFTIntf_1:status_1\/main_4 2.784
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_4 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:StsReg\/status_1 6.053
statuscell2 U(3,1) 1 \MyTFTIntf_1:StsReg\ SETUP 1.570
Clock Skew 0.000
\MyTFTIntf_1:state_2\/q \MyTFTIntf_1:GraphLcd8:Lsb\/cs_addr_2 61.789 MHz 16.184 25.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,1) 1 \MyTFTIntf_1:state_2\ \MyTFTIntf_1:state_2\/clock_0 \MyTFTIntf_1:state_2\/q 1.250
Route 1 \MyTFTIntf_1:state_2\ \MyTFTIntf_1:state_2\/q \MyTFTIntf_1:GraphLcd8:Lsb\/cs_addr_2 3.404
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ SETUP 11.530
Clock Skew 0.000
\MyTFTIntf_1:state_1\/q \MyTFTIntf_1:GraphLcd8:Lsb\/cs_addr_1 61.797 MHz 16.182 25.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \MyTFTIntf_1:state_1\ \MyTFTIntf_1:state_1\/clock_0 \MyTFTIntf_1:state_1\/q 1.250
Route 1 \MyTFTIntf_1:state_1\ \MyTFTIntf_1:state_1\/q \MyTFTIntf_1:GraphLcd8:Lsb\/cs_addr_1 3.402
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ SETUP 11.530
Clock Skew 0.000
\MyTFTIntf_1:state_0\/q \MyTFTIntf_1:GraphLcd8:Lsb\/cs_addr_0 61.862 MHz 16.165 25.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \MyTFTIntf_1:state_0\ \MyTFTIntf_1:state_0\/clock_0 \MyTFTIntf_1:state_0\/q 1.250
Route 1 \MyTFTIntf_1:state_0\ \MyTFTIntf_1:state_0\/q \MyTFTIntf_1:GraphLcd8:Lsb\/cs_addr_0 3.385
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ SETUP 11.530
Clock Skew 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/z0_comb \MyTFTIntf_1:LsbReg\/clk_en 62.873 MHz 15.905 25.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/z0_comb 3.850
Route 1 \MyTFTIntf_1:z0_detect\ \MyTFTIntf_1:GraphLcd8:Lsb\/z0_comb \MyTFTIntf_1:status_1\/main_4 2.784
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_4 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:LsbReg\/clk_en 3.821
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 2.100
Clock Skew 0.000
\MyTFTIntf_1:state_1\/q \MyTFTIntf_1:StsReg\/status_1 63.877 MHz 15.655 26.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \MyTFTIntf_1:state_1\ \MyTFTIntf_1:state_1\/clock_0 \MyTFTIntf_1:state_1\/q 1.250
Route 1 \MyTFTIntf_1:state_1\ \MyTFTIntf_1:state_1\/q \MyTFTIntf_1:status_1\/main_2 3.432
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_2 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:StsReg\/status_1 6.053
statuscell2 U(3,1) 1 \MyTFTIntf_1:StsReg\ SETUP 1.570
Clock Skew 0.000
\MyTFTIntf_1:state_2\/q \MyTFTIntf_1:StsReg\/status_1 63.984 MHz 15.629 26.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,1) 1 \MyTFTIntf_1:state_2\ \MyTFTIntf_1:state_2\/clock_0 \MyTFTIntf_1:state_2\/q 1.250
Route 1 \MyTFTIntf_1:state_2\ \MyTFTIntf_1:state_2\/q \MyTFTIntf_1:status_1\/main_1 3.406
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_1 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:StsReg\/status_1 6.053
statuscell2 U(3,1) 1 \MyTFTIntf_1:StsReg\ SETUP 1.570
Clock Skew 0.000
\MyTFTIntf_1:state_0\/q \MyTFTIntf_1:StsReg\/status_1 64.098 MHz 15.601 26.066
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \MyTFTIntf_1:state_0\ \MyTFTIntf_1:state_0\/clock_0 \MyTFTIntf_1:state_0\/q 1.250
Route 1 \MyTFTIntf_1:state_0\ \MyTFTIntf_1:state_0\/q \MyTFTIntf_1:status_1\/main_3 3.378
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_3 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:StsReg\/status_1 6.053
statuscell2 U(3,1) 1 \MyTFTIntf_1:StsReg\ SETUP 1.570
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q \MyTFTIntf_1:StsReg\/status_1 66.225 MHz 15.100 26.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q \MyTFTIntf_1:status_1\/main_0 2.877
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_0 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:StsReg\/status_1 6.053
statuscell2 U(3,1) 1 \MyTFTIntf_1:StsReg\ SETUP 1.570
Clock Skew 0.000
\MyTFTIntf_1:state_1\/q \MyTFTIntf_1:LsbReg\/clk_en 71.669 MHz 13.953 27.714
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,1) 1 \MyTFTIntf_1:state_1\ \MyTFTIntf_1:state_1\/clock_0 \MyTFTIntf_1:state_1\/q 1.250
Route 1 \MyTFTIntf_1:state_1\ \MyTFTIntf_1:state_1\/q \MyTFTIntf_1:status_1\/main_2 3.432
macrocell11 U(2,1) 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/main_2 \MyTFTIntf_1:status_1\/q 3.350
Route 1 \MyTFTIntf_1:status_1\ \MyTFTIntf_1:status_1\/q \MyTFTIntf_1:LsbReg\/clk_en 3.821
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 2.100
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_0 Net_132/main_5 3.659
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_0 1.360
Route 1 Net_86_0 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_0 Net_132/main_5 2.299
macrocell5 U(3,1) 1 Net_132 HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q Net_127/main_0 4.127
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q Net_127/main_0 2.877
macrocell1 U(2,1) 1 Net_127 HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_1\/main_1 4.127
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_1\/main_1 2.877
macrocell8 U(2,1) 1 \MyTFTIntf_1:state_1\ HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_3\/main_1 4.127
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_3\/main_1 2.877
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q Net_130/main_0 4.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q Net_130/main_0 2.881
macrocell3 U(3,1) 1 Net_130 HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q Net_131/main_0 4.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q Net_131/main_0 2.881
macrocell4 U(3,1) 1 Net_131 HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_0\/main_1 4.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_0\/main_1 2.881
macrocell7 U(3,1) 1 \MyTFTIntf_1:state_0\ HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q Net_129/main_0 4.133
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q Net_129/main_0 2.883
macrocell2 U(3,1) 1 Net_129 HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q Net_132/main_0 4.133
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q Net_132/main_0 2.883
macrocell5 U(3,1) 1 Net_132 HOLD 0.000
Clock Skew 0.000
\MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_2\/main_0 4.133
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/clock_0 \MyTFTIntf_1:state_3\/q 1.250
Route 1 \MyTFTIntf_1:state_3\ \MyTFTIntf_1:state_3\/q \MyTFTIntf_1:state_2\/main_0 2.883
macrocell9 U(3,1) 1 \MyTFTIntf_1:state_2\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_1
Source Destination Delay (ns)
d(2)_PAD:in \MyTFTIntf_1:LsbReg\/status_2 19.649
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(2)_PAD d(2)_PAD:in d(2)/pad_in 0.000
iocell9 P12[4] 1 d(2) d(2)/pad_in d(2)/fb 9.290
Route 1 Net_133_2 d(2)/fb \MyTFTIntf_1:LsbReg\/status_2 8.789
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(3)_PAD:in \MyTFTIntf_1:LsbReg\/status_3 17.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(3)_PAD d(3)_PAD:in d(3)/pad_in 0.000
iocell10 P12[5] 1 d(3) d(3)/pad_in d(3)/fb 7.440
Route 1 Net_133_3 d(3)/fb \MyTFTIntf_1:LsbReg\/status_3 8.785
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(1)_PAD:in \MyTFTIntf_1:LsbReg\/status_1 16.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(1)_PAD d(1)_PAD:in d(1)/pad_in 0.000
iocell8 P12[3] 1 d(1) d(1)/pad_in d(1)/fb 8.430
Route 1 Net_133_1 d(1)/fb \MyTFTIntf_1:LsbReg\/status_1 6.962
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(4)_PAD:in \MyTFTIntf_1:LsbReg\/status_4 16.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(4)_PAD d(4)_PAD:in d(4)/pad_in 0.000
iocell11 P12[6] 1 d(4) d(4)/pad_in d(4)/fb 7.337
Route 1 Net_133_4 d(4)/fb \MyTFTIntf_1:LsbReg\/status_4 7.111
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(0)_PAD:in \MyTFTIntf_1:LsbReg\/status_0 15.681
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(0)_PAD d(0)_PAD:in d(0)/pad_in 0.000
iocell7 P12[2] 1 d(0) d(0)/pad_in d(0)/fb 7.315
Route 1 Net_133_0 d(0)/fb \MyTFTIntf_1:LsbReg\/status_0 6.796
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(6)_PAD:in \MyTFTIntf_1:LsbReg\/status_6 15.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(6)_PAD d(6)_PAD:in d(6)/pad_in 0.000
iocell13 P1[7] 1 d(6) d(6)/pad_in d(6)/fb 7.089
Route 1 Net_133_6 d(6)/fb \MyTFTIntf_1:LsbReg\/status_6 6.769
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(5)_PAD:in \MyTFTIntf_1:LsbReg\/status_5 15.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(5)_PAD d(5)_PAD:in d(5)/pad_in 0.000
iocell12 P12[7] 1 d(5) d(5)/pad_in d(5)/fb 7.271
Route 1 Net_133_5 d(5)/fb \MyTFTIntf_1:LsbReg\/status_5 6.469
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
d(7)_PAD:in \MyTFTIntf_1:LsbReg\/status_7 13.059
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 d(7)_PAD d(7)_PAD:in d(7)/pad_in 0.000
iocell14 P3[0] 1 d(7) d(7)/pad_in d(7)/fb 6.324
Route 1 Net_133_7 d(7)/fb \MyTFTIntf_1:LsbReg\/status_7 5.165
statuscell1 U(2,1) 1 \MyTFTIntf_1:LsbReg\ SETUP 1.570
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_2 d(2)_PAD:out 27.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_2 1.690
Route 1 Net_86_2 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_2 d(2)/pin_input 9.617
iocell9 P12[4] 1 d(2) d(2)/pin_input d(2)/pad_out 16.615
Route 1 d(2)_PAD d(2)/pad_out d(2)_PAD:out 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_4 d(4)_PAD:out 27.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_4 1.690
Route 1 Net_86_4 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_4 d(4)/pin_input 9.635
iocell11 P12[6] 1 d(4) d(4)/pin_input d(4)/pad_out 16.220
Route 1 d(4)_PAD d(4)/pad_out d(4)_PAD:out 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_5 d(5)_PAD:out 25.852
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_5 1.690
Route 1 Net_86_5 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_5 d(5)/pin_input 7.195
iocell12 P12[7] 1 d(5) d(5)/pin_input d(5)/pad_out 16.967
Route 1 d(5)_PAD d(5)/pad_out d(5)_PAD:out 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_3 d(3)_PAD:out 25.085
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_3 1.690
Route 1 Net_86_3 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_3 d(3)/pin_input 7.357
iocell10 P12[5] 1 d(3) d(3)/pin_input d(3)/pad_out 16.038
Route 1 d(3)_PAD d(3)/pad_out d(3)_PAD:out 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_1 d(1)_PAD:out 24.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_1 1.690
Route 1 Net_86_1 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_1 d(1)/pin_input 6.403
iocell8 P12[3] 1 d(1) d(1)/pin_input d(1)/pad_out 16.196
Route 1 d(1)_PAD d(1)/pad_out d(1)_PAD:out 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_6 d(6)_PAD:out 24.043
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_6 1.690
Route 1 Net_86_6 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_6 d(6)/pin_input 6.972
iocell13 P1[7] 1 d(6) d(6)/pin_input d(6)/pad_out 15.381
Route 1 d(6)_PAD d(6)/pad_out d(6)_PAD:out 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_0 d(0)_PAD:out 23.189
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_0 1.690
Route 1 Net_86_0 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_0 d(0)/pin_input 5.833
iocell7 P12[2] 1 d(0) d(0)/pin_input d(0)/pad_out 15.666
Route 1 d(0)_PAD d(0)/pad_out d(0)_PAD:out 0.000
Clock Clock path delay 0.000
Net_132/q RS(0)_PAD 22.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,1) 1 Net_132 Net_132/clock_0 Net_132/q 1.250
Route 1 Net_132 Net_132/q RS(0)/pin_input 6.092
iocell5 P3[2] 1 RS(0) RS(0)/pin_input RS(0)/pad_out 14.995
Route 1 RS(0)_PAD RS(0)/pad_out RS(0)_PAD 0.000
Clock Clock path delay 0.000
\MyTFTIntf_1:GraphLcd8:Lsb\/p_out_7 d(7)_PAD:out 22.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \MyTFTIntf_1:GraphLcd8:Lsb\ \MyTFTIntf_1:GraphLcd8:Lsb\/clock \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_7 1.690
Route 1 Net_86_7 \MyTFTIntf_1:GraphLcd8:Lsb\/p_out_7 d(7)/pin_input 5.781
iocell14 P3[0] 1 d(7) d(7)/pin_input d(7)/pad_out 14.620
Route 1 d(7)_PAD d(7)/pad_out d(7)_PAD:out 0.000
Clock Clock path delay 0.000
Net_129/q CS(0)_PAD 22.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,1) 1 Net_129 Net_129/clock_0 Net_129/q 1.250
Route 1 Net_129 Net_129/q CS(0)/pin_input 5.835
iocell1 P3[1] 1 CS(0) CS(0)/pin_input CS(0)/pad_out 14.979
Route 1 CS(0)_PAD CS(0)/pad_out CS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_130/q WR(0)_PAD 22.040
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,1) 1 Net_130 Net_130/clock_0 Net_130/q 1.250
Route 1 Net_130 Net_130/q WR(0)/pin_input 6.199
iocell6 P3[3] 1 WR(0) WR(0)/pin_input WR(0)/pad_out 14.591
Route 1 WR(0)_PAD WR(0)/pad_out WR(0)_PAD 0.000
Clock Clock path delay 0.000
Net_131/q RD(0)_PAD 22.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 Net_131 Net_131/clock_0 Net_131/q 1.250
Route 1 Net_131 Net_131/q RD(0)/pin_input 5.788
iocell3 P3[4] 1 RD(0) RD(0)/pin_input RD(0)/pad_out 14.987
Route 1 RD(0)_PAD RD(0)/pad_out RD(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock To Output Enable Section
+ Clock_1
Source Destination Type Delay (ns)
Net_127/q d(3)_PAD:out TURN ON 26.960
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(3)/oe 6.630
iocell10 P12[5] 1 d(3) d(3)/oe d(3)/pad_out 19.080
Route 1 d(3)_PAD d(3)/pad_out d(3)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(3)_PAD:out TURN OFF 26.960
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(3)/oe 6.630
iocell10 P12[5] 1 d(3) d(3)/oe d(3)/pad_out 19.080
Route 1 d(3)_PAD d(3)/pad_out d(3)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(0)_PAD:out TURN ON 26.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(0)/oe 6.630
iocell7 P12[2] 1 d(0) d(0)/oe d(0)/pad_out 18.903
Route 1 d(0)_PAD d(0)/pad_out d(0)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(0)_PAD:out TURN OFF 26.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(0)/oe 6.630
iocell7 P12[2] 1 d(0) d(0)/oe d(0)/pad_out 18.903
Route 1 d(0)_PAD d(0)/pad_out d(0)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(2)_PAD:out TURN ON 26.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(2)/oe 6.630
iocell9 P12[4] 1 d(2) d(2)/oe d(2)/pad_out 18.771
Route 1 d(2)_PAD d(2)/pad_out d(2)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(2)_PAD:out TURN OFF 26.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(2)/oe 6.630
iocell9 P12[4] 1 d(2) d(2)/oe d(2)/pad_out 18.771
Route 1 d(2)_PAD d(2)/pad_out d(2)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(1)_PAD:out TURN ON 26.083
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(1)/oe 6.630
iocell8 P12[3] 1 d(1) d(1)/oe d(1)/pad_out 18.203
Route 1 d(1)_PAD d(1)/pad_out d(1)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(1)_PAD:out TURN OFF 26.083
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(1)/oe 6.630
iocell8 P12[3] 1 d(1) d(1)/oe d(1)/pad_out 18.203
Route 1 d(1)_PAD d(1)/pad_out d(1)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(4)_PAD:out TURN ON 25.599
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(4)/oe 6.630
iocell11 P12[6] 1 d(4) d(4)/oe d(4)/pad_out 17.719
Route 1 d(4)_PAD d(4)/pad_out d(4)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(4)_PAD:out TURN OFF 25.599
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(4)/oe 6.630
iocell11 P12[6] 1 d(4) d(4)/oe d(4)/pad_out 17.719
Route 1 d(4)_PAD d(4)/pad_out d(4)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(5)_PAD:out TURN ON 25.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(5)/oe 6.630
iocell12 P12[7] 1 d(5) d(5)/oe d(5)/pad_out 17.654
Route 1 d(5)_PAD d(5)/pad_out d(5)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(5)_PAD:out TURN OFF 25.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(5)/oe 6.630
iocell12 P12[7] 1 d(5) d(5)/oe d(5)/pad_out 17.654
Route 1 d(5)_PAD d(5)/pad_out d(5)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(6)_PAD:out TURN ON 25.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(6)/oe 7.157
iocell13 P1[7] 1 d(6) d(6)/oe d(6)/pad_out 17.094
Route 1 d(6)_PAD d(6)/pad_out d(6)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(6)_PAD:out TURN OFF 25.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(6)/oe 7.157
iocell13 P1[7] 1 d(6) d(6)/oe d(6)/pad_out 17.094
Route 1 d(6)_PAD d(6)/pad_out d(6)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(7)_PAD:out TURN ON 24.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(7)/oe 6.522
iocell14 P3[0] 1 d(7) d(7)/oe d(7)/pad_out 16.500
Route 1 d(7)_PAD d(7)/pad_out d(7)_PAD:out 0.000
Clock Clock path delay 0.000
Net_127/q d(7)_PAD:out TURN OFF 24.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,1) 1 Net_127 Net_127/clock_0 Net_127/q 1.250
Route 1 Net_127 Net_127/q d(7)/oe 6.522
iocell14 P3[0] 1 d(7) d(7)/oe d(7)/pad_out 16.500
Route 1 d(7)_PAD d(7)/pad_out d(7)_PAD:out 0.000
Clock Clock path delay 0.000