Static Timing Analysis

Project : Application
Build Time : 05/27/17 13:53:52
Device : CY8C5267AXI-LP051
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 3.30
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 44.000 MHz 44.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 44.000 MHz 44.000 MHz 74.901 MHz
ETH_IntClock CyMASTER_CLK 22.000 MHz 22.000 MHz 50.259 MHz
URT_IntClock CyMASTER_CLK 923.077 kHz 936.170 kHz 45.595 MHz
ETC CyMASTER_CLK 20.005  Hz 20.005  Hz N/A
LDON_CK CyMASTER_CLK 0.700  Hz 0.700  Hz N/A
CyPLL_OUT CyPLL_OUT 44.000 MHz 44.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A
ETC(routed) ETC(routed) 20.005  Hz 20.005  Hz N/A
LDON_CK(routed) LDON_CK(routed) 0.700  Hz 0.700  Hz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 22.7273ns(44 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
URX(0)_SYNC/out \URT:BUART:sRX:RxShifter:u0\/route_si 74.901 MHz 13.351 9.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_postpoll\/main_2 3.267
macrocell13 U(2,0) 1 \URT:BUART:rx_postpoll\ \URT:BUART:rx_postpoll\/main_2 \URT:BUART:rx_postpoll\/q 3.350
Route 1 \URT:BUART:rx_postpoll\ \URT:BUART:rx_postpoll\/q \URT:BUART:sRX:RxShifter:u0\/route_si 2.244
datapathcell4 U(3,0) 1 \URT:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_state_0\/main_10 127.779 MHz 7.826 14.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_state_0\/main_10 3.296
macrocell33 U(3,0) 1 \URT:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_state_2\/main_9 127.779 MHz 7.826 14.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_state_2\/main_9 3.296
macrocell36 U(3,0) 1 \URT:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:pollcount_0\/main_3 127.861 MHz 7.821 14.906
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:pollcount_0\/main_3 3.291
macrocell40 U(2,0) 1 \URT:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:pollcount_1\/main_4 128.254 MHz 7.797 14.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:pollcount_1\/main_4 3.267
macrocell39 U(2,0) 1 \URT:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_last\/main_0 128.254 MHz 7.797 14.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_last\/main_0 3.267
macrocell43 U(2,0) 1 \URT:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_status_3\/main_7 132.591 MHz 7.542 15.185
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 1.020
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_status_3\/main_7 3.012
macrocell42 U(3,0) 1 \URT:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 45.4545ns(22 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_pre_reg\/main_0 50.259 MHz 19.897 25.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \ETH:BSPIM:sR8:Dp:u0\ \ETH:BSPIM:sR8:Dp:u0\/clock \ETH:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \ETH:BSPIM:mosi_from_dp\ \ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_pre_reg_split\/main_3 4.806
macrocell1 U(0,1) 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/main_3 \ETH:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/q \ETH:BSPIM:mosi_pre_reg\/main_0 2.871
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_pre_reg\/main_1 56.218 MHz 17.788 27.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \ETH:BSPIM:sR8:Dp:u0\ \ETH:BSPIM:sR8:Dp:u0\/clock \ETH:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \ETH:BSPIM:mosi_from_dp\ \ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_pre_reg_split_1\/main_3 3.333
macrocell41 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/main_3 \ETH:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/q \ETH:BSPIM:mosi_pre_reg\/main_1 2.235
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:state_0\/q \ETH:BSPIM:mosi_pre_reg\/main_0 59.605 MHz 16.777 28.678
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \ETH:BSPIM:state_0\ \ETH:BSPIM:state_0\/clock_0 \ETH:BSPIM:state_0\/q 1.250
Route 1 \ETH:BSPIM:state_0\ \ETH:BSPIM:state_0\/q \ETH:BSPIM:mosi_pre_reg_split\/main_2 5.796
macrocell1 U(0,1) 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/main_2 \ETH:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/q \ETH:BSPIM:mosi_pre_reg\/main_0 2.871
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_hs_reg\/main_3 61.207 MHz 16.338 29.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \ETH:BSPIM:sR8:Dp:u0\ \ETH:BSPIM:sR8:Dp:u0\/clock \ETH:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \ETH:BSPIM:mosi_from_dp\ \ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_hs_reg\/main_3 7.468
macrocell21 U(2,1) 1 \ETH:BSPIM:mosi_hs_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_from_dp_reg\/main_0 61.305 MHz 16.312 29.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \ETH:BSPIM:sR8:Dp:u0\ \ETH:BSPIM:sR8:Dp:u0\/clock \ETH:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \ETH:BSPIM:mosi_from_dp\ \ETH:BSPIM:sR8:Dp:u0\/so_comb \ETH:BSPIM:mosi_from_dp_reg\/main_0 7.442
macrocell24 U(3,1) 1 \ETH:BSPIM:mosi_from_dp_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:state_1\/q \ETH:BSPIM:mosi_pre_reg\/main_1 61.835 MHz 16.172 29.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ \ETH:BSPIM:state_1\/clock_0 \ETH:BSPIM:state_1\/q 1.250
Route 1 \ETH:BSPIM:state_1\ \ETH:BSPIM:state_1\/q \ETH:BSPIM:mosi_pre_reg_split_1\/main_1 5.827
macrocell41 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/main_1 \ETH:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/q \ETH:BSPIM:mosi_pre_reg\/main_1 2.235
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:state_2\/q \ETH:BSPIM:mosi_pre_reg\/main_0 62.869 MHz 15.906 29.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,0) 1 \ETH:BSPIM:state_2\ \ETH:BSPIM:state_2\/clock_0 \ETH:BSPIM:state_2\/q 1.250
Route 1 \ETH:BSPIM:state_2\ \ETH:BSPIM:state_2\/q \ETH:BSPIM:mosi_pre_reg_split\/main_0 4.925
macrocell1 U(0,1) 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/main_0 \ETH:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/q \ETH:BSPIM:mosi_pre_reg\/main_0 2.871
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_3 \ETH:BSPIM:mosi_pre_reg\/main_1 63.996 MHz 15.626 29.829
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_3 1.940
Route 1 \ETH:BSPIM:count_3\ \ETH:BSPIM:BitCounter\/count_3 \ETH:BSPIM:mosi_pre_reg_split_1\/main_5 4.591
macrocell41 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/main_5 \ETH:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/q \ETH:BSPIM:mosi_pre_reg\/main_1 2.235
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_0 \ETH:BSPIM:mosi_pre_reg\/main_1 65.164 MHz 15.346 30.109
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_0 1.940
Route 1 \ETH:BSPIM:count_0\ \ETH:BSPIM:BitCounter\/count_0 \ETH:BSPIM:mosi_pre_reg_split_1\/main_7 4.311
macrocell41 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/main_7 \ETH:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split_1\ \ETH:BSPIM:mosi_pre_reg_split_1\/q \ETH:BSPIM:mosi_pre_reg\/main_1 2.235
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\ETH:BSPIM:state_1\/q \ETH:BSPIM:mosi_pre_reg\/main_0 66.885 MHz 14.951 30.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ \ETH:BSPIM:state_1\/clock_0 \ETH:BSPIM:state_1\/q 1.250
Route 1 \ETH:BSPIM:state_1\ \ETH:BSPIM:state_1\/q \ETH:BSPIM:mosi_pre_reg_split\/main_1 3.970
macrocell1 U(0,1) 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/main_1 \ETH:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \ETH:BSPIM:mosi_pre_reg_split\ \ETH:BSPIM:mosi_pre_reg_split\/q \ETH:BSPIM:mosi_pre_reg\/main_0 2.871
macrocell22 U(0,0) 1 \ETH:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1068.18ns(936.17 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\URT:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \URT:BUART:sTX:TxSts\/status_0 45.595 MHz 21.932 1046.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \URT:BUART:sTX:TxShifter:u0\ \URT:BUART:sTX:TxShifter:u0\/clock \URT:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \URT:BUART:tx_fifo_empty\ \URT:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \URT:BUART:tx_status_0\/main_3 8.290
macrocell10 U(1,1) 1 \URT:BUART:tx_status_0\ \URT:BUART:tx_status_0\/main_3 \URT:BUART:tx_status_0\/q 3.350
Route 1 \URT:BUART:tx_status_0\ \URT:BUART:tx_status_0\/q \URT:BUART:sTX:TxSts\/status_0 6.212
statusicell3 U(2,1) 1 \URT:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\URT:BUART:tx_state_2\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.248 MHz 17.168 1051.014
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,1) 1 \URT:BUART:tx_state_2\ \URT:BUART:tx_state_2\/clock_0 \URT:BUART:tx_state_2\/q 1.250
Route 1 \URT:BUART:tx_state_2\ \URT:BUART:tx_state_2\/q \URT:BUART:counter_load_not\/main_3 4.066
macrocell9 U(1,1) 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/main_3 \URT:BUART:counter_load_not\/q 3.350
Route 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.312
datapathcell3 U(1,1) 1 \URT:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\URT:BUART:tx_state_0\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.258 MHz 17.165 1051.017
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,1) 1 \URT:BUART:tx_state_0\ \URT:BUART:tx_state_0\/clock_0 \URT:BUART:tx_state_0\/q 1.250
Route 1 \URT:BUART:tx_state_0\ \URT:BUART:tx_state_0\/q \URT:BUART:counter_load_not\/main_1 4.063
macrocell9 U(1,1) 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/main_1 \URT:BUART:counter_load_not\/q 3.350
Route 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.312
datapathcell3 U(1,1) 1 \URT:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\URT:BUART:tx_state_1\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.326 MHz 16.856 1051.326
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(1,1) 1 \URT:BUART:tx_state_1\ \URT:BUART:tx_state_1\/clock_0 \URT:BUART:tx_state_1\/q 1.250
Route 1 \URT:BUART:tx_state_1\ \URT:BUART:tx_state_1\/q \URT:BUART:counter_load_not\/main_0 3.754
macrocell9 U(1,1) 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/main_0 \URT:BUART:counter_load_not\/q 3.350
Route 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.312
datapathcell3 U(1,1) 1 \URT:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\URT:BUART:tx_ctrl_mark_last\/q \URT:BUART:sRX:RxBitCounter\/load 59.698 MHz 16.751 1051.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,1) 1 \URT:BUART:tx_ctrl_mark_last\ \URT:BUART:tx_ctrl_mark_last\/clock_0 \URT:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \URT:BUART:tx_ctrl_mark_last\ \URT:BUART:tx_ctrl_mark_last\/q \URT:BUART:rx_counter_load\/main_0 4.545
macrocell12 U(3,0) 1 \URT:BUART:rx_counter_load\ \URT:BUART:rx_counter_load\/main_0 \URT:BUART:rx_counter_load\/q 3.350
Route 1 \URT:BUART:rx_counter_load\ \URT:BUART:rx_counter_load\/q \URT:BUART:sRX:RxBitCounter\/load 2.246
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\URT:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.854 MHz 16.167 1052.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,1) 1 \URT:BUART:sTX:sCLOCK:TxBitClkGen\ \URT:BUART:sTX:sCLOCK:TxBitClkGen\/clock \URT:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \URT:BUART:tx_bitclk_enable_pre\ \URT:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \URT:BUART:counter_load_not\/main_2 4.125
macrocell9 U(1,1) 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/main_2 \URT:BUART:counter_load_not\/q 3.350
Route 1 \URT:BUART:counter_load_not\ \URT:BUART:counter_load_not\/q \URT:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.312
datapathcell3 U(1,1) 1 \URT:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\URT:BUART:tx_state_0\/q \URT:BUART:sTX:TxShifter:u0\/cs_addr_1 64.504 MHz 15.503 1052.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,1) 1 \URT:BUART:tx_state_0\ \URT:BUART:tx_state_0\/clock_0 \URT:BUART:tx_state_0\/q 1.250
Route 1 \URT:BUART:tx_state_0\ \URT:BUART:tx_state_0\/q \URT:BUART:sTX:TxShifter:u0\/cs_addr_1 8.243
datapathcell2 U(2,1) 1 \URT:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\URT:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \URT:BUART:tx_state_0\/main_3 65.020 MHz 15.380 1052.802
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \URT:BUART:sTX:TxShifter:u0\ \URT:BUART:sTX:TxShifter:u0\/clock \URT:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \URT:BUART:tx_fifo_empty\ \URT:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \URT:BUART:tx_state_0\/main_3 8.290
macrocell29 U(1,1) 1 \URT:BUART:tx_state_0\ SETUP 3.510
Clock Skew 0.000
\URT:BUART:tx_state_2\/q \URT:BUART:sTX:TxSts\/status_0 65.028 MHz 15.378 1052.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(1,1) 1 \URT:BUART:tx_state_2\ \URT:BUART:tx_state_2\/clock_0 \URT:BUART:tx_state_2\/q 1.250
Route 1 \URT:BUART:tx_state_2\ \URT:BUART:tx_state_2\/q \URT:BUART:tx_status_0\/main_4 4.066
macrocell10 U(1,1) 1 \URT:BUART:tx_status_0\ \URT:BUART:tx_status_0\/main_4 \URT:BUART:tx_status_0\/q 3.350
Route 1 \URT:BUART:tx_status_0\ \URT:BUART:tx_status_0\/q \URT:BUART:sTX:TxSts\/status_0 6.212
statusicell3 U(2,1) 1 \URT:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\URT:BUART:tx_state_0\/q \URT:BUART:sTX:TxSts\/status_0 65.041 MHz 15.375 1052.807
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,1) 1 \URT:BUART:tx_state_0\ \URT:BUART:tx_state_0\/clock_0 \URT:BUART:tx_state_0\/q 1.250
Route 1 \URT:BUART:tx_state_0\ \URT:BUART:tx_state_0\/q \URT:BUART:tx_status_0\/main_1 4.063
macrocell10 U(1,1) 1 \URT:BUART:tx_status_0\ \URT:BUART:tx_status_0\/main_1 \URT:BUART:tx_status_0\/q 3.350
Route 1 \URT:BUART:tx_status_0\ \URT:BUART:tx_status_0\/q \URT:BUART:sTX:TxSts\/status_0 6.212
statusicell3 U(2,1) 1 \URT:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
URX(0)_SYNC/out \URT:BUART:rx_status_3\/main_7 3.362
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_status_3\/main_7 3.012
macrocell42 U(3,0) 1 \URT:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:pollcount_1\/main_4 3.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:pollcount_1\/main_4 3.267
macrocell39 U(2,0) 1 \URT:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_last\/main_0 3.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_last\/main_0 3.267
macrocell43 U(2,0) 1 \URT:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:pollcount_0\/main_3 3.641
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:pollcount_0\/main_3 3.291
macrocell40 U(2,0) 1 \URT:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_state_0\/main_10 3.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_state_0\/main_10 3.296
macrocell33 U(3,0) 1 \URT:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:rx_state_2\/main_9 3.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_state_2\/main_9 3.296
macrocell36 U(3,0) 1 \URT:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
URX(0)_SYNC/out \URT:BUART:sRX:RxShifter:u0\/route_si 9.211
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 URX(0)_SYNC URX(0)_SYNC/clock URX(0)_SYNC/out 0.350
Route 1 Net_92_SYNCOUT URX(0)_SYNC/out \URT:BUART:rx_postpoll\/main_2 3.267
macrocell13 U(2,0) 1 \URT:BUART:rx_postpoll\ \URT:BUART:rx_postpoll\/main_2 \URT:BUART:rx_postpoll\/q 3.350
Route 1 \URT:BUART:rx_postpoll\ \URT:BUART:rx_postpoll\/q \URT:BUART:sRX:RxShifter:u0\/route_si 2.244
datapathcell4 U(3,0) 1 \URT:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ETH:BSPIM:BitCounter\/count_0 \ETH:BSPIM:state_1\/main_7 3.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_0 0.620
Route 1 \ETH:BSPIM:count_0\ \ETH:BSPIM:BitCounter\/count_0 \ETH:BSPIM:state_1\/main_7 2.631
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_0 \ETH:BSPIM:ld_ident\/main_7 3.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_0 0.620
Route 1 \ETH:BSPIM:count_0\ \ETH:BSPIM:BitCounter\/count_0 \ETH:BSPIM:ld_ident\/main_7 2.631
macrocell25 U(0,1) 1 \ETH:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_3 \ETH:BSPIM:state_1\/main_4 3.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_3 0.620
Route 1 \ETH:BSPIM:count_3\ \ETH:BSPIM:BitCounter\/count_3 \ETH:BSPIM:state_1\/main_4 2.642
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_3 \ETH:BSPIM:ld_ident\/main_4 3.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_3 0.620
Route 1 \ETH:BSPIM:count_3\ \ETH:BSPIM:BitCounter\/count_3 \ETH:BSPIM:ld_ident\/main_4 2.642
macrocell25 U(0,1) 1 \ETH:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_2 \ETH:BSPIM:state_1\/main_5 3.265
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_2 0.620
Route 1 \ETH:BSPIM:count_2\ \ETH:BSPIM:BitCounter\/count_2 \ETH:BSPIM:state_1\/main_5 2.645
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_2 \ETH:BSPIM:ld_ident\/main_5 3.265
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_2 0.620
Route 1 \ETH:BSPIM:count_2\ \ETH:BSPIM:BitCounter\/count_2 \ETH:BSPIM:ld_ident\/main_5 2.645
macrocell25 U(0,1) 1 \ETH:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_4 \ETH:BSPIM:state_1\/main_3 3.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_4 0.620
Route 1 \ETH:BSPIM:count_4\ \ETH:BSPIM:BitCounter\/count_4 \ETH:BSPIM:state_1\/main_3 2.821
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_4 \ETH:BSPIM:ld_ident\/main_3 3.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_4 0.620
Route 1 \ETH:BSPIM:count_4\ \ETH:BSPIM:BitCounter\/count_4 \ETH:BSPIM:ld_ident\/main_3 2.821
macrocell25 U(0,1) 1 \ETH:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_1 \ETH:BSPIM:state_1\/main_6 3.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_1 0.620
Route 1 \ETH:BSPIM:count_1\ \ETH:BSPIM:BitCounter\/count_1 \ETH:BSPIM:state_1\/main_6 2.836
macrocell18 U(0,1) 1 \ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\ETH:BSPIM:BitCounter\/count_1 \ETH:BSPIM:ld_ident\/main_6 3.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \ETH:BSPIM:BitCounter\ \ETH:BSPIM:BitCounter\/clock \ETH:BSPIM:BitCounter\/count_1 0.620
Route 1 \ETH:BSPIM:count_1\ \ETH:BSPIM:BitCounter\/count_1 \ETH:BSPIM:ld_ident\/main_6 2.836
macrocell25 U(0,1) 1 \ETH:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\URT:BUART:rx_status_3\/q \URT:BUART:sRX:RxSts\/status_3 2.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(3,0) 1 \URT:BUART:rx_status_3\ \URT:BUART:rx_status_3\/clock_0 \URT:BUART:rx_status_3\/q 1.250
Route 1 \URT:BUART:rx_status_3\ \URT:BUART:rx_status_3\/q \URT:BUART:sRX:RxSts\/status_3 2.867
statusicell4 U(3,1) 1 \URT:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_0 \URT:BUART:rx_bitclk_enable\/main_2 2.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \URT:BUART:rx_count_0\ \URT:BUART:sRX:RxBitCounter\/count_0 \URT:BUART:rx_bitclk_enable\/main_2 2.250
macrocell37 U(2,0) 1 \URT:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_1 \URT:BUART:rx_bitclk_enable\/main_1 3.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \URT:BUART:rx_count_1\ \URT:BUART:sRX:RxBitCounter\/count_1 \URT:BUART:rx_bitclk_enable\/main_1 2.570
macrocell37 U(2,0) 1 \URT:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_2 \URT:BUART:rx_bitclk_enable\/main_0 3.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \URT:BUART:rx_count_2\ \URT:BUART:sRX:RxBitCounter\/count_2 \URT:BUART:rx_bitclk_enable\/main_0 2.570
macrocell37 U(2,0) 1 \URT:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_2 \URT:BUART:pollcount_1\/main_0 3.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \URT:BUART:rx_count_2\ \URT:BUART:sRX:RxBitCounter\/count_2 \URT:BUART:pollcount_1\/main_0 2.570
macrocell39 U(2,0) 1 \URT:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_1 \URT:BUART:pollcount_1\/main_1 3.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \URT:BUART:rx_count_1\ \URT:BUART:sRX:RxBitCounter\/count_1 \URT:BUART:pollcount_1\/main_1 2.570
macrocell39 U(2,0) 1 \URT:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_4 \URT:BUART:rx_load_fifo\/main_7 3.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \URT:BUART:rx_count_4\ \URT:BUART:sRX:RxBitCounter\/count_4 \URT:BUART:rx_load_fifo\/main_7 2.574
macrocell34 U(3,0) 1 \URT:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_2 \URT:BUART:pollcount_0\/main_0 3.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \URT:BUART:rx_count_2\ \URT:BUART:sRX:RxBitCounter\/count_2 \URT:BUART:pollcount_0\/main_0 2.578
macrocell40 U(2,0) 1 \URT:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_1 \URT:BUART:pollcount_0\/main_1 3.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \URT:BUART:rx_count_1\ \URT:BUART:sRX:RxBitCounter\/count_1 \URT:BUART:pollcount_0\/main_1 2.578
macrocell40 U(2,0) 1 \URT:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\URT:BUART:sRX:RxBitCounter\/count_4 \URT:BUART:rx_state_0\/main_7 3.201
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \URT:BUART:sRX:RxBitCounter\ \URT:BUART:sRX:RxBitCounter\/clock \URT:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \URT:BUART:rx_count_4\ \URT:BUART:sRX:RxBitCounter\/count_4 \URT:BUART:rx_state_0\/main_7 2.581
macrocell33 U(3,0) 1 \URT:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ ETH_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \ETH:BSPIM:sR8:Dp:u0\/route_si 16.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell10 P5[3] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 7.832
Route 1 Net_19 MISO(0)/fb \ETH:BSPIM:sR8:Dp:u0\/route_si 5.576
datapathcell1 U(0,0) 1 \ETH:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ ETH_IntClock
Source Destination Delay (ns)
\ETH:BSPIM:state_0\/q MOSI(0)_PAD 36.315
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \ETH:BSPIM:state_0\ \ETH:BSPIM:state_0\/clock_0 \ETH:BSPIM:state_0\/q 1.250
Route 1 \ETH:BSPIM:state_0\ \ETH:BSPIM:state_0\/q Net_44/main_2 9.449
macrocell4 U(2,1) 1 Net_44 Net_44/main_2 Net_44/q 3.350
Route 1 Net_44 Net_44/q MOSI(0)/pin_input 7.380
iocell11 P5[4] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 14.886
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_45/q SCLK(0)_PAD 21.505
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 Net_45 Net_45/clock_0 Net_45/q 1.250
Route 1 Net_45 Net_45/q SCLK(0)/pin_input 5.865
iocell12 P5[5] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 14.390
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
+ LDON_CK(routed)
Source Destination Delay (ns)
ClockBlock/dclk_3 LDON(0)_PAD 26.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_3 0.000
Route 1 Net_130_local ClockBlock/dclk_3 LDON(0)/pin_input 10.272
iocell8 P6[2] 1 LDON(0) LDON(0)/pin_input LDON(0)/pad_out 15.746
Route 1 LDON(0)_PAD LDON(0)/pad_out LDON(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_3 LDON(0)_PAD 26.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_3 0.000
Route 1 Net_130_local ClockBlock/dclk_3 LDON(0)/pin_input 10.272
iocell8 P6[2] 1 LDON(0) LDON(0)/pin_input LDON(0)/pad_out 15.746
Route 1 LDON(0)_PAD LDON(0)/pad_out LDON(0)_PAD 0.000
Clock Clock path delay 0.000
+ URT_IntClock
Source Destination Delay (ns)
\URT:BUART:txn\/q UTX(0)_PAD 29.816
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,1) 1 \URT:BUART:txn\ \URT:BUART:txn\/clock_0 \URT:BUART:txn\/q 1.250
Route 1 \URT:BUART:txn\ \URT:BUART:txn\/q Net_79/main_0 2.804
macrocell8 U(3,1) 1 Net_79 Net_79/main_0 Net_79/q 3.350
Route 1 Net_79 Net_79/q UTX(0)/pin_input 6.557
iocell15 P12[0] 1 UTX(0) UTX(0)/pin_input UTX(0)/pad_out 15.855
Route 1 UTX(0)_PAD UTX(0)/pad_out UTX(0)_PAD 0.000
Clock Clock path delay 0.000