Static Timing Analysis

Project : Opcode_ver1
Build Time : 06/07/19 15:09:20
Device : CY8C5888AXQ-LP096
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 25.000 MHz 25.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 23.438 MHz 23.438 MHz N/A
CyBUS_CLK CyMASTER_CLK 23.438 MHz 23.438 MHz N/A
Clock_1 CyMASTER_CLK 11.719 MHz 11.719 MHz 90.992 MHz
Clock_3 CyMASTER_CLK 11.719 MHz 11.719 MHz 61.185 MHz
Clock_2 CyMASTER_CLK 11.719 MHz 11.719 MHz 47.046 MHz
Clock_4 CyMASTER_CLK 5.859 MHz 5.859 MHz 60.617 MHz
Clock_6 CyMASTER_CLK 1.563 MHz 1.563 MHz 23.486 MHz
CyPLL_OUT CyPLL_OUT 23.438 MHz 23.438 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A
SPI0_CLK(0)_PAD SPI0_CLK(0)_PAD UNKNOWN UNKNOWN 38.739 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 85.3333ns(11.7188 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_DSP:BSPIS:sync_2\/out \SPIS_DSP:BSPIS:TxStsReg\/status_0 90.992 MHz 10.990 74.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_2\ \SPIS_DSP:BSPIS:sync_2\/clock \SPIS_DSP:BSPIS:sync_2\/out 1.020
Route 1 \SPIS_DSP:BSPIS:miso_tx_empty_reg_fin\ \SPIS_DSP:BSPIS:sync_2\/out \SPIS_DSP:BSPIS:tx_status_0\/main_2 3.806
macrocell8 U(2,3) 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/main_2 \SPIS_DSP:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 2.314
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:RxStsReg\/status_5 98.049 MHz 10.199 75.134
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \SPIS_DSP:BSPIS:sync_3\ \SPIS_DSP:BSPIS:sync_3\/clock \SPIS_DSP:BSPIS:sync_3\/out 1.020
Route 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_reg\ \SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:rx_buf_overrun\/main_0 3.005
macrocell5 U(2,1) 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/main_0 \SPIS_DSP:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/q \SPIS_DSP:BSPIS:RxStsReg\/status_5 2.324
statusicell2 U(2,1) 1 \SPIS_DSP:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:TxStsReg\/status_6 99.177 MHz 10.083 75.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_1\ \SPIS_DSP:BSPIS:sync_1\/clock \SPIS_DSP:BSPIS:sync_1\/out 1.020
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_fin\ \SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:byte_complete\/main_0 2.878
macrocell4 U(2,3) 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/main_0 \SPIS_DSP:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/q \SPIS_DSP:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:TxStsReg\/status_0 99.384 MHz 10.062 75.271
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_1\ \SPIS_DSP:BSPIS:sync_1\/clock \SPIS_DSP:BSPIS:sync_1\/out 1.020
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_fin\ \SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:tx_status_0\/main_0 2.878
macrocell8 U(2,3) 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/main_0 \SPIS_DSP:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 2.314
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:TxStsReg\/status_6 102.606 MHz 9.746 75.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,3) 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_DSP:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:byte_complete\/main_1 2.311
macrocell4 U(2,3) 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/main_1 \SPIS_DSP:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/q \SPIS_DSP:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 102.828 MHz 9.725 75.608
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,3) 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_DSP:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:tx_status_0\/main_1 2.311
macrocell8 U(2,3) 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/main_1 \SPIS_DSP:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 2.314
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/q \SPIS_DSP:BSPIS:RxStsReg\/status_5 102.838 MHz 9.724 75.609
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,1) 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\ \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\ \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/q \SPIS_DSP:BSPIS:rx_buf_overrun\/main_1 2.300
macrocell5 U(2,1) 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/main_1 \SPIS_DSP:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/q \SPIS_DSP:BSPIS:RxStsReg\/status_5 2.324
statusicell2 U(2,1) 1 \SPIS_DSP:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/main_0 133.014 MHz 7.518 77.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \SPIS_DSP:BSPIS:sync_3\ \SPIS_DSP:BSPIS:sync_3\/clock \SPIS_DSP:BSPIS:sync_3\/out 1.020
Route 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_reg\ \SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/main_0 2.988
macrocell32 U(2,1) 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\ SETUP 3.510
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:dpcounter_one_reg\/main_0 134.989 MHz 7.408 77.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_1\ \SPIS_DSP:BSPIS:sync_1\/clock \SPIS_DSP:BSPIS:sync_1\/out 1.020
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_fin\ \SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:dpcounter_one_reg\/main_0 2.878
macrocell31 U(2,3) 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 85.3333ns(11.7188 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CLKGEN2:BSPIM:BitCounter\/count_2 \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 47.046 MHz 21.256 64.077
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_2 1.940
Route 1 \CLKGEN2:BSPIM:count_2\ \CLKGEN2:BSPIM:BitCounter\/count_2 \CLKGEN2:BSPIM:load_rx_data\/main_2 7.631
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_2 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 5.485
datapathcell4 U(3,2) 1 \CLKGEN2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_2 \CLKGEN2:BSPIM:TxStsReg\/status_3 47.826 MHz 20.909 64.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_2 1.940
Route 1 \CLKGEN2:BSPIM:count_2\ \CLKGEN2:BSPIM:BitCounter\/count_2 \CLKGEN2:BSPIM:load_rx_data\/main_2 7.631
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_2 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:TxStsReg\/status_3 7.488
statusicell5 U(3,1) 1 \CLKGEN2:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_2 \CLKGEN2:BSPIM:RxStsReg\/status_6 55.039 MHz 18.169 67.164
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_2 1.940
Route 1 \CLKGEN2:BSPIM:count_2\ \CLKGEN2:BSPIM:BitCounter\/count_2 \CLKGEN2:BSPIM:rx_status_6\/main_2 8.185
macrocell18 U(3,3) 1 \CLKGEN2:BSPIM:rx_status_6\ \CLKGEN2:BSPIM:rx_status_6\/main_2 \CLKGEN2:BSPIM:rx_status_6\/q 3.350
Route 1 \CLKGEN2:BSPIM:rx_status_6\ \CLKGEN2:BSPIM:rx_status_6\/q \CLKGEN2:BSPIM:RxStsReg\/status_6 4.194
statusicell6 U(3,3) 1 \CLKGEN2:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_1 \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 55.488 MHz 18.022 67.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_1 1.940
Route 1 \CLKGEN2:BSPIM:count_1\ \CLKGEN2:BSPIM:BitCounter\/count_1 \CLKGEN2:BSPIM:load_rx_data\/main_3 4.397
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_3 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 5.485
datapathcell4 U(3,2) 1 \CLKGEN2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_1 \CLKGEN2:BSPIM:TxStsReg\/status_3 56.577 MHz 17.675 67.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_1 1.940
Route 1 \CLKGEN2:BSPIM:count_1\ \CLKGEN2:BSPIM:BitCounter\/count_1 \CLKGEN2:BSPIM:load_rx_data\/main_3 4.397
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_3 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:TxStsReg\/status_3 7.488
statusicell5 U(3,1) 1 \CLKGEN2:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_0 \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 57.425 MHz 17.414 67.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_0 1.940
Route 1 \CLKGEN2:BSPIM:count_0\ \CLKGEN2:BSPIM:BitCounter\/count_0 \CLKGEN2:BSPIM:load_rx_data\/main_4 3.789
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_4 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 5.485
datapathcell4 U(3,2) 1 \CLKGEN2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_0 \CLKGEN2:BSPIM:TxStsReg\/status_3 58.593 MHz 17.067 68.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_0 1.940
Route 1 \CLKGEN2:BSPIM:count_0\ \CLKGEN2:BSPIM:BitCounter\/count_0 \CLKGEN2:BSPIM:load_rx_data\/main_4 3.789
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_4 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:TxStsReg\/status_3 7.488
statusicell5 U(3,1) 1 \CLKGEN2:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_4 \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 58.765 MHz 17.017 68.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_4 1.940
Route 1 \CLKGEN2:BSPIM:count_4\ \CLKGEN2:BSPIM:BitCounter\/count_4 \CLKGEN2:BSPIM:load_rx_data\/main_0 3.392
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_0 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 5.485
datapathcell4 U(3,2) 1 \CLKGEN2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_4 \CLKGEN2:BSPIM:TxStsReg\/status_3 59.988 MHz 16.670 68.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_4 1.940
Route 1 \CLKGEN2:BSPIM:count_4\ \CLKGEN2:BSPIM:BitCounter\/count_4 \CLKGEN2:BSPIM:load_rx_data\/main_0 3.392
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_0 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:TxStsReg\/status_3 7.488
statusicell5 U(3,1) 1 \CLKGEN2:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_3 \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 60.028 MHz 16.659 68.674
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_3 1.940
Route 1 \CLKGEN2:BSPIM:count_3\ \CLKGEN2:BSPIM:BitCounter\/count_3 \CLKGEN2:BSPIM:load_rx_data\/main_1 3.034
macrocell15 U(3,3) 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/main_1 \CLKGEN2:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN2:BSPIM:load_rx_data\ \CLKGEN2:BSPIM:load_rx_data\/q \CLKGEN2:BSPIM:sR8:Dp:u0\/f1_load 5.485
datapathcell4 U(3,2) 1 \CLKGEN2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
Path Delay Requirement : 85.3333ns(11.7188 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CLKGEN1:BSPIM:BitCounter\/count_4 \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 61.185 MHz 16.344 68.989
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_4 1.940
Route 1 \CLKGEN1:BSPIM:count_4\ \CLKGEN1:BSPIM:BitCounter\/count_4 \CLKGEN1:BSPIM:load_rx_data\/main_0 4.510
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_0 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 3.694
datapathcell3 U(0,2) 1 \CLKGEN1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_4 \CLKGEN1:BSPIM:TxStsReg\/status_3 62.901 MHz 15.898 69.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_4 1.940
Route 1 \CLKGEN1:BSPIM:count_4\ \CLKGEN1:BSPIM:BitCounter\/count_4 \CLKGEN1:BSPIM:load_rx_data\/main_0 4.510
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_0 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:TxStsReg\/status_3 5.598
statusicell3 U(0,1) 1 \CLKGEN1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 66.410 MHz 15.058 70.275
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_2 1.940
Route 1 \CLKGEN1:BSPIM:count_2\ \CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:load_rx_data\/main_2 3.224
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_2 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 3.694
datapathcell3 U(0,2) 1 \CLKGEN1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_4 \CLKGEN1:BSPIM:RxStsReg\/status_6 68.083 MHz 14.688 70.645
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_4 1.940
Route 1 \CLKGEN1:BSPIM:count_4\ \CLKGEN1:BSPIM:BitCounter\/count_4 \CLKGEN1:BSPIM:rx_status_6\/main_0 6.590
macrocell14 U(0,2) 1 \CLKGEN1:BSPIM:rx_status_6\ \CLKGEN1:BSPIM:rx_status_6\/main_0 \CLKGEN1:BSPIM:rx_status_6\/q 3.350
Route 1 \CLKGEN1:BSPIM:rx_status_6\ \CLKGEN1:BSPIM:rx_status_6\/q \CLKGEN1:BSPIM:RxStsReg\/status_6 2.308
statusicell4 U(0,2) 1 \CLKGEN1:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:TxStsReg\/status_3 68.437 MHz 14.612 70.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_2 1.940
Route 1 \CLKGEN1:BSPIM:count_2\ \CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:load_rx_data\/main_2 3.224
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_2 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:TxStsReg\/status_3 5.598
statusicell3 U(0,1) 1 \CLKGEN1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 70.577 MHz 14.169 71.164
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_3 1.940
Route 1 \CLKGEN1:BSPIM:count_3\ \CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:load_rx_data\/main_1 2.335
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_1 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 3.694
datapathcell3 U(0,2) 1 \CLKGEN1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 70.691 MHz 14.146 71.187
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_0 1.940
Route 1 \CLKGEN1:BSPIM:count_0\ \CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:load_rx_data\/main_4 2.312
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_4 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 3.694
datapathcell3 U(0,2) 1 \CLKGEN1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_1 \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 70.701 MHz 14.144 71.189
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_1 1.940
Route 1 \CLKGEN1:BSPIM:count_1\ \CLKGEN1:BSPIM:BitCounter\/count_1 \CLKGEN1:BSPIM:load_rx_data\/main_3 2.310
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_3 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:sR8:Dp:u0\/f1_load 3.694
datapathcell3 U(0,2) 1 \CLKGEN1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:TxStsReg\/status_3 72.870 MHz 13.723 71.610
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_3 1.940
Route 1 \CLKGEN1:BSPIM:count_3\ \CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:load_rx_data\/main_1 2.335
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_1 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:TxStsReg\/status_3 5.598
statusicell3 U(0,1) 1 \CLKGEN1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:TxStsReg\/status_3 72.993 MHz 13.700 71.633
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_0 1.940
Route 1 \CLKGEN1:BSPIM:count_0\ \CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:load_rx_data\/main_4 2.312
macrocell11 U(0,3) 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/main_4 \CLKGEN1:BSPIM:load_rx_data\/q 3.350
Route 1 \CLKGEN1:BSPIM:load_rx_data\ \CLKGEN1:BSPIM:load_rx_data\/q \CLKGEN1:BSPIM:TxStsReg\/status_3 5.598
statusicell3 U(0,1) 1 \CLKGEN1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 170.667ns(5.85938 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 60.617 MHz 16.497 154.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_0\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_4 4.007
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_4 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 4.350
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 60.621 MHz 16.496 154.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_0\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_4 4.007
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_4 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 4.349
datapathcell6 U(2,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 \SPIM_LEDDRIVER:BSPIM:TxStsReg\/status_3 63.943 MHz 15.639 155.028
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_0\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_0 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_4 4.007
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_4 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:TxStsReg\/status_3 5.842
statusicell7 U(2,4) 1 \SPIM_LEDDRIVER:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 64.115 MHz 15.597 155.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_3\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_1 3.107
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 4.350
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 64.119 MHz 15.596 155.071
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_3\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_1 3.107
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 4.349
datapathcell6 U(2,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_4 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 64.641 MHz 15.470 155.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_4\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_4 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_0 2.980
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_0 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 4.350
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 64.645 MHz 15.469 155.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_1\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_3 2.979
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_3 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 4.350
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_4 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 64.645 MHz 15.469 155.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_4\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_4 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_0 2.980
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_0 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 4.349
datapathcell6 U(2,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 64.650 MHz 15.468 155.199
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_1\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_3 2.979
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_3 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/f1_load 4.349
datapathcell6 U(2,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 64.721 MHz 15.451 155.216
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM_LEDDRIVER:BSPIM:count_2\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_2 2.961
macrocell19 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/main_2 \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_LEDDRIVER:BSPIM:load_rx_data\ \SPIM_LEDDRIVER:BSPIM:load_rx_data\/q \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/f1_load 4.350
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
Path Delay Requirement : 640ns(1.5625 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\TempI2C:sda_x_wire\/q \TempI2C:bI2C_UDB:sda_in_reg\/main_0 23.486 MHz 42.578 597.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(1,0) 1 \TempI2C:sda_x_wire\ \TempI2C:sda_x_wire\/clock_0 \TempI2C:sda_x_wire\/q 1.250
Route 1 \TempI2C:sda_x_wire\ \TempI2C:sda_x_wire\/q TEMP_SMDATA(0)/pin_input 8.184
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pin_input TEMP_SMDATA(0)/pad_out 15.933
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pad_out TEMP_SMDATA(0)/pad_in 0.000
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pad_in TEMP_SMDATA(0)/fb 7.630
Route 1 \TempI2C:Net_1109_1\ TEMP_SMDATA(0)/fb \TempI2C:bI2C_UDB:sda_in_reg\/main_0 6.071
macrocell61 U(2,2) 1 \TempI2C:bI2C_UDB:sda_in_reg\ SETUP 3.510
Clock Skew 0.000
\TempI2C:sda_x_wire\/q \TempI2C:bI2C_UDB:status_1\/main_6 23.499 MHz 42.555 597.445
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(1,0) 1 \TempI2C:sda_x_wire\ \TempI2C:sda_x_wire\/clock_0 \TempI2C:sda_x_wire\/q 1.250
Route 1 \TempI2C:sda_x_wire\ \TempI2C:sda_x_wire\/q TEMP_SMDATA(0)/pin_input 8.184
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pin_input TEMP_SMDATA(0)/pad_out 15.933
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pad_out TEMP_SMDATA(0)/pad_in 0.000
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pad_in TEMP_SMDATA(0)/fb 7.630
Route 1 \TempI2C:Net_1109_1\ TEMP_SMDATA(0)/fb \TempI2C:bI2C_UDB:status_1\/main_6 6.048
macrocell69 U(3,2) 1 \TempI2C:bI2C_UDB:status_1\ SETUP 3.510
Clock Skew 0.000
\TempI2C:Net_643_3\/q \TempI2C:bI2C_UDB:scl_in_reg\/main_0 25.296 MHz 39.532 600.468
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,1) 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/clock_0 \TempI2C:Net_643_3\/q 1.250
Route 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/q TEMP_SBCLK(0)/pin_input 7.486
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pin_input TEMP_SBCLK(0)/pad_out 15.855
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pad_out TEMP_SBCLK(0)/pad_in 0.000
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pad_in TEMP_SBCLK(0)/fb 6.830
Route 1 \TempI2C:Net_1109_0\ TEMP_SBCLK(0)/fb \TempI2C:bI2C_UDB:scl_in_reg\/main_0 4.601
macrocell71 U(3,0) 1 \TempI2C:bI2C_UDB:scl_in_reg\ SETUP 3.510
Clock Skew 0.000
\TempI2C:Net_643_3\/q \TempI2C:bI2C_UDB:clk_eq_reg\/main_0 25.296 MHz 39.532 600.468
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,1) 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/clock_0 \TempI2C:Net_643_3\/q 1.250
Route 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/q TEMP_SBCLK(0)/pin_input 7.486
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pin_input TEMP_SBCLK(0)/pad_out 15.855
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pad_out TEMP_SBCLK(0)/pad_in 0.000
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pad_in TEMP_SBCLK(0)/fb 6.830
Route 1 \TempI2C:Net_1109_0\ TEMP_SBCLK(0)/fb \TempI2C:bI2C_UDB:clk_eq_reg\/main_0 4.601
macrocell81 U(3,0) 1 \TempI2C:bI2C_UDB:clk_eq_reg\ SETUP 3.510
Clock Skew 0.000
\TempI2C:bI2C_UDB:m_state_3\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 28.059 MHz 35.639 604.361
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell63 U(1,1) 1 \TempI2C:bI2C_UDB:m_state_3\ \TempI2C:bI2C_UDB:m_state_3\/clock_0 \TempI2C:bI2C_UDB:m_state_3\/q 1.250
Route 1 \TempI2C:bI2C_UDB:m_state_3\ \TempI2C:bI2C_UDB:m_state_3\/q \TempI2C:bI2C_UDB:cnt_reset\/main_1 11.138
macrocell25 U(3,0) 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/main_1 \TempI2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/q \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 3.024
macrocell29 U(2,0) 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 7.517
datapathcell7 U(1,3) 1 \TempI2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\TempI2C:bI2C_UDB:m_state_4\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 29.729 MHz 33.637 606.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(1,0) 1 \TempI2C:bI2C_UDB:m_state_4\ \TempI2C:bI2C_UDB:m_state_4\/clock_0 \TempI2C:bI2C_UDB:m_state_4\/q 1.250
Route 1 \TempI2C:bI2C_UDB:m_state_4\ \TempI2C:bI2C_UDB:m_state_4\/q \TempI2C:bI2C_UDB:cnt_reset\/main_0 9.136
macrocell25 U(3,0) 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/main_0 \TempI2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/q \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 3.024
macrocell29 U(2,0) 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 7.517
datapathcell7 U(1,3) 1 \TempI2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\TempI2C:bI2C_UDB:m_state_1\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 31.430 MHz 31.817 608.183
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell65 U(3,2) 1 \TempI2C:bI2C_UDB:m_state_1\ \TempI2C:bI2C_UDB:m_state_1\/clock_0 \TempI2C:bI2C_UDB:m_state_1\/q 1.250
Route 1 \TempI2C:bI2C_UDB:m_state_1\ \TempI2C:bI2C_UDB:m_state_1\/q \TempI2C:bI2C_UDB:cnt_reset\/main_3 7.316
macrocell25 U(3,0) 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/main_3 \TempI2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/q \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 3.024
macrocell29 U(2,0) 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 7.517
datapathcell7 U(1,3) 1 \TempI2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\TempI2C:bI2C_UDB:m_state_3\/q \TempI2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 31.861 MHz 31.386 608.614
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell63 U(1,1) 1 \TempI2C:bI2C_UDB:m_state_3\ \TempI2C:bI2C_UDB:m_state_3\/clock_0 \TempI2C:bI2C_UDB:m_state_3\/q 1.250
Route 1 \TempI2C:bI2C_UDB:m_state_3\ \TempI2C:bI2C_UDB:m_state_3\/q \TempI2C:bI2C_UDB:cnt_reset\/main_1 11.138
macrocell25 U(3,0) 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/main_1 \TempI2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/q \TempI2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 5.248
macrocell26 U(2,2) 1 \TempI2C:bI2C_UDB:cs_addr_clkgen_1\ \TempI2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 \TempI2C:bI2C_UDB:cs_addr_clkgen_1\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cs_addr_clkgen_1\ \TempI2C:bI2C_UDB:cs_addr_clkgen_1\/q \TempI2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 2.920
datapathcell8 U(2,3) 1 \TempI2C:bI2C_UDB:Master:ClkGen:u0\ SETUP 4.130
Clock Skew 0.000
\TempI2C:bI2C_UDB:m_state_2\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 32.296 MHz 30.964 609.036
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell64 U(3,1) 1 \TempI2C:bI2C_UDB:m_state_2\ \TempI2C:bI2C_UDB:m_state_2\/clock_0 \TempI2C:bI2C_UDB:m_state_2\/q 1.250
Route 1 \TempI2C:bI2C_UDB:m_state_2\ \TempI2C:bI2C_UDB:m_state_2\/q \TempI2C:bI2C_UDB:cnt_reset\/main_2 6.463
macrocell25 U(3,0) 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/main_2 \TempI2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/q \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 3.024
macrocell29 U(2,0) 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 7.517
datapathcell7 U(1,3) 1 \TempI2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\TempI2C:Net_643_3\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 32.517 MHz 30.753 609.247
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,1) 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/clock_0 \TempI2C:Net_643_3\/q 1.250
Route 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/q \TempI2C:bI2C_UDB:cnt_reset\/main_8 6.252
macrocell25 U(3,0) 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/main_8 \TempI2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cnt_reset\ \TempI2C:bI2C_UDB:cnt_reset\/q \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 3.024
macrocell29 U(2,0) 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \TempI2C:bI2C_UDB:cs_addr_shifter_0\ \TempI2C:bI2C_UDB:cs_addr_shifter_0\/q \TempI2C:bI2C_UDB:Shifter:u0\/cs_addr_0 7.517
datapathcell7 U(1,3) 1 \TempI2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_DSP:BSPIS:mosi_tmp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 77.477 MHz 12.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(0,2) 1 \SPIS_DSP:BSPIS:mosi_tmp\ \SPIS_DSP:BSPIS:mosi_tmp\/clock_0 \SPIS_DSP:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS_DSP:BSPIS:mosi_tmp\ \SPIS_DSP:BSPIS:mosi_tmp\/q \SPIS_DSP:BSPIS:mosi_to_dp\/main_4 2.889
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_4 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 1.970
Clock Skew -1.781
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 95.896 MHz 10.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:tx_load\/main_0 2.327
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_0 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 95.914 MHz 10.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 95.914 MHz 10.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:tx_load\/main_0 2.327
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_0 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 95.932 MHz 10.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 95.942 MHz 10.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 95.960 MHz 10.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 95.969 MHz 10.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 95.988 MHz 10.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew -3.119
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 67.078 MHz 14.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:tx_load\/main_0 2.327
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_0 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 4.480
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 67.087 MHz 14.906
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:tx_load\/main_0 2.327
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_0 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP 4.480
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 67.087 MHz 14.906
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 4.480
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 67.096 MHz 14.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP 4.480
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 67.101 MHz 14.903
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 4.480
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 67.110 MHz 14.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP 4.480
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 67.114 MHz 14.900
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 4.480
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 67.123 MHz 14.898
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ SETUP 4.480
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 85.470 MHz 11.700
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:mosi_to_dp\/main_0 2.327
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_0 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 1.970
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 85.485 MHz 11.698
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:mosi_to_dp\/main_1 2.325
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_1 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 1.970
Clock Skew -3.116
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:dpcounter_one_reg\/main_0 3.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_1\ \SPIS_DSP:BSPIS:sync_1\/clock \SPIS_DSP:BSPIS:sync_1\/out 0.350
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_fin\ \SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:dpcounter_one_reg\/main_0 2.878
macrocell31 U(2,3) 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ HOLD 0.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/main_0 3.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \SPIS_DSP:BSPIS:sync_3\ \SPIS_DSP:BSPIS:sync_3\/clock \SPIS_DSP:BSPIS:sync_3\/out 0.350
Route 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_reg\ \SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/main_0 2.988
macrocell32 U(2,1) 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\ HOLD 0.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:TxStsReg\/status_0 6.892
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_1\ \SPIS_DSP:BSPIS:sync_1\/clock \SPIS_DSP:BSPIS:sync_1\/out 0.350
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_fin\ \SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:tx_status_0\/main_0 2.878
macrocell8 U(2,3) 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/main_0 \SPIS_DSP:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 2.314
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:TxStsReg\/status_6 6.913
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_1\ \SPIS_DSP:BSPIS:sync_1\/clock \SPIS_DSP:BSPIS:sync_1\/out 0.350
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_fin\ \SPIS_DSP:BSPIS:sync_1\/out \SPIS_DSP:BSPIS:byte_complete\/main_0 2.878
macrocell4 U(2,3) 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/main_0 \SPIS_DSP:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/q \SPIS_DSP:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:RxStsReg\/status_5 7.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \SPIS_DSP:BSPIS:sync_3\ \SPIS_DSP:BSPIS:sync_3\/clock \SPIS_DSP:BSPIS:sync_3\/out 0.350
Route 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_reg\ \SPIS_DSP:BSPIS:sync_3\/out \SPIS_DSP:BSPIS:rx_buf_overrun\/main_0 3.005
macrocell5 U(2,1) 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/main_0 \SPIS_DSP:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/q \SPIS_DSP:BSPIS:RxStsReg\/status_5 2.324
statusicell2 U(2,1) 1 \SPIS_DSP:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/q \SPIS_DSP:BSPIS:RxStsReg\/status_5 7.224
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,1) 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\ \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\ \SPIS_DSP:BSPIS:mosi_buf_overrun_fin\/q \SPIS_DSP:BSPIS:rx_buf_overrun\/main_1 2.300
macrocell5 U(2,1) 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/main_1 \SPIS_DSP:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_DSP:BSPIS:rx_buf_overrun\ \SPIS_DSP:BSPIS:rx_buf_overrun\/q \SPIS_DSP:BSPIS:RxStsReg\/status_5 2.324
statusicell2 U(2,1) 1 \SPIS_DSP:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 7.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,3) 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_DSP:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:tx_status_0\/main_1 2.311
macrocell8 U(2,3) 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/main_1 \SPIS_DSP:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 2.314
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:TxStsReg\/status_6 7.246
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,3) 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_DSP:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_DSP:BSPIS:dpcounter_one_reg\ \SPIS_DSP:BSPIS:dpcounter_one_reg\/q \SPIS_DSP:BSPIS:byte_complete\/main_1 2.311
macrocell4 U(2,3) 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/main_1 \SPIS_DSP:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_DSP:BSPIS:byte_complete\ \SPIS_DSP:BSPIS:byte_complete\/q \SPIS_DSP:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_DSP:BSPIS:sync_2\/out \SPIS_DSP:BSPIS:TxStsReg\/status_0 7.820
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 \SPIS_DSP:BSPIS:sync_2\ \SPIS_DSP:BSPIS:sync_2\/clock \SPIS_DSP:BSPIS:sync_2\/out 0.350
Route 1 \SPIS_DSP:BSPIS:miso_tx_empty_reg_fin\ \SPIS_DSP:BSPIS:sync_2\/out \SPIS_DSP:BSPIS:tx_status_0\/main_2 3.806
macrocell8 U(2,3) 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/main_2 \SPIS_DSP:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_status_0\ \SPIS_DSP:BSPIS:tx_status_0\/q \SPIS_DSP:BSPIS:TxStsReg\/status_0 2.314
statusicell1 U(2,3) 1 \SPIS_DSP:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\CLKGEN2:BSPIM:load_cond\/q \CLKGEN2:BSPIM:load_cond\/main_8 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell50 U(3,3) 1 \CLKGEN2:BSPIM:load_cond\ \CLKGEN2:BSPIM:load_cond\/clock_0 \CLKGEN2:BSPIM:load_cond\/q 1.250
macrocell50 U(3,3) 1 \CLKGEN2:BSPIM:load_cond\ \CLKGEN2:BSPIM:load_cond\/q \CLKGEN2:BSPIM:load_cond\/main_8 2.294
macrocell50 U(3,3) 1 \CLKGEN2:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_3 Net_117/main_6 3.654
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_3 0.620
Route 1 \CLKGEN2:BSPIM:count_3\ \CLKGEN2:BSPIM:BitCounter\/count_3 Net_117/main_6 3.034
macrocell46 U(3,3) 1 Net_117 HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_3 \CLKGEN2:BSPIM:load_cond\/main_4 3.674
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_3 0.620
Route 1 \CLKGEN2:BSPIM:count_3\ \CLKGEN2:BSPIM:BitCounter\/count_3 \CLKGEN2:BSPIM:load_cond\/main_4 3.054
macrocell50 U(3,3) 1 \CLKGEN2:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:cnt_enable\/q \CLKGEN2:BSPIM:cnt_enable\/main_3 3.869
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(3,4) 1 \CLKGEN2:BSPIM:cnt_enable\ \CLKGEN2:BSPIM:cnt_enable\/clock_0 \CLKGEN2:BSPIM:cnt_enable\/q 1.250
macrocell52 U(3,4) 1 \CLKGEN2:BSPIM:cnt_enable\ \CLKGEN2:BSPIM:cnt_enable\/q \CLKGEN2:BSPIM:cnt_enable\/main_3 2.619
macrocell52 U(3,4) 1 \CLKGEN2:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:ld_ident\/q \CLKGEN2:BSPIM:state_2\/main_9 3.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(3,4) 1 \CLKGEN2:BSPIM:ld_ident\ \CLKGEN2:BSPIM:ld_ident\/clock_0 \CLKGEN2:BSPIM:ld_ident\/q 1.250
Route 1 \CLKGEN2:BSPIM:ld_ident\ \CLKGEN2:BSPIM:ld_ident\/q \CLKGEN2:BSPIM:state_2\/main_9 2.630
macrocell47 U(3,4) 1 \CLKGEN2:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:ld_ident\/q \CLKGEN2:BSPIM:state_1\/main_9 3.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(3,4) 1 \CLKGEN2:BSPIM:ld_ident\ \CLKGEN2:BSPIM:ld_ident\/clock_0 \CLKGEN2:BSPIM:ld_ident\/q 1.250
Route 1 \CLKGEN2:BSPIM:ld_ident\ \CLKGEN2:BSPIM:ld_ident\/q \CLKGEN2:BSPIM:state_1\/main_9 2.630
macrocell48 U(3,4) 1 \CLKGEN2:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:ld_ident\/q \CLKGEN2:BSPIM:ld_ident\/main_8 3.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(3,4) 1 \CLKGEN2:BSPIM:ld_ident\ \CLKGEN2:BSPIM:ld_ident\/clock_0 \CLKGEN2:BSPIM:ld_ident\/q 1.250
macrocell51 U(3,4) 1 \CLKGEN2:BSPIM:ld_ident\ \CLKGEN2:BSPIM:ld_ident\/q \CLKGEN2:BSPIM:ld_ident\/main_8 2.630
macrocell51 U(3,4) 1 \CLKGEN2:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_4 Net_117/main_5 4.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_4 0.620
Route 1 \CLKGEN2:BSPIM:count_4\ \CLKGEN2:BSPIM:BitCounter\/count_4 Net_117/main_5 3.392
macrocell46 U(3,3) 1 Net_117 HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:BitCounter\/count_4 \CLKGEN2:BSPIM:load_cond\/main_3 4.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \CLKGEN2:BSPIM:BitCounter\ \CLKGEN2:BSPIM:BitCounter\/clock \CLKGEN2:BSPIM:BitCounter\/count_4 0.620
Route 1 \CLKGEN2:BSPIM:count_4\ \CLKGEN2:BSPIM:BitCounter\/count_4 \CLKGEN2:BSPIM:load_cond\/main_3 3.690
macrocell50 U(3,3) 1 \CLKGEN2:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN2:BSPIM:state_2\/q \CLKGEN2:BSPIM:state_2\/main_0 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(3,4) 1 \CLKGEN2:BSPIM:state_2\ \CLKGEN2:BSPIM:state_2\/clock_0 \CLKGEN2:BSPIM:state_2\/q 1.250
macrocell47 U(3,4) 1 \CLKGEN2:BSPIM:state_2\ \CLKGEN2:BSPIM:state_2\/q \CLKGEN2:BSPIM:state_2\/main_0 3.088
macrocell47 U(3,4) 1 \CLKGEN2:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\CLKGEN1:BSPIM:BitCounter\/count_1 \CLKGEN1:BSPIM:load_cond\/main_6 2.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_1 0.620
Route 1 \CLKGEN1:BSPIM:count_1\ \CLKGEN1:BSPIM:BitCounter\/count_1 \CLKGEN1:BSPIM:load_cond\/main_6 2.310
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_1 \CLKGEN1:BSPIM:ld_ident\/main_6 2.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_1 0.620
Route 1 \CLKGEN1:BSPIM:count_1\ \CLKGEN1:BSPIM:BitCounter\/count_1 \CLKGEN1:BSPIM:ld_ident\/main_6 2.310
macrocell42 U(0,3) 1 \CLKGEN1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:load_cond\/main_7 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_0 0.620
Route 1 \CLKGEN1:BSPIM:count_0\ \CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:load_cond\/main_7 2.312
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:ld_ident\/main_7 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_0 0.620
Route 1 \CLKGEN1:BSPIM:count_0\ \CLKGEN1:BSPIM:BitCounter\/count_0 \CLKGEN1:BSPIM:ld_ident\/main_7 2.312
macrocell42 U(0,3) 1 \CLKGEN1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:load_cond\/main_4 2.955
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_3 0.620
Route 1 \CLKGEN1:BSPIM:count_3\ \CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:load_cond\/main_4 2.335
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:ld_ident\/main_4 2.955
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_3 0.620
Route 1 \CLKGEN1:BSPIM:count_3\ \CLKGEN1:BSPIM:BitCounter\/count_3 \CLKGEN1:BSPIM:ld_ident\/main_4 2.335
macrocell42 U(0,3) 1 \CLKGEN1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:load_cond\/q \CLKGEN1:BSPIM:load_cond\/main_8 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ \CLKGEN1:BSPIM:load_cond\/clock_0 \CLKGEN1:BSPIM:load_cond\/q 1.250
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ \CLKGEN1:BSPIM:load_cond\/q \CLKGEN1:BSPIM:load_cond\/main_8 2.300
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:cnt_enable\/q \CLKGEN1:BSPIM:cnt_enable\/main_3 3.781
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(0,0) 1 \CLKGEN1:BSPIM:cnt_enable\ \CLKGEN1:BSPIM:cnt_enable\/clock_0 \CLKGEN1:BSPIM:cnt_enable\/q 1.250
macrocell43 U(0,0) 1 \CLKGEN1:BSPIM:cnt_enable\ \CLKGEN1:BSPIM:cnt_enable\/q \CLKGEN1:BSPIM:cnt_enable\/main_3 2.531
macrocell43 U(0,0) 1 \CLKGEN1:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:load_cond\/main_5 3.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_2 0.620
Route 1 \CLKGEN1:BSPIM:count_2\ \CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:load_cond\/main_5 3.224
macrocell41 U(0,3) 1 \CLKGEN1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:ld_ident\/main_5 3.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \CLKGEN1:BSPIM:BitCounter\ \CLKGEN1:BSPIM:BitCounter\/clock \CLKGEN1:BSPIM:BitCounter\/count_2 0.620
Route 1 \CLKGEN1:BSPIM:count_2\ \CLKGEN1:BSPIM:BitCounter\/count_2 \CLKGEN1:BSPIM:ld_ident\/main_5 3.224
macrocell42 U(0,3) 1 \CLKGEN1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/sol_msb \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/sir 0.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/clock \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/sol_msb 0.170
Route 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0.sol_msb__sig\ \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/sol_msb \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\/sir 0.000
datapathcell6 U(2,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u1\ HOLD 0.000
Clock Skew 0.000
Net_354/q Net_354/main_0 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(2,5) 1 Net_354 Net_354/clock_0 Net_354/q 1.250
macrocell54 U(2,5) 1 Net_354 Net_354/q Net_354/main_0 2.288
macrocell54 U(2,5) 1 Net_354 HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:cnt_enable\/q \SPIM_LEDDRIVER:BSPIM:cnt_enable\/main_3 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell60 U(2,3) 1 \SPIM_LEDDRIVER:BSPIM:cnt_enable\ \SPIM_LEDDRIVER:BSPIM:cnt_enable\/clock_0 \SPIM_LEDDRIVER:BSPIM:cnt_enable\/q 1.250
macrocell60 U(2,3) 1 \SPIM_LEDDRIVER:BSPIM:cnt_enable\ \SPIM_LEDDRIVER:BSPIM:cnt_enable\/q \SPIM_LEDDRIVER:BSPIM:cnt_enable\/main_3 2.306
macrocell60 U(2,3) 1 \SPIM_LEDDRIVER:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:load_cond\/q \SPIM_LEDDRIVER:BSPIM:load_cond\/main_8 3.560
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_cond\ \SPIM_LEDDRIVER:BSPIM:load_cond\/clock_0 \SPIM_LEDDRIVER:BSPIM:load_cond\/q 1.250
macrocell58 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_cond\ \SPIM_LEDDRIVER:BSPIM:load_cond\/q \SPIM_LEDDRIVER:BSPIM:load_cond\/main_8 2.310
macrocell58 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:state_2\/main_5 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_LEDDRIVER:BSPIM:count_2\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:state_2\/main_5 2.952
macrocell55 U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:state_1\/main_5 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_LEDDRIVER:BSPIM:count_2\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:state_1\/main_5 2.952
macrocell56 U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:ld_ident\/main_5 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_LEDDRIVER:BSPIM:count_2\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:ld_ident\/main_5 2.952
macrocell59 U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:load_cond\/main_5 3.581
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_LEDDRIVER:BSPIM:count_2\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 \SPIM_LEDDRIVER:BSPIM:load_cond\/main_5 2.961
macrocell58 U(3,5) 1 \SPIM_LEDDRIVER:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 Net_354/main_6 3.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM_LEDDRIVER:BSPIM:count_3\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_3 Net_354/main_6 2.962
macrocell54 U(2,5) 1 Net_354 HOLD 0.000
Clock Skew 0.000
\SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 Net_354/main_7 3.589
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \SPIM_LEDDRIVER:BSPIM:BitCounter\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/clock \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_LEDDRIVER:BSPIM:count_2\ \SPIM_LEDDRIVER:BSPIM:BitCounter\/count_2 Net_354/main_7 2.969
macrocell54 U(2,5) 1 Net_354 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \TempI2C:bI2C_UDB:m_state_3\/main_2 2.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\ \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 0.360
Route 1 \TempI2C:bI2C_UDB:control_2\ \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \TempI2C:bI2C_UDB:m_state_3\/main_2 2.325
macrocell63 U(1,1) 1 \TempI2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_5 \TempI2C:bI2C_UDB:m_state_3\/main_1 2.993
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\ \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_5 0.360
Route 1 \TempI2C:bI2C_UDB:control_5\ \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_5 \TempI2C:bI2C_UDB:m_state_3\/main_1 2.633
macrocell63 U(1,1) 1 \TempI2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_6 \TempI2C:bI2C_UDB:m_state_3\/main_0 3.185
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\ \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_6 0.360
Route 1 \TempI2C:bI2C_UDB:control_6\ \TempI2C:bI2C_UDB:SyncCtl:CtrlReg\/control_6 \TempI2C:bI2C_UDB:m_state_3\/main_0 2.825
macrocell63 U(1,1) 1 \TempI2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:clkgen_tc2_reg\/q \TempI2C:sda_x_wire\/main_10 3.472
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell79 U(1,0) 1 \TempI2C:bI2C_UDB:clkgen_tc2_reg\ \TempI2C:bI2C_UDB:clkgen_tc2_reg\/clock_0 \TempI2C:bI2C_UDB:clkgen_tc2_reg\/q 1.250
Route 1 \TempI2C:bI2C_UDB:clkgen_tc2_reg\ \TempI2C:bI2C_UDB:clkgen_tc2_reg\/q \TempI2C:sda_x_wire\/main_10 2.222
macrocell83 U(1,0) 1 \TempI2C:sda_x_wire\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:scl_in_last2_reg\/q \TempI2C:bI2C_UDB:bus_busy_reg\/main_2 3.475
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(3,0) 1 \TempI2C:bI2C_UDB:scl_in_last2_reg\ \TempI2C:bI2C_UDB:scl_in_last2_reg\/clock_0 \TempI2C:bI2C_UDB:scl_in_last2_reg\/q 1.250
Route 1 \TempI2C:bI2C_UDB:scl_in_last2_reg\ \TempI2C:bI2C_UDB:scl_in_last2_reg\/q \TempI2C:bI2C_UDB:bus_busy_reg\/main_2 2.225
macrocell80 U(3,0) 1 \TempI2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:bus_busy_reg\/q \TempI2C:bI2C_UDB:bus_busy_reg\/main_6 3.496
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(3,0) 1 \TempI2C:bI2C_UDB:bus_busy_reg\ \TempI2C:bI2C_UDB:bus_busy_reg\/clock_0 \TempI2C:bI2C_UDB:bus_busy_reg\/q 1.250
macrocell80 U(3,0) 1 \TempI2C:bI2C_UDB:bus_busy_reg\ \TempI2C:bI2C_UDB:bus_busy_reg\/q \TempI2C:bI2C_UDB:bus_busy_reg\/main_6 2.246
macrocell80 U(3,0) 1 \TempI2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:status_1\/q \TempI2C:bI2C_UDB:status_1\/main_0 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell69 U(3,2) 1 \TempI2C:bI2C_UDB:status_1\ \TempI2C:bI2C_UDB:status_1\/clock_0 \TempI2C:bI2C_UDB:status_1\/q 1.250
macrocell69 U(3,2) 1 \TempI2C:bI2C_UDB:status_1\ \TempI2C:bI2C_UDB:status_1\/q \TempI2C:bI2C_UDB:status_1\/main_0 2.299
macrocell69 U(3,2) 1 \TempI2C:bI2C_UDB:status_1\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:lost_arb_reg\/q \TempI2C:bI2C_UDB:lost_arb_reg\/main_2 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(1,3) 1 \TempI2C:bI2C_UDB:lost_arb_reg\ \TempI2C:bI2C_UDB:lost_arb_reg\/clock_0 \TempI2C:bI2C_UDB:lost_arb_reg\/q 1.250
macrocell77 U(1,3) 1 \TempI2C:bI2C_UDB:lost_arb_reg\ \TempI2C:bI2C_UDB:lost_arb_reg\/q \TempI2C:bI2C_UDB:lost_arb_reg\/main_2 2.306
macrocell77 U(1,3) 1 \TempI2C:bI2C_UDB:lost_arb_reg\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:scl_in_last_reg\/q \TempI2C:bI2C_UDB:scl_in_last2_reg\/main_0 3.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(3,0) 1 \TempI2C:bI2C_UDB:scl_in_last_reg\ \TempI2C:bI2C_UDB:scl_in_last_reg\/clock_0 \TempI2C:bI2C_UDB:scl_in_last_reg\/q 1.250
Route 1 \TempI2C:bI2C_UDB:scl_in_last_reg\ \TempI2C:bI2C_UDB:scl_in_last_reg\/q \TempI2C:bI2C_UDB:scl_in_last2_reg\/main_0 2.518
macrocell73 U(3,0) 1 \TempI2C:bI2C_UDB:scl_in_last2_reg\ HOLD 0.000
Clock Skew 0.000
\TempI2C:bI2C_UDB:scl_in_last_reg\/q \TempI2C:bI2C_UDB:bus_busy_reg\/main_1 3.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(3,0) 1 \TempI2C:bI2C_UDB:scl_in_last_reg\ \TempI2C:bI2C_UDB:scl_in_last_reg\/clock_0 \TempI2C:bI2C_UDB:scl_in_last_reg\/q 1.250
Route 1 \TempI2C:bI2C_UDB:scl_in_last_reg\ \TempI2C:bI2C_UDB:scl_in_last_reg\/q \TempI2C:bI2C_UDB:bus_busy_reg\/main_1 2.520
macrocell80 U(3,0) 1 \TempI2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS_DSP:BSPIS:mosi_tmp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5009.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(0,2) 1 \SPIS_DSP:BSPIS:mosi_tmp\ \SPIS_DSP:BSPIS:mosi_tmp\/clock_0 \SPIS_DSP:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS_DSP:BSPIS:mosi_tmp\ \SPIS_DSP:BSPIS:mosi_tmp\/q \SPIS_DSP:BSPIS:mosi_to_dp\/main_4 2.889
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_4 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -1.570
Clock Skew -1.781
Source Destination Slack (ns) Violation
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5005.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5005.710
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5005.711
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5005.713
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5005.714
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5005.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:tx_load\/main_0 2.327
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_0 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/f1_load 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5005.716
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5005.718
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:tx_load\/main_0 2.327
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_0 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/f1_load 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -3.116
Source Destination Slack (ns) Violation
\SPIS_DSP:BSPIS:sR16:Dp:u0\/sol_msb \SPIS_DSP:BSPIS:sR16:Dp:u1\/sir 2.867
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ \SPIS_DSP:BSPIS:sR16:Dp:u0\/clock \SPIS_DSP:BSPIS:sR16:Dp:u0\/sol_msb 4.170
Route 1 \SPIS_DSP:BSPIS:sR16:Dp:u0.sol_msb__sig\ \SPIS_DSP:BSPIS:sR16:Dp:u0\/sol_msb \SPIS_DSP:BSPIS:sR16:Dp:u1\/sir 0.000
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD -1.300
Clock Skew -0.003
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 6.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:mosi_to_dp\/main_3 2.319
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_3 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -1.570
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 6.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:mosi_to_dp\/main_2 2.322
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_2 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -1.570
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 6.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:mosi_to_dp\/main_1 2.325
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_1 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -1.570
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 6.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_DSP:BSPIS:count_3\ \SPIS_DSP:BSPIS:BitCounter\/count_3 \SPIS_DSP:BSPIS:mosi_to_dp\/main_0 2.327
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_0 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD -1.570
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 9.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD 0.000
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 9.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_DSP:BSPIS:count_0\ \SPIS_DSP:BSPIS:BitCounter\/count_0 \SPIS_DSP:BSPIS:tx_load\/main_3 2.319
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_3 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD 0.000
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 9.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD 0.000
Clock Skew -3.119
\SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 9.103
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_DSP:BSPIS:count_1\ \SPIS_DSP:BSPIS:BitCounter\/count_1 \SPIS_DSP:BSPIS:tx_load\/main_2 2.322
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_2 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/cs_addr_0 5.927
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ HOLD 0.000
Clock Skew -3.116
\SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 9.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ \SPIS_DSP:BSPIS:BitCounter\/clock_n \SPIS_DSP:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_DSP:BSPIS:count_2\ \SPIS_DSP:BSPIS:BitCounter\/count_2 \SPIS_DSP:BSPIS:tx_load\/main_1 2.325
macrocell3 U(1,3) 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/main_1 \SPIS_DSP:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_DSP:BSPIS:tx_load\ \SPIS_DSP:BSPIS:tx_load\/q \SPIS_DSP:BSPIS:sR16:Dp:u1\/cs_addr_0 5.928
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ HOLD 0.000
Clock Skew -3.119
+ Input To Output Section
Source Destination Delay (ns)
SPI0_CS0(0)_PAD SPI0_DIN(0)_PAD 42.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
Opcode_ver1 1 SPI0_CS0(0)_PAD SPI0_CS0(0)_PAD SPI0_CS0(0)_PAD 0.000
Route 1 SPI0_CS0(0)_PAD SPI0_CS0(0)_PAD SPI0_CS0(0)/pad_in 0.000
iocell21 P2[5] 1 SPI0_CS0(0) SPI0_CS0(0)/pad_in SPI0_CS0(0)/fb 7.735
Route 1 Net_71 SPI0_CS0(0)/fb Net_68/main_0 7.996
macrocell6 U(0,0) 1 Net_68 Net_68/main_0 Net_68/q 3.350
Route 1 Net_68 Net_68/q SPI0_DIN(0)/pin_input 7.963
iocell22 P2[6] 1 SPI0_DIN(0) SPI0_DIN(0)/pin_input SPI0_DIN(0)/pad_out 15.124
Route 1 SPI0_DIN(0)_PAD SPI0_DIN(0)/pad_out SPI0_DIN(0)_PAD 0.000
LEDDRIVER_DOUT(0)_PAD MCUTEST7(0)_PAD 31.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
Opcode_ver1 1 LEDDRIVER_DOUT(0)_PAD LEDDRIVER_DOUT(0)_PAD LEDDRIVER_DOUT(0)_PAD 0.000
Route 1 LEDDRIVER_DOUT(0)_PAD LEDDRIVER_DOUT(0)_PAD LEDDRIVER_DOUT(0)/pad_in 0.000
iocell56 P0[7] 1 LEDDRIVER_DOUT(0) LEDDRIVER_DOUT(0)/pad_in LEDDRIVER_DOUT(0)/fb 7.644
Route 1 Net_178 LEDDRIVER_DOUT(0)/fb MCUTEST7(0)/pin_input 8.282
iocell38 P15[5] 1 MCUTEST7(0) MCUTEST7(0)/pin_input MCUTEST7(0)/pad_out 15.925
Route 1 MCUTEST7(0)_PAD MCUTEST7(0)/pad_out MCUTEST7(0)_PAD 0.000
+ Input To Clock Section
+ Clock_2
Source Destination Delay (ns)
CLK_GEN2_SDO(0)_PAD \CLKGEN2:BSPIM:sR8:Dp:u0\/route_si 16.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 CLK_GEN2_SDO(0)_PAD CLK_GEN2_SDO(0)_PAD CLK_GEN2_SDO(0)/pad_in 0.000
iocell48 P3[3] 1 CLK_GEN2_SDO(0) CLK_GEN2_SDO(0)/pad_in CLK_GEN2_SDO(0)/fb 6.651
Route 1 Net_120 CLK_GEN2_SDO(0)/fb \CLKGEN2:BSPIM:sR8:Dp:u0\/route_si 5.972
datapathcell4 U(3,2) 1 \CLKGEN2:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock_3
Source Destination Delay (ns)
CLK_GEN1_SDO(0)_PAD \CLKGEN1:BSPIM:sR8:Dp:u0\/route_si 17.820
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 CLK_GEN1_SDO(0)_PAD CLK_GEN1_SDO(0)_PAD CLK_GEN1_SDO(0)/pad_in 0.000
iocell44 P3[6] 1 CLK_GEN1_SDO(0) CLK_GEN1_SDO(0)/pad_in CLK_GEN1_SDO(0)/fb 6.683
Route 1 Net_160 CLK_GEN1_SDO(0)/fb \CLKGEN1:BSPIM:sR8:Dp:u0\/route_si 7.637
datapathcell3 U(0,2) 1 \CLKGEN1:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock_4
Source Destination Delay (ns)
LEDDRIVER_DOUT(0)_PAD \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/route_si 17.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 LEDDRIVER_DOUT(0)_PAD LEDDRIVER_DOUT(0)_PAD LEDDRIVER_DOUT(0)/pad_in 0.000
iocell56 P0[7] 1 LEDDRIVER_DOUT(0) LEDDRIVER_DOUT(0)/pad_in LEDDRIVER_DOUT(0)/fb 7.644
Route 1 Net_178 LEDDRIVER_DOUT(0)/fb \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\/route_si 6.798
datapathcell5 U(3,4) 1 \SPIM_LEDDRIVER:BSPIM:sR16:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock_6
Source Destination Delay (ns)
TEMP_SMDATA(0)_PAD:in \TempI2C:bI2C_UDB:sda_in_reg\/main_0 17.211
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 TEMP_SMDATA(0)_PAD TEMP_SMDATA(0)_PAD:in TEMP_SMDATA(0)/pad_in 0.000
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pad_in TEMP_SMDATA(0)/fb 7.630
Route 1 \TempI2C:Net_1109_1\ TEMP_SMDATA(0)/fb \TempI2C:bI2C_UDB:sda_in_reg\/main_0 6.071
macrocell61 U(2,2) 1 \TempI2C:bI2C_UDB:sda_in_reg\ SETUP 3.510
Clock Clock path delay 0.000
TEMP_SBCLK(0)_PAD:in \TempI2C:bI2C_UDB:scl_in_reg\/main_0 14.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 TEMP_SBCLK(0)_PAD TEMP_SBCLK(0)_PAD:in TEMP_SBCLK(0)/pad_in 0.000
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pad_in TEMP_SBCLK(0)/fb 6.830
Route 1 \TempI2C:Net_1109_0\ TEMP_SBCLK(0)/fb \TempI2C:bI2C_UDB:scl_in_reg\/main_0 4.601
macrocell71 U(3,0) 1 \TempI2C:bI2C_UDB:scl_in_reg\ SETUP 3.510
Clock Clock path delay 0.000
+ SPI0_CLK(0)_PAD
Source Destination Delay (ns)
SPI0_CS0(0)_PAD \SPIS_DSP:BSPIS:BitCounter\/enable 16.829
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SPI0_CS0(0)_PAD SPI0_CS0(0)_PAD SPI0_CS0(0)/pad_in 0.000
iocell21 P2[5] 1 SPI0_CS0(0) SPI0_CS0(0)/pad_in SPI0_CS0(0)/fb 7.735
Route 1 Net_71 SPI0_CS0(0)/fb \SPIS_DSP:BSPIS:inv_ss\/main_0 8.917
macrocell2 U(2,1) 1 \SPIS_DSP:BSPIS:inv_ss\ \SPIS_DSP:BSPIS:inv_ss\/main_0 \SPIS_DSP:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS_DSP:BSPIS:inv_ss\ \SPIS_DSP:BSPIS:inv_ss\/q \SPIS_DSP:BSPIS:BitCounter\/enable 7.333
count7cell U(1,3) 1 \SPIS_DSP:BSPIS:BitCounter\ SETUP 4.060
Clock Clock path delay -14.566
SPI0_DOUT(0)_PAD \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 6.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SPI0_DOUT(0)_PAD SPI0_DOUT(0)_PAD SPI0_DOUT(0)/pad_in 0.000
iocell29 P2[4] 1 SPI0_DOUT(0) SPI0_DOUT(0)/pad_in SPI0_DOUT(0)/fb 7.454
Route 1 Net_69 SPI0_DOUT(0)/fb \SPIS_DSP:BSPIS:mosi_to_dp\/main_5 5.717
macrocell10 U(1,3) 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/main_5 \SPIS_DSP:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_DSP:BSPIS:mosi_to_dp\ \SPIS_DSP:BSPIS:mosi_to_dp\/q \SPIS_DSP:BSPIS:sR16:Dp:u0\/route_si 5.229
datapathcell1 U(0,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u0\ SETUP 1.970
Clock Clock path delay -17.682
SPI0_DOUT(0)_PAD \SPIS_DSP:BSPIS:mosi_tmp\/main_0 1.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SPI0_DOUT(0)_PAD SPI0_DOUT(0)_PAD SPI0_DOUT(0)/pad_in 0.000
iocell29 P2[4] 1 SPI0_DOUT(0) SPI0_DOUT(0)/pad_in SPI0_DOUT(0)/fb 7.454
Route 1 Net_69 SPI0_DOUT(0)/fb \SPIS_DSP:BSPIS:mosi_tmp\/main_0 6.498
macrocell33 U(0,2) 1 \SPIS_DSP:BSPIS:mosi_tmp\ SETUP 3.510
Clock Clock path delay -15.901
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
Net_119/q CLK_GEN2_CSB(0)_PAD 26.054
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell45 U(3,5) 1 Net_119 Net_119/clock_0 Net_119/q 1.250
Route 1 Net_119 Net_119/q CLK_GEN2_CSB(0)/pin_input 9.809
iocell47 P3[2] 1 CLK_GEN2_CSB(0) CLK_GEN2_CSB(0)/pin_input CLK_GEN2_CSB(0)/pad_out 14.995
Route 1 CLK_GEN2_CSB(0)_PAD CLK_GEN2_CSB(0)/pad_out CLK_GEN2_CSB(0)_PAD 0.000
Clock Clock path delay 0.000
Net_118/q CLK_GEN2_SCL(0)_PAD 23.049
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell53 U(3,3) 1 Net_118 Net_118/clock_0 Net_118/q 1.250
Route 1 Net_118 Net_118/q CLK_GEN2_SCL(0)/pin_input 6.919
iocell50 P0[4] 1 CLK_GEN2_SCL(0) CLK_GEN2_SCL(0)/pin_input CLK_GEN2_SCL(0)/pad_out 14.880
Route 1 CLK_GEN2_SCL(0)_PAD CLK_GEN2_SCL(0)/pad_out CLK_GEN2_SCL(0)_PAD 0.000
Clock Clock path delay 0.000
Net_117/q CLK_GEN2_SDIO(0)_PAD 22.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell46 U(3,3) 1 Net_117 Net_117/clock_0 Net_117/q 1.250
Route 1 Net_117 Net_117/q CLK_GEN2_SDIO(0)/pin_input 6.171
iocell49 P0[5] 1 CLK_GEN2_SDIO(0) CLK_GEN2_SDIO(0)/pin_input CLK_GEN2_SDIO(0)/pad_out 15.023
Route 1 CLK_GEN2_SDIO(0)_PAD CLK_GEN2_SDIO(0)/pad_out CLK_GEN2_SDIO(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_3
Source Destination Delay (ns)
Net_135/q CLK_GEN1_SDIO(0)_PAD 25.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(0,1) 1 Net_135 Net_135/clock_0 Net_135/q 1.250
Route 1 Net_135 Net_135/q CLK_GEN1_SDIO(0)/pin_input 9.236
iocell45 P0[0] 1 CLK_GEN1_SDIO(0) CLK_GEN1_SDIO(0)/pin_input CLK_GEN1_SDIO(0)/pad_out 15.251
Route 1 CLK_GEN1_SDIO(0)_PAD CLK_GEN1_SDIO(0)/pad_out CLK_GEN1_SDIO(0)_PAD 0.000
Clock Clock path delay 0.000
Net_134/q CLK_GEN1_SCL(0)_PAD 25.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(1,2) 1 Net_134 Net_134/clock_0 Net_134/q 1.250
Route 1 Net_134 Net_134/q CLK_GEN1_SCL(0)/pin_input 8.546
iocell46 P0[1] 1 CLK_GEN1_SCL(0) CLK_GEN1_SCL(0)/pin_input CLK_GEN1_SCL(0)/pad_out 15.802
Route 1 CLK_GEN1_SCL(0)_PAD CLK_GEN1_SCL(0)/pad_out CLK_GEN1_SCL(0)_PAD 0.000
Clock Clock path delay 0.000
Net_136/q CLK_GEN1_CSB(0)_PAD 24.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(1,2) 1 Net_136 Net_136/clock_0 Net_136/q 1.250
Route 1 Net_136 Net_136/q CLK_GEN1_CSB(0)/pin_input 8.354
iocell43 P3[7] 1 CLK_GEN1_CSB(0) CLK_GEN1_CSB(0)/pin_input CLK_GEN1_CSB(0)/pad_out 15.161
Route 1 CLK_GEN1_CSB(0)_PAD CLK_GEN1_CSB(0)/pad_out CLK_GEN1_CSB(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_4
Source Destination Delay (ns)
Net_353/q MCUTEST5(0)_PAD 25.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,4) 1 Net_353 Net_353/clock_0 Net_353/q 1.250
Route 1 Net_353 Net_353/q MCUTEST5(0)/pin_input 7.836
iocell36 P12[5] 1 MCUTEST5(0) MCUTEST5(0)/pin_input MCUTEST5(0)/pad_out 16.038
Route 1 MCUTEST5(0)_PAD MCUTEST5(0)/pad_out MCUTEST5(0)_PAD 0.000
Clock Clock path delay 0.000
Net_354/q MCUTEST4(0)_PAD 24.885
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(2,5) 1 Net_354 Net_354/clock_0 Net_354/q 1.250
Route 1 Net_354 Net_354/q MCUTEST4(0)/pin_input 7.020
iocell37 P12[4] 1 MCUTEST4(0) MCUTEST4(0)/pin_input MCUTEST4(0)/pad_out 16.615
Route 1 MCUTEST4(0)_PAD MCUTEST4(0)/pad_out MCUTEST4(0)_PAD 0.000
Clock Clock path delay 0.000
Net_344/q MCUTEST6(0)_PAD 24.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,3) 1 Net_344 Net_344/clock_0 Net_344/q 1.250
Route 1 Net_344 Net_344/q MCUTEST6(0)/pin_input 7.495
iocell35 P15[4] 1 MCUTEST6(0) MCUTEST6(0)/pin_input MCUTEST6(0)/pad_out 15.848
Route 1 MCUTEST6(0)_PAD MCUTEST6(0)/pad_out MCUTEST6(0)_PAD 0.000
Clock Clock path delay 0.000
Net_353/q LEDDRIVER_CLK(0)_PAD 24.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,4) 1 Net_353 Net_353/clock_0 Net_353/q 1.250
Route 1 Net_353 Net_353/q LEDDRIVER_CLK(0)/pin_input 8.367
iocell57 P3[0] 1 LEDDRIVER_CLK(0) LEDDRIVER_CLK(0)/pin_input LEDDRIVER_CLK(0)/pad_out 14.620
Route 1 LEDDRIVER_CLK(0)_PAD LEDDRIVER_CLK(0)/pad_out LEDDRIVER_CLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_344/q LEDDRIVER_CS(0)_PAD 23.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,3) 1 Net_344 Net_344/clock_0 Net_344/q 1.250
Route 1 Net_344 Net_344/q LEDDRIVER_CS(0)/pin_input 7.536
iocell59 P3[1] 1 LEDDRIVER_CS(0) LEDDRIVER_CS(0)/pin_input LEDDRIVER_CS(0)/pad_out 14.979
Route 1 LEDDRIVER_CS(0)_PAD LEDDRIVER_CS(0)/pad_out LEDDRIVER_CS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_354/q LEDDRIVER_DIN(0)_PAD 22.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(2,5) 1 Net_354 Net_354/clock_0 Net_354/q 1.250
Route 1 Net_354 Net_354/q LEDDRIVER_DIN(0)/pin_input 5.776
iocell58 P0[6] 1 LEDDRIVER_DIN(0) LEDDRIVER_DIN(0)/pin_input LEDDRIVER_DIN(0)/pad_out 15.561
Route 1 LEDDRIVER_DIN(0)_PAD LEDDRIVER_DIN(0)/pad_out LEDDRIVER_DIN(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_6
Source Destination Delay (ns)
\TempI2C:sda_x_wire\/q TEMP_SMDATA(0)_PAD:out 25.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(1,0) 1 \TempI2C:sda_x_wire\ \TempI2C:sda_x_wire\/clock_0 \TempI2C:sda_x_wire\/q 1.250
Route 1 \TempI2C:sda_x_wire\ \TempI2C:sda_x_wire\/q TEMP_SMDATA(0)/pin_input 8.184
iocell61 P12[1] 1 TEMP_SMDATA(0) TEMP_SMDATA(0)/pin_input TEMP_SMDATA(0)/pad_out 15.933
Route 1 TEMP_SMDATA(0)_PAD TEMP_SMDATA(0)/pad_out TEMP_SMDATA(0)_PAD:out 0.000
Clock Clock path delay 0.000
\TempI2C:Net_643_3\/q TEMP_SBCLK(0)_PAD:out 24.591
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,1) 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/clock_0 \TempI2C:Net_643_3\/q 1.250
Route 1 \TempI2C:Net_643_3\ \TempI2C:Net_643_3\/q TEMP_SBCLK(0)/pin_input 7.486
iocell60 P12[0] 1 TEMP_SBCLK(0) TEMP_SBCLK(0)/pin_input TEMP_SBCLK(0)/pad_out 15.855
Route 1 TEMP_SBCLK(0)_PAD TEMP_SBCLK(0)/pad_out TEMP_SBCLK(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ SPI0_CLK(0)_PAD
Source Destination Delay (ns)
\SPIS_DSP:BSPIS:sR16:Dp:u1\/so_comb SPI0_DIN(0)_PAD 55.522
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \SPIS_DSP:BSPIS:sR16:Dp:u1\ \SPIS_DSP:BSPIS:sR16:Dp:u1\/clock \SPIS_DSP:BSPIS:sR16:Dp:u1\/so_comb 9.160
Route 1 \SPIS_DSP:BSPIS:miso_from_dp\ \SPIS_DSP:BSPIS:sR16:Dp:u1\/so_comb Net_68/main_1 2.240
macrocell6 U(0,0) 1 Net_68 Net_68/main_1 Net_68/q 3.350
Route 1 Net_68 Net_68/q SPI0_DIN(0)/pin_input 7.963
iocell22 P2[6] 1 SPI0_DIN(0) SPI0_DIN(0)/pin_input SPI0_DIN(0)/pad_out 15.124
Route 1 SPI0_DIN(0)_PAD SPI0_DIN(0)/pad_out SPI0_DIN(0)_PAD 0.000
Clock Clock path delay 17.685