Static Timing Analysis

Project : SPI_PSOC_PSOC
Build Time : 12/26/17 21:51:05
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock CyMASTER_CLK 1.000 MHz 1.000 MHz 53.882 MHz
Clock_1 CyMASTER_CLK 1.000 MHz 1.000 MHz 84.019 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
SCLK_S(0)_PAD SCLK_S(0)_PAD UNKNOWN UNKNOWN 39.442 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 53.882 MHz 18.559 981.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 7.255
macrocell11 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.164
datapathcell2 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:RxStsReg\/status_6 56.886 MHz 17.579 982.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:rx_status_6\/main_4 7.255
macrocell14 U(3,1) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_4 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 4.534
statusicell4 U(3,2) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 57.113 MHz 17.509 982.491
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 7.255
macrocell11 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 4.464
statusicell3 U(2,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 69.132 MHz 14.465 985.535
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,2) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 4.735
datapathcell2 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 8.480
Clock Skew 0.000
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:RxStsReg\/status_6 70.077 MHz 14.270 985.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \SPIM:BSPIM:rx_status_4\ \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:rx_status_6\/main_5 2.306
macrocell14 U(3,1) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_5 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 4.534
statusicell4 U(3,2) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:TxStsReg\/status_0 70.240 MHz 14.237 985.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,2) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:tx_status_0\/main_2 6.900
macrocell12 U(3,0) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_2 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 2.237
statusicell3 U(2,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:state_1\/main_7 70.507 MHz 14.183 985.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:state_1\/main_7 8.733
macrocell20 U(3,0) 1 \SPIM:BSPIM:state_1\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:cnt_enable\/main_7 70.557 MHz 14.173 985.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:cnt_enable\/main_7 8.723
macrocell24 U(3,0) 1 \SPIM:BSPIM:cnt_enable\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_1\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 70.761 MHz 14.132 985.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,0) 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/clock_0 \SPIM:BSPIM:state_1\/q 1.250
Route 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 4.402
datapathcell2 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 8.480
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 71.638 MHz 13.959 986.041
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.655
macrocell11 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.164
datapathcell2 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:RxStsReg\/status_5 84.019 MHz 11.902 988.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,3) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:rx_buf_overrun\/main_1 2.303
macrocell4 U(3,3) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_1 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.499
statusicell2 U(2,2) 1 \SPIS:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:RxStsReg\/status_5 85.616 MHz 11.680 988.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 1.020
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:rx_buf_overrun\/main_0 2.311
macrocell4 U(3,3) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_0 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.499
statusicell2 U(2,2) 1 \SPIS:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:TxStsReg\/status_0 91.033 MHz 10.985 989.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_2\ \SPIS:BSPIS:sync_2\/clock \SPIS:BSPIS:sync_2\/out 1.020
Route 1 \SPIS:BSPIS:miso_tx_empty_reg_fin\ \SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:tx_status_0\/main_2 3.792
macrocell7 U(2,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_2 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 2.323
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_6 97.982 MHz 10.206 989.794
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:byte_complete\/main_1 2.771
macrocell3 U(2,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_1 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_0 98.030 MHz 10.201 989.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:tx_status_0\/main_1 2.778
macrocell7 U(2,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_1 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 2.323
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_6 101.771 MHz 9.826 990.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.020
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:byte_complete\/main_0 2.621
macrocell3 U(2,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_0 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_0 102.010 MHz 9.803 990.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.020
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:tx_status_0\/main_0 2.610
macrocell7 U(2,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_0 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 2.323
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 139.841 MHz 7.151 992.849
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.020
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.621
macrocell15 U(2,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ SETUP 3.510
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 146.177 MHz 6.841 993.159
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 1.020
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.311
macrocell16 U(3,3) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 71.256 MHz 14.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 71.256 MHz 14.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 71.256 MHz 14.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 71.261 MHz 14.033
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.267
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 77.393 MHz 12.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_3 4.352
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 81.222 MHz 12.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_2 3.743
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 85.441 MHz 11.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_1 3.135
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 85.463 MHz 11.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_0 3.132
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -1.601
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 104.668 MHz 9.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 104.668 MHz 9.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 104.668 MHz 9.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 104.679 MHz 9.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.267
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -1.601
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 78.883 MHz 12.677
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,1) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_4 2.289
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 0.908
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_2\/main_4 2.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_2\/main_4 2.303
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 2.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 2.311
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 2.312
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_2\/main_3 3.275
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_2\/main_3 2.655
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
Net_272/q Net_272/main_3 3.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,0) 1 Net_272 Net_272/clock_0 Net_272/q 1.250
macrocell22 U(3,0) 1 Net_272 Net_272/q Net_272/main_3 2.233
macrocell22 U(3,0) 1 Net_272 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,3) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell23 U(3,3) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.291
macrocell23 U(3,3) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_0\/main_4 3.796
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_0\/main_4 3.176
macrocell21 U(3,2) 1 \SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_0\/main_6 3.802
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_0\/main_6 3.182
macrocell21 U(3,2) 1 \SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_0\/main_5 3.806
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_0\/main_5 3.186
macrocell21 U(3,2) 1 \SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:cnt_enable\/main_6 3.987
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:cnt_enable\/main_6 3.367
macrocell24 U(3,0) 1 \SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.350
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.311
macrocell16 U(3,3) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.621
macrocell15 U(2,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_0 6.633
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:tx_status_0\/main_0 2.610
macrocell7 U(2,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_0 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 2.323
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_6 6.656
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:byte_complete\/main_0 2.621
macrocell3 U(2,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_0 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_0 7.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:tx_status_0\/main_1 2.778
macrocell7 U(2,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_1 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 2.323
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_6 7.706
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:byte_complete\/main_1 2.771
macrocell3 U(2,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_1 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.335
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:TxStsReg\/status_0 7.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_2\ \SPIS:BSPIS:sync_2\/clock \SPIS:BSPIS:sync_2\/out 0.350
Route 1 \SPIS:BSPIS:miso_tx_empty_reg_fin\ \SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:tx_status_0\/main_2 3.792
macrocell7 U(2,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_2 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 2.323
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:RxStsReg\/status_5 8.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.350
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:rx_buf_overrun\/main_0 2.311
macrocell4 U(3,3) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_0 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.499
statusicell2 U(2,2) 1 \SPIS:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:RxStsReg\/status_5 9.402
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,3) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:rx_buf_overrun\/main_1 2.303
macrocell4 U(3,3) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_1 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.499
statusicell2 U(2,2) 1 \SPIS:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.841
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_0 3.132
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_1 3.135
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 7.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_2 3.743
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 8.061
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_3 4.352
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 8.233
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.267
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 8.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 8.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 8.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -1.601
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5004.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.267
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5004.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5004.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -1.601
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5004.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.268
macrocell2 U(2,0) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.597
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -1.601
Source Destination Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 5009.137
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,1) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_4 2.289
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 0.908
+ Input To Output Section
Source Destination Delay (ns)
CS_S(0)_PAD MISO_S(0)_PAD 42.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
SPI_PSOC_PSOC 1 CS_S(0)_PAD CS_S(0)_PAD CS_S(0)_PAD 0.000
Route 1 CS_S(0)_PAD CS_S(0)_PAD CS_S(0)/pad_in 0.000
iocell8 P1[4] 1 CS_S(0) CS_S(0)/pad_in CS_S(0)/fb 7.732
Route 1 Net_253 CS_S(0)/fb Net_265/main_0 8.283
macrocell5 U(2,2) 1 Net_265 Net_265/main_0 Net_265/q 3.350
Route 1 Net_265 Net_265/q MISO_S(0)/pin_input 7.472
iocell12 P1[7] 1 MISO_S(0) MISO_S(0)/pin_input MISO_S(0)/pad_out 15.381
Route 1 MISO_S(0)_PAD MISO_S(0)/pad_out MISO_S(0)_PAD 0.000
+ Input To Clock Section
+ Clock
Source Destination Delay (ns)
MISO_M(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 18.417
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO_M(0)_PAD MISO_M(0)_PAD MISO_M(0)/pad_in 0.000
iocell15 P3[1] 1 MISO_M(0) MISO_M(0)/pad_in MISO_M(0)/fb 6.259
Route 1 Net_271 MISO_M(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 6.188
datapathcell2 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 5.970
Clock Clock path delay 0.000
+ SCLK_S(0)_PAD
Source Destination Delay (ns)
CS_S(0)_PAD \SPIS:BSPIS:BitCounter\/enable 14.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 CS_S(0)_PAD CS_S(0)_PAD CS_S(0)/pad_in 0.000
iocell8 P1[4] 1 CS_S(0) CS_S(0)/pad_in CS_S(0)/fb 7.732
Route 1 Net_253 CS_S(0)/fb \SPIS:BSPIS:inv_ss\/main_0 8.016
macrocell1 U(3,2) 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/main_0 \SPIS:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/q \SPIS:BSPIS:BitCounter\/enable 5.222
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ SETUP 4.060
Clock Clock path delay -14.223
MOSI_S(0)_PAD \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MOSI_S(0)_PAD MOSI_S(0)_PAD MOSI_S(0)/pad_in 0.000
iocell14 P1[6] 1 MOSI_S(0) MOSI_S(0)/pad_in MOSI_S(0)/fb 7.843
Route 1 Net_30 MOSI_S(0)/fb \SPIS:BSPIS:mosi_to_dp\/main_5 6.005
macrocell10 U(2,1) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_5 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.910
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Clock path delay -15.824
MOSI_S(0)_PAD \SPIS:BSPIS:mosi_tmp\/main_0 0.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MOSI_S(0)_PAD MOSI_S(0)_PAD MOSI_S(0)/pad_in 0.000
iocell14 P1[6] 1 MOSI_S(0) MOSI_S(0)/pad_in MOSI_S(0)/fb 7.843
Route 1 Net_30 MOSI_S(0)/fb \SPIS:BSPIS:mosi_tmp\/main_0 6.005
macrocell17 U(2,1) 1 \SPIS:BSPIS:mosi_tmp\ SETUP 3.510
Clock Clock path delay -16.732
+ Clock To Output Section
+ Clock
Source Destination Delay (ns)
Net_275/q MOSI_M(0)_PAD 22.682
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_275 Net_275/clock_0 Net_275/q 1.250
Route 1 Net_275 Net_275/q MOSI_M(0)/pin_input 6.094
iocell11 P3[5] 1 MOSI_M(0) MOSI_M(0)/pin_input MOSI_M(0)/pad_out 15.338
Route 1 MOSI_M(0)_PAD MOSI_M(0)/pad_out MOSI_M(0)_PAD 0.000
Clock Clock path delay 0.000
Net_273/q SCLK_M(0)_PAD 22.371
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,2) 1 Net_273 Net_273/clock_0 Net_273/q 1.250
Route 1 Net_273 Net_273/q SCLK_M(0)/pin_input 6.530
iocell10 P3[3] 1 SCLK_M(0) SCLK_M(0)/pin_input SCLK_M(0)/pad_out 14.591
Route 1 SCLK_M(0)_PAD SCLK_M(0)/pad_out SCLK_M(0)_PAD 0.000
Clock Clock path delay 0.000
+ SCLK_S(0)_PAD
Source Destination Delay (ns)
\SPIS:BSPIS:sR8:Dp:u0\/so_comb MISO_S(0)_PAD 53.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ \SPIS:BSPIS:sR8:Dp:u0\/clock \SPIS:BSPIS:sR8:Dp:u0\/so_comb 9.160
Route 1 \SPIS:BSPIS:miso_from_dp\ \SPIS:BSPIS:sR8:Dp:u0\/so_comb Net_265/main_1 2.328
macrocell5 U(2,2) 1 Net_265 Net_265/main_1 Net_265/q 3.350
Route 1 Net_265 Net_265/q MISO_S(0)/pin_input 7.472
iocell12 P1[7] 1 MISO_S(0) MISO_S(0)/pin_input MISO_S(0)/pad_out 15.381
Route 1 MISO_S(0)_PAD MISO_S(0)/pad_out MISO_S(0)_PAD 0.000
Clock Clock path delay 15.824