Static Timing Analysis

Project : projetoIC
Build Time : 01/27/16 14:54:14
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 70.000 MHz 70.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 70.000 MHz 70.000 MHz N/A
ADC_DelSig_theACLK(fixed-function) ADC_DelSig_theACLK(fixed-function) 1.591 MHz 1.591 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 70.000 MHz 70.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 70.000 MHz 70.000 MHz 78.407 MHz
ADC_DelSig_theACLK CyMASTER_CLK 1.591 MHz 1.591 MHz N/A
UART_1_IntClock CyMASTER_CLK 921.053 kHz 921.053 kHz 49.579 MHz
CyPLL_OUT CyPLL_OUT 70.000 MHz 70.000 MHz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 14.2857ns(70 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)_SYNC/out \UART_1:BUART:sRX:RxShifter:u0\/route_si 78.407 MHz 12.754 1.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_postpoll\/main_2 2.687
macrocell6 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.227
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 123.198 MHz 8.117 6.169
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 3.587
macrocell24 U(0,1) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 123.472 MHz 8.099 6.187
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.569
macrocell16 U(0,1) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 123.472 MHz 8.099 6.187
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.569
macrocell19 U(0,1) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 138.255 MHz 7.233 7.053
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 2.703
macrocell22 U(0,0) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 138.562 MHz 7.217 7.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 2.687
macrocell23 U(0,0) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 138.562 MHz 7.217 7.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 2.687
macrocell25 U(0,0) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1085.71ns(921.053 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 49.579 MHz 20.170 1065.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 7.894
macrocell5 U(0,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.591 MHz 16.781 1068.933
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.762
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 59.834 MHz 16.713 1069.001
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxShifter:u0\/cs_addr_1 9.453
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.414 MHz 16.022 1069.692
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.003
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 63.084 MHz 15.852 1069.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 2.833
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 64.025 MHz 15.619 1070.095
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 5.937
macrocell3 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.252
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 66.436 MHz 15.052 1070.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,1) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 2.776
macrocell5 U(0,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 66.948 MHz 14.937 1070.777
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 2.978
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 67.168 MHz 14.888 1070.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 2.612
macrocell5 U(0,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 67.240 MHz 14.872 1070.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 2.596
macrocell5 U(0,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 2.687
macrocell23 U(0,0) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 2.687
macrocell25 U(0,0) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.053
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 2.703
macrocell22 U(0,0) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.569
macrocell16 U(0,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.569
macrocell19 U(0,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 3.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 3.587
macrocell24 U(0,1) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:sRX:RxShifter:u0\/route_si 8.614
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_336_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_postpoll\/main_2 2.687
macrocell6 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.227
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.536
macrocell13 U(1,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.547
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.547
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 3.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 2.845
macrocell12 U(0,0) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 2.978
macrocell13 U(1,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 3.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 2.978
macrocell14 U(1,0) 1 \UART_1:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 3.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 2.992
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.783
macrocell17 U(0,1) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 3.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.787
macrocell17 U(0,1) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 3.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 2.821
macrocell16 U(0,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 31.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_331/main_0 3.297
macrocell1 U(1,1) 1 Net_331 Net_331/main_0 Net_331/q 3.350
Route 1 Net_331 Net_331/q Tx_1(0)/pin_input 6.187
iocell7 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000