Static Timing Analysis

Project : DMA_UART
Build Time : 09/26/14 20:14:27
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
CyBUS_CLK CyBUS_CLK -14.732
UART_IntClock CyBUS_CLK -10.494
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 31.921 MHz
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz 28.118 MHz Frequency
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_1/dmareq 28.118 MHz 35.565 -14.732 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/busclk \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART:BUART:tx_fifo_notfull\ \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART:BUART:tx_status_2\/main_0 2.549
macrocell24 U(3,0) 1 \UART:BUART:tx_status_2\ \UART:BUART:tx_status_2\/main_0 \UART:BUART:tx_status_2\/q 3.350
Route 1 \UART:BUART:tx_status_2\ \UART:BUART:tx_status_2\/q \UART:BUART:sTX:TxSts\/status_2 2.240
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/status_2 \UART:BUART:sTX:TxSts\/interrupt 3.910
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 SETUP 7.100
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_1/dmareq 33.367 MHz 29.970 -9.137 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/busclk \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART:BUART:tx_fifo_notfull\ \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART:BUART:sTX:TxSts\/status_3 2.544
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/status_3 \UART:BUART:sTX:TxSts\/interrupt 3.910
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 SETUP 7.100
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)_SYNC/out \UART:BUART:sRX:RxShifter:u0\/route_si 63.747 MHz 15.687 5.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_postpoll\/main_2 2.798
macrocell10 U(2,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.849
datapathcell1 U(2,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 114.784 MHz 8.712 12.121
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.722
macrocell15 U(2,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 114.811 MHz 8.710 12.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 3.720
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 116.891 MHz 8.555 12.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.565
macrocell11 U(2,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 116.891 MHz 8.555 12.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.565
macrocell12 U(2,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 128.403 MHz 7.788 13.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 2.798
macrocell3 U(2,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 128.403 MHz 7.788 13.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.480
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 2.798
macrocell8 U(2,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb DMA_1/dmareq 31.921 MHz 31.327 -10.494 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_1 5.831
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/status_1 \UART:BUART:sTX:TxSts\/interrupt 3.910
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 SETUP 7.100
Clock Skew 0.000
\UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 49.174 MHz 20.336 0.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/clock \UART:BUART:sTX:TxSts\/interrupt 4.030
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 SETUP 7.100
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.405 MHz 22.024 1061.309
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.655
macrocell2 U(2,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.249
datapathcell3 U(2,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.492 MHz 21.509 1061.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_2 3.140
macrocell2 U(2,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.249
datapathcell3 U(2,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.505 MHz 21.503 1061.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.134
macrocell2 U(2,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.249
datapathcell3 U(2,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_bitclk\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.832 MHz 21.353 1061.980
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,0) 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/clock_0 \UART:BUART:tx_bitclk\/q 1.250
Route 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/q \UART:BUART:counter_load_not\/main_3 2.984
macrocell2 U(2,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.249
datapathcell3 U(2,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 50.490 MHz 19.806 1063.527
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART:BUART:tx_bitclk_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART:BUART:tx_bitclk_enable_pre\/main_0 2.237
macrocell19 U(2,0) 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:tx_bitclk_enable_pre\/main_0 \UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:tx_bitclk_enable_pre\/q \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.249
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 59.077 MHz 16.927 1066.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_1 4.268
macrocell10 U(2,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.849
datapathcell1 U(2,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 60.241 MHz 16.600 1066.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 3.941
macrocell10 U(2,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.849
datapathcell1 U(2,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.239 MHz 16.067 1067.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_2 3.607
macrocell23 U(3,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_2 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.260
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 65.720 MHz 15.216 1068.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.080
macrocell7 U(2,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(2,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:rx_address_detected\/q \UART:BUART:sRX:RxBitCounter\/load 66.269 MHz 15.090 1068.243
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,1) 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/clock_0 \UART:BUART:rx_address_detected\/q 1.250
Route 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/q \UART:BUART:rx_counter_load\/main_0 3.954
macrocell7 U(2,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(2,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_1/dmareq 21.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/busclk \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART:BUART:tx_fifo_notfull\ \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART:BUART:sTX:TxSts\/status_3 2.544
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/status_3 \UART:BUART:sTX:TxSts\/interrupt 2.460
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb DMA_1/dmareq 27.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/busclk \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb 7.210
Route 1 \UART:BUART:tx_fifo_notfull\ \UART:BUART:sTX:TxShifter:u0\/f0_bus_stat_comb \UART:BUART:tx_status_2\/main_0 2.549
macrocell24 U(3,0) 1 \UART:BUART:tx_status_2\ \UART:BUART:tx_status_2\/main_0 \UART:BUART:tx_status_2\/q 3.350
Route 1 \UART:BUART:tx_status_2\ \UART:BUART:tx_status_2\/q \UART:BUART:sTX:TxSts\/status_2 2.240
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/status_2 \UART:BUART:sTX:TxSts\/interrupt 2.460
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 3.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 2.798
macrocell3 U(2,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 3.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 2.798
macrocell8 U(2,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 4.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.565
macrocell11 U(2,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 4.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.565
macrocell12 U(2,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 4.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 3.720
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 4.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.722
macrocell15 U(2,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:sRX:RxShifter:u0\/route_si 9.997
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.000
Route 1 Net_52_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_postpoll\/main_2 2.798
macrocell10 U(2,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.849
datapathcell1 U(2,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 13.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/clock \UART:BUART:sTX:TxSts\/interrupt 4.030
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb DMA_1/dmareq 22.777
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_1 5.831
statusicell2 U(3,0) 1 \UART:BUART:sTX:TxSts\ \UART:BUART:sTX:TxSts\/status_1 \UART:BUART:sTX:TxSts\/interrupt 2.460
Route 1 Net_88 \UART:BUART:sTX:TxSts\/interrupt DMA_1/dmareq 9.206
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell25 U(3,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.231
macrocell25 U(3,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 3.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,1) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 2.588
datapathcell1 U(2,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_0\/main_3 3.857
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_0\/main_3 2.607
macrocell11 U(2,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 3.857
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 2.607
macrocell12 U(2,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_3\/main_3 3.857
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_3\/main_3 2.607
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_load_fifo\/main_3 3.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_load_fifo\/main_3 2.612
macrocell9 U(2,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_stop1_reg\/main_2 3.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_stop1_reg\/main_2 2.612
macrocell14 U(2,1) 1 \UART:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_status_3\/main_3 3.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_status_3\/main_3 2.612
macrocell15 U(2,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 4.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 2.788
macrocell9 U(2,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_stop1_reg\/main_3 4.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_stop1_reg\/main_3 2.788
macrocell14 U(2,1) 1 \UART:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 31.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_47/main_0 3.132
macrocell1 U(3,1) 1 Net_47 Net_47/main_0 Net_47/q 3.350
Route 1 Net_47 Net_47/q Tx_1(0)/pin_input 8.122
iocell2 P0[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.495
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000