Static Timing Analysis

Project : PowerManagement_Hibernate01
Build Time : 09/17/18 17:38:21
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.50
VDDABUF : 5.50
VDDD : 5.50
VDDIO0 : 5.50
VDDIO1 : 5.50
VDDIO2 : 5.50
VDDIO3 : 5.50
VUSB : 5.50
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 12.000 MHz 12.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A