Static Timing Analysis

Project : BatteryCharger
Build Time : 12/17/13 18:13:44
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 48.000 MHz 48.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 48.000 MHz 48.000 MHz N/A
ADC_DelSig_theACLK(fixed-function) ADC_DelSig_theACLK(fixed-function) 2.526 MHz 2.526 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
Clock_1 CyMASTER_CLK 24.000 MHz 24.000 MHz 55.630 MHz
SampleClock CyMASTER_CLK 6.000 MHz 6.000 MHz 43.556 MHz
ADC_DelSig_theACLK CyMASTER_CLK 2.526 MHz 2.526 MHz N/A
Debug_Clock CyMASTER_CLK 10.000  Hz 10.000  Hz N/A
Clock_TimeOut CyMASTER_CLK 2.000  Hz 2.000  Hz 43.657 MHz
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
Debug_Clock(routed) Debug_Clock(routed) 10.000  Hz 10.000  Hz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 55.630 MHz 17.976 23.691
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\ \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/clock \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\ \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.606
datapathcell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_Sync:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.651 MHz 17.652 24.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,1) 1 \PWM_Sync:PWMUDB:sP8:pwmdp:u0\ \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell3 U(3,1) 1 \PWM_Sync:PWMUDB:sP8:pwmdp:u0\ \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.282
datapathcell3 U(3,1) 1 \PWM_Sync:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_Sync:PWMUDB:runmode_enable\/q \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.304 MHz 15.082 26.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,1) 1 \PWM_Sync:PWMUDB:runmode_enable\ \PWM_Sync:PWMUDB:runmode_enable\/clock_0 \PWM_Sync:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Sync:PWMUDB:runmode_enable\ \PWM_Sync:PWMUDB:runmode_enable\/q \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.312
datapathcell3 U(3,1) 1 \PWM_Sync:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:runmode_enable\/q \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.348 MHz 15.072 26.595
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:runmode_enable\ \DitheredPWM_1:PWM:PWMUDB:runmode_enable\/clock_0 \DitheredPWM_1:PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \DitheredPWM_1:PWM:PWMUDB:runmode_enable\ \DitheredPWM_1:PWM:PWMUDB:runmode_enable\/q \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.302
datapathcell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\DitheredPWM_1:Net_16\/q \DitheredPWM_1:Net_28\/clk_en 72.902 MHz 13.717 27.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 \DitheredPWM_1:Net_16\ \DitheredPWM_1:Net_16\/clock_0 \DitheredPWM_1:Net_16\/q 1.250
Route 1 \DitheredPWM_1:Net_16\ \DitheredPWM_1:Net_16\/q \DitheredPWM_1:PrISM:ClkSync__AND\/main_0 4.679
macrocell16 U(2,1) 1 \DitheredPWM_1:PrISM:ClkSync__AND\ \DitheredPWM_1:PrISM:ClkSync__AND\/main_0 \DitheredPWM_1:PrISM:ClkSync__AND\/q 3.350
Route 1 \DitheredPWM_1:PrISM:ClkSync__AND_OUT\ \DitheredPWM_1:PrISM:ClkSync__AND\/q \DitheredPWM_1:Net_28\/clk_en 2.338
macrocell8 U(2,1) 1 \DitheredPWM_1:Net_28\ SETUP 2.100
Clock Skew 0.000
\DitheredPWM_1:Net_16\/q \DitheredPWM_1:PrISM:sC8:PrISMdp:u0\/clk_en 72.902 MHz 13.717 27.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 \DitheredPWM_1:Net_16\ \DitheredPWM_1:Net_16\/clock_0 \DitheredPWM_1:Net_16\/q 1.250
Route 1 \DitheredPWM_1:Net_16\ \DitheredPWM_1:Net_16\/q \DitheredPWM_1:PrISM:ClkSync__AND\/main_0 4.679
macrocell16 U(2,1) 1 \DitheredPWM_1:PrISM:ClkSync__AND\ \DitheredPWM_1:PrISM:ClkSync__AND\/main_0 \DitheredPWM_1:PrISM:ClkSync__AND\/q 3.350
Route 1 \DitheredPWM_1:PrISM:ClkSync__AND_OUT\ \DitheredPWM_1:PrISM:ClkSync__AND\/q \DitheredPWM_1:PrISM:sC8:PrISMdp:u0\/clk_en 2.338
datapathcell2 U(2,1) 1 \DitheredPWM_1:PrISM:sC8:PrISMdp:u0\ SETUP 2.100
Clock Skew 0.000
\Sync_2:genblk1[0]:INST\/out Net_1740/clk_en 81.659 MHz 12.246 29.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.480
Route 1 Net_744 \Sync_2:genblk1[0]:INST\/out \UDBClkEn_1:udbclkenable__AND\/main_0 2.977
macrocell25 U(2,1) 1 \UDBClkEn_1:udbclkenable__AND\ \UDBClkEn_1:udbclkenable__AND\/main_0 \UDBClkEn_1:udbclkenable__AND\/q 3.350
Route 1 \UDBClkEn_1:udbclkenable__AND_OUT\ \UDBClkEn_1:udbclkenable__AND\/q Net_1740/clk_en 2.339
macrocell2 U(2,1) 1 Net_1740 SETUP 2.100
Clock Skew 0.000
\DitheredPWM_1:PrISM:enable_final_reg\/q \DitheredPWM_1:Net_28\/clk_en 84.296 MHz 11.863 29.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,0) 1 \DitheredPWM_1:PrISM:enable_final_reg\ \DitheredPWM_1:PrISM:enable_final_reg\/clock_0 \DitheredPWM_1:PrISM:enable_final_reg\/q 1.250
Route 1 \DitheredPWM_1:PrISM:enable_final_reg\ \DitheredPWM_1:PrISM:enable_final_reg\/q \DitheredPWM_1:PrISM:ClkSync__AND\/main_1 2.825
macrocell16 U(2,1) 1 \DitheredPWM_1:PrISM:ClkSync__AND\ \DitheredPWM_1:PrISM:ClkSync__AND\/main_1 \DitheredPWM_1:PrISM:ClkSync__AND\/q 3.350
Route 1 \DitheredPWM_1:PrISM:ClkSync__AND_OUT\ \DitheredPWM_1:PrISM:ClkSync__AND\/q \DitheredPWM_1:Net_28\/clk_en 2.338
macrocell8 U(2,1) 1 \DitheredPWM_1:Net_28\ SETUP 2.100
Clock Skew 0.000
\DitheredPWM_1:PrISM:enable_final_reg\/q \DitheredPWM_1:PrISM:sC8:PrISMdp:u0\/clk_en 84.296 MHz 11.863 29.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,0) 1 \DitheredPWM_1:PrISM:enable_final_reg\ \DitheredPWM_1:PrISM:enable_final_reg\/clock_0 \DitheredPWM_1:PrISM:enable_final_reg\/q 1.250
Route 1 \DitheredPWM_1:PrISM:enable_final_reg\ \DitheredPWM_1:PrISM:enable_final_reg\/q \DitheredPWM_1:PrISM:ClkSync__AND\/main_1 2.825
macrocell16 U(2,1) 1 \DitheredPWM_1:PrISM:ClkSync__AND\ \DitheredPWM_1:PrISM:ClkSync__AND\/main_1 \DitheredPWM_1:PrISM:ClkSync__AND\/q 3.350
Route 1 \DitheredPWM_1:PrISM:ClkSync__AND_OUT\ \DitheredPWM_1:PrISM:ClkSync__AND\/q \DitheredPWM_1:PrISM:sC8:PrISMdp:u0\/clk_en 2.338
datapathcell2 U(2,1) 1 \DitheredPWM_1:PrISM:sC8:PrISMdp:u0\ SETUP 2.100
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \DitheredPWM_1:Net_25\/main_1 84.810 MHz 11.791 29.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\ \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/clock \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \DitheredPWM_1:PWM:PWMUDB:compare1\ \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \DitheredPWM_1:Net_25\/main_1 2.601
macrocell6 U(2,3) 1 \DitheredPWM_1:Net_25\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 5e+008ns(2  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 43.657 MHz 22.906 499999977.094
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.826
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 46.564 MHz 21.476 499999978.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.826
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 49.400 MHz 20.243 499999979.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(3,0) 1 \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_TimeOut:TimerUDB:control_7\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.863
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 50.615 MHz 19.757 499999980.243
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.957
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 50.953 MHz 19.626 499999980.374
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.826
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 54.564 MHz 18.327 499999981.673
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.957
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 54.957 MHz 18.196 499999981.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.826
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_1 58.545 MHz 17.081 499999982.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(3,0) 1 \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_TimeOut:TimerUDB:control_7\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.981
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_1 58.952 MHz 16.963 499999983.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(3,0) 1 \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_TimeOut:TimerUDB:control_7\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.863
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 64.847 MHz 15.421 499999984.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:status_tc\/main_1 2.973
macrocell24 U(3,0) 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/main_1 \Timer_TimeOut:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/q \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 2.248
statusicell4 U(3,0) 1 \Timer_TimeOut:TimerUDB:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 166.667ns(6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 43.556 MHz 22.959 143.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.879
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 46.449 MHz 21.529 145.138
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.879
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 49.203 MHz 20.324 146.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,2) 1 \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_Scan:TimerUDB:control_7\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.944
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 50.816 MHz 19.679 146.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.879
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 50.823 MHz 19.676 146.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.876
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 54.798 MHz 18.249 148.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.879
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 54.807 MHz 18.246 148.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.876
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_1 58.187 MHz 17.186 149.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,2) 1 \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_Scan:TimerUDB:control_7\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.086
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_1 58.672 MHz 17.044 149.623
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,2) 1 \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer_Scan:TimerUDB:control_7\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.944
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 64.906 MHz 15.407 151.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:status_tc\/main_1 2.884
macrocell23 U(2,2) 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/main_1 \Timer_Scan:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/q \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 2.323
statusicell3 U(2,2) 1 \Timer_Scan:TimerUDB:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_Sync:PWMUDB:status_1\/q \PWM_Sync:PWMUDB:genblk8:stsreg\/status_1 1.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,1) 1 \PWM_Sync:PWMUDB:status_1\ \PWM_Sync:PWMUDB:status_1\/clock_0 \PWM_Sync:PWMUDB:status_1\/q 1.250
Route 1 \PWM_Sync:PWMUDB:status_1\ \PWM_Sync:PWMUDB:status_1\/q \PWM_Sync:PWMUDB:genblk8:stsreg\/status_1 2.299
statusicell2 U(3,1) 1 \PWM_Sync:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_Sync:PWMUDB:status_0\/q \PWM_Sync:PWMUDB:genblk8:stsreg\/status_0 1.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,1) 1 \PWM_Sync:PWMUDB:status_0\ \PWM_Sync:PWMUDB:status_0\/clock_0 \PWM_Sync:PWMUDB:status_0\/q 1.250
Route 1 \PWM_Sync:PWMUDB:status_0\ \PWM_Sync:PWMUDB:status_0\/q \PWM_Sync:PWMUDB:genblk8:stsreg\/status_0 2.311
statusicell2 U(3,1) 1 \PWM_Sync:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:status_1\/q \DitheredPWM_1:PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_1 1.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:status_1\ \DitheredPWM_1:PWM:PWMUDB:status_1\/clock_0 \DitheredPWM_1:PWM:PWMUDB:status_1\/q 1.250
Route 1 \DitheredPWM_1:PWM:PWMUDB:status_1\ \DitheredPWM_1:PWM:PWMUDB:status_1\/q \DitheredPWM_1:PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_1 2.321
statusicell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:status_0\/q \DitheredPWM_1:PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:status_0\ \DitheredPWM_1:PWM:PWMUDB:status_0\/clock_0 \DitheredPWM_1:PWM:PWMUDB:status_0\/q 1.250
Route 1 \DitheredPWM_1:PWM:PWMUDB:status_0\ \DitheredPWM_1:PWM:PWMUDB:status_0\/q \DitheredPWM_1:PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 2.323
statusicell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_Sync:PWMUDB:prevCompare2\/q \PWM_Sync:PWMUDB:status_1\/main_0 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 \PWM_Sync:PWMUDB:prevCompare2\ \PWM_Sync:PWMUDB:prevCompare2\/clock_0 \PWM_Sync:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_Sync:PWMUDB:prevCompare2\ \PWM_Sync:PWMUDB:prevCompare2\/q \PWM_Sync:PWMUDB:status_1\/main_0 2.293
macrocell22 U(3,1) 1 \PWM_Sync:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:prevCompare2\/q \DitheredPWM_1:PWM:PWMUDB:status_1\/main_1 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:prevCompare2\ \DitheredPWM_1:PWM:PWMUDB:prevCompare2\/clock_0 \DitheredPWM_1:PWM:PWMUDB:prevCompare2\/q 1.250
Route 1 \DitheredPWM_1:PWM:PWMUDB:prevCompare2\ \DitheredPWM_1:PWM:PWMUDB:prevCompare2\/q \DitheredPWM_1:PWM:PWMUDB:status_1\/main_1 2.295
macrocell14 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:prevCompare1\/q \DitheredPWM_1:PWM:PWMUDB:status_0\/main_1 3.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:prevCompare1\ \DitheredPWM_1:PWM:PWMUDB:prevCompare1\/clock_0 \DitheredPWM_1:PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \DitheredPWM_1:PWM:PWMUDB:prevCompare1\ \DitheredPWM_1:PWM:PWMUDB:prevCompare1\/q \DitheredPWM_1:PWM:PWMUDB:status_0\/main_1 2.298
macrocell13 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_Sync:PWMUDB:prevCompare1\/q \PWM_Sync:PWMUDB:status_0\/main_0 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 \PWM_Sync:PWMUDB:prevCompare1\ \PWM_Sync:PWMUDB:prevCompare1\/clock_0 \PWM_Sync:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_Sync:PWMUDB:prevCompare1\ \PWM_Sync:PWMUDB:prevCompare1\/q \PWM_Sync:PWMUDB:status_0\/main_0 2.299
macrocell21 U(3,1) 1 \PWM_Sync:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\DitheredPWM_1:PWM:PWMUDB:runmode_enable\/q \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:runmode_enable\ \DitheredPWM_1:PWM:PWMUDB:runmode_enable\/clock_0 \DitheredPWM_1:PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \DitheredPWM_1:PWM:PWMUDB:runmode_enable\ \DitheredPWM_1:PWM:PWMUDB:runmode_enable\/q \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.302
datapathcell1 U(2,3) 1 \DitheredPWM_1:PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_Sync:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Sync:PWMUDB:genblk8:stsreg\/status_2 3.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,1) 1 \PWM_Sync:PWMUDB:sP8:pwmdp:u0\ \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
Route 1 \PWM_Sync:PWMUDB:tc_i\ \PWM_Sync:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Sync:PWMUDB:genblk8:stsreg\/status_2 2.289
statusicell2 U(3,1) 1 \PWM_Sync:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_1 4.903
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(3,0) 1 \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_TimeOut:TimerUDB:control_7\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.863
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_1 5.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(3,0) 1 \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_TimeOut:TimerUDB:control_7\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.981
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 6.096
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.826
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 6.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.957
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 7.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.826
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 7.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.957
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 8.630
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(3,0) 1 \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_TimeOut:TimerUDB:control_7\ \Timer_TimeOut:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_TimeOut:TimerUDB:status_tc\/main_0 2.992
macrocell24 U(3,0) 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/main_0 \Timer_TimeOut:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/q \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 2.248
statusicell4 U(3,0) 1 \Timer_TimeOut:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 9.841
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:status_tc\/main_1 2.973
macrocell24 U(3,0) 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/main_1 \Timer_TimeOut:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/q \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 2.248
statusicell4 U(3,0) 1 \Timer_TimeOut:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 11.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(2,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/clock \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u0\/z0 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell7 U(3,0) 1 \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0i \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_TimeOut:TimerUDB:per_zero\ \Timer_TimeOut:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_TimeOut:TimerUDB:status_tc\/main_1 2.973
macrocell24 U(3,0) 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/main_1 \Timer_TimeOut:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_TimeOut:TimerUDB:status_tc\ \Timer_TimeOut:TimerUDB:status_tc\/q \Timer_TimeOut:TimerUDB:rstSts:stsreg\/status_0 2.248
statusicell4 U(3,0) 1 \Timer_TimeOut:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_1 4.984
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,2) 1 \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_Scan:TimerUDB:control_7\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.944
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_1 5.126
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,2) 1 \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_Scan:TimerUDB:control_7\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.086
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 6.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.876
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 6.149
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.879
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 7.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.876
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 7.359
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:sT16:timerdp:u0\/cs_addr_0 2.879
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 8.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,2) 1 \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer_Scan:TimerUDB:control_7\ \Timer_Scan:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Scan:TimerUDB:status_tc\/main_0 3.091
macrocell23 U(2,2) 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/main_0 \Timer_Scan:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/q \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 2.323
statusicell3 U(2,2) 1 \Timer_Scan:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 9.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:status_tc\/main_1 2.884
macrocell23 U(2,2) 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/main_1 \Timer_Scan:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/q \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 2.323
statusicell3 U(2,2) 1 \Timer_Scan:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 11.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/clock \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Timer_Scan:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Scan:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell5 U(2,2) 1 \Timer_Scan:TimerUDB:sT16:timerdp:u1\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_Scan:TimerUDB:per_zero\ \Timer_Scan:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Scan:TimerUDB:status_tc\/main_1 2.884
macrocell23 U(2,2) 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/main_1 \Timer_Scan:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Scan:TimerUDB:status_tc\ \Timer_Scan:TimerUDB:status_tc\/q \Timer_Scan:TimerUDB:rstSts:stsreg\/status_0 2.323
statusicell3 U(2,2) 1 \Timer_Scan:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_1740/q Pin_PWMOut(0)_PAD 29.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,1) 1 Net_1740 Net_1740/clock_0 Net_1740/q 1.250
Route 1 Net_1740 Net_1740/q Net_320/main_3 3.703
macrocell4 U(2,2) 1 Net_320 Net_320/main_3 Net_320/q 3.350
Route 1 Net_320 Net_320/q Pin_PWMOut(0)/pin_input 5.830
iocell7 P12[0] 1 Pin_PWMOut(0) Pin_PWMOut(0)/pin_input Pin_PWMOut(0)/pad_out 15.855
Route 1 Pin_PWMOut(0)_PAD Pin_PWMOut(0)/pad_out Pin_PWMOut(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Sync_2:genblk1[0]:INST\/out Net_1740/ap_0 222.420 MHz 4.496 37.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.480
Route 1 Net_744 \Sync_2:genblk1[0]:INST\/out Net_1740/ap_0 3.016
macrocell2 U(2,1) 1 Net_1740 RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Sync_2:genblk1[0]:INST\/out Net_1740/ap_0 4.016
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,0) 1 \Sync_2:genblk1[0]:INST\ \Sync_2:genblk1[0]:INST\/clock \Sync_2:genblk1[0]:INST\/out 1.000
Route 1 Net_744 \Sync_2:genblk1[0]:INST\/out Net_1740/ap_0 3.016
macrocell2 U(2,1) 1 Net_1740 REMOVAL 0.000
Clock Skew 0.000