Static Timing Analysis

Project : MUXtest
Build Time : 02/09/12 16:13:50
Device : CY8C3866AXI-040
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk Sync 4.800 MHz 4.800 MHz N/A
ADC_theACLK Sync 1.263 MHz 1.263 MHz N/A
ClockBlock/aclk_0 Async 1.263 MHz 1.263 MHz N/A
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
ClockBlock/dclk_0 Async 4.800 MHz 4.800 MHz N/A
ClockBlock/dclk_1 Async 153.846 kHz 153.846 kHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
UART_1_IntClock Sync 153.846 kHz 153.846 kHz 44.258 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 6500ns(153.846 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.258 MHz 22.595 6477.405
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.184
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell2 U(2,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.508 MHz 21.974 6478.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.563
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell2 U(2,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.514 MHz 21.499 6478.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 3.088
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell2 U(2,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.797 MHz 21.369 6478.631
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 2.958
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell2 U(2,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 50.163 MHz 19.935 6480.065
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 2.310
macrocell4 U(3,1) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.305
datapathcell1 U(3,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 61.831 MHz 16.173 6483.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 3.649
macrocell8 U(2,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.324
statusicell1 U(3,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 76.371 MHz 13.094 6486.906
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 7.280
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.304
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxSts\/status_0 78.877 MHz 12.678 6487.322
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_status_0\/main_1 4.184
macrocell8 U(2,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_1 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.324
statusicell1 U(3,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_state_0\/main_2 80.392 MHz 12.439 6487.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_state_0\/main_2 3.649
macrocell5 U(2,1) 1 \UART_1:BUART:tx_state_0\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 81.202 MHz 12.315 6487.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 4.775
datapathcell1 U(3,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.836
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.586
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_0\/main_4 4.208
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_0\/main_4 2.958
macrocell5 U(2,1) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_2 4.223
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_2 2.973
macrocell6 U(2,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 4.223
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 2.973
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_0\/main_3 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_0\/main_3 3.088
macrocell5 U(2,1) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_1\/main_3 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_1\/main_3 3.088
macrocell6 U(2,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_2\/main_3 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_2\/main_3 3.088
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_5 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_5 3.088
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_2\/main_2 4.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_2\/main_2 3.095
macrocell7 U(3,1) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_1\/main_0 4.656
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
macrocell6 U(2,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_1\/main_0 3.406
macrocell6 U(2,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 30.508
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_92/main_0 2.587
macrocell1 U(2,1) 1 Net_92 Net_92/main_0 Net_92/q 3.350
Route 1 Net_92 Net_92/q Tx_1(0)/pin_input 7.121
iocell P1[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.200
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000