Static Timing Analysis

Project : testofcom
Build Time : 10/01/15 20:22:00
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
UART_1_IntClock CyMASTER_CLK 461.538 kHz 461.538 kHz 43.401 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 51.570 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 51.570 MHz 19.391 22.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.273
macrocell10 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 83.766 MHz 11.938 29.729
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 6.771
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 87.413 MHz 11.440 30.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.273
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 87.413 MHz 11.440 30.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.273
macrocell8 U(3,4) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 94.625 MHz 10.568 31.099
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.401
macrocell11 U(3,5) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 94.625 MHz 10.568 31.099
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.401
macrocell12 U(3,5) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 94.796 MHz 10.549 31.118
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.382
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 2166.67ns(461.538 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.401 MHz 23.041 2143.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,4) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 4.629
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.693 MHz 22.375 2144.292
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.963
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.279 MHz 21.608 2145.059
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 3.196
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.473 MHz 21.518 2145.149
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,5) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.106
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell3 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 48.650 MHz 20.555 2146.112
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 2.926
macrocell19 U(2,4) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.309
datapathcell2 U(2,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 58.716 MHz 17.031 2149.636
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.312
macrocell16 U(3,3) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 4.519
statusicell1 U(3,4) 1 \UART_1:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 59.812 MHz 16.719 2149.948
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 4.008
macrocell10 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.898 MHz 16.695 2149.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,5) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 4.976
macrocell7 U(3,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.899
count7cell U(3,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 60.698 MHz 16.475 2150.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 3.950
macrocell23 U(2,5) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.325
statusicell2 U(2,5) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:rx_address_detected\/q \UART_1:BUART:sRX:RxBitCounter\/load 63.500 MHz 15.748 2150.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,3) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/clock_0 \UART_1:BUART:rx_address_detected\/q 1.250
Route 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_counter_load\/main_0 4.029
macrocell7 U(3,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.899
count7cell U(3,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 7.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.382
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.401
macrocell11 U(3,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.401
macrocell12 U(3,5) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 7.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.273
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.273
macrocell8 U(3,4) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 6.771
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 14.181
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P4[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.657
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.273
macrocell10 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.932
statusicell1 U(3,4) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 2.287
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxShifter:u0\/f0_load 3.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,3) 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/clock_0 \UART_1:BUART:rx_load_fifo\/q 1.250
Route 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxShifter:u0\/f0_load 2.604
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_state_0\/main_8 3.874
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_state_0\/main_8 2.624
macrocell11 U(3,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.888
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.638
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_1\/main_3 4.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,4) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_1\/main_3 2.788
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_5 4.041
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,4) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_5 2.791
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:txn\/main_1 4.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:txn\/main_1 2.881
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_1\/main_0 4.133
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_1\/main_0 2.883
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 4.138
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 2.888
datapathcell2 U(2,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.472
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 3.421
macrocell1 U(2,5) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx_1(0)/pin_input 5.489
iocell4 P4[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.962
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000