Static Timing Analysis

Project : MPU
Build Time : 09/01/16 10:41:02
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
emFile_Clock_1 emFile_Clock_1 -4.156
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(fixed-function) Clock_1(fixed-function) 64.000 kHz 64.000 kHz N/A
Clock_3(routed) Clock_3(routed) 64.000 kHz 64.000 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 12.000 MHz 12.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 72.000 MHz 72.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 72.000 MHz 72.000 MHz 77.101 MHz
emFile_Clock_1 CyMASTER_CLK 72.000 MHz 72.000 MHz 55.417 MHz Frequency
SPIM_IntClock CyMASTER_CLK 2.000 MHz 2.000 MHz 64.404 MHz
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 58.551 MHz
Clock_1 CyMASTER_CLK 64.000 kHz 64.000 kHz N/A
Clock_3 CyMASTER_CLK 64.000 kHz 64.000 kHz N/A
CyPLL_OUT CyPLL_OUT 72.000 MHz 72.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 13.8889ns(72 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)_SYNC/out \UART:BUART:sRX:RxShifter:u0\/route_si 77.101 MHz 12.970 0.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_postpoll\/main_2 2.876
macrocell12 U(3,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.254
datapathcell4 U(2,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 120.700 MHz 8.285 5.604
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 3.755
macrocell47 U(2,1) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 132.205 MHz 7.564 6.325
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.034
macrocell37 U(2,0) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 132.205 MHz 7.564 6.325
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.034
macrocell40 U(2,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 132.398 MHz 7.553 6.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.023
macrocell46 U(2,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 135.026 MHz 7.406 6.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 2.876
macrocell43 U(3,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 135.026 MHz 7.406 6.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 1.020
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 2.876
macrocell44 U(3,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 64.404 MHz 15.527 484.473
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 3.213
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 4.174
datapathcell5 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:TxStsReg\/status_3 64.994 MHz 15.386 484.614
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 3.213
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 6.383
statusicell5 U(3,5) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 66.836 MHz 14.962 485.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.648
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 4.174
datapathcell5 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 66.867 MHz 14.955 485.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.641
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 4.174
datapathcell5 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:TxStsReg\/status_3 67.472 MHz 14.821 485.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.648
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 6.383
statusicell5 U(3,5) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 67.504 MHz 14.814 485.186
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.641
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 6.383
statusicell5 U(3,5) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 68.301 MHz 14.641 485.359
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.327
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 4.174
datapathcell5 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 68.353 MHz 14.630 485.370
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.316
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 4.174
datapathcell5 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:TxStsReg\/status_3 68.966 MHz 14.500 485.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.327
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 6.383
statusicell5 U(3,5) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:TxStsReg\/status_3 69.018 MHz 14.489 485.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.316
macrocell15 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 6.383
statusicell5 U(3,5) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.551 MHz 17.079 1066.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,4) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.980
macrocell8 U(3,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.309
datapathcell3 U(3,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.263 MHz 16.594 1066.739
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.555
macrocell8 U(3,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.309
datapathcell3 U(3,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.732 MHz 16.199 1067.134
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,5) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.100
macrocell8 U(3,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.309
datapathcell3 U(3,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 62.360 MHz 16.036 1067.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,0) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 3.821
macrocell11 U(2,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.531 MHz 15.992 1067.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,5) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.893
macrocell8 U(3,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.309
datapathcell3 U(3,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 65.776 MHz 15.203 1068.130
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,0) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 2.988
macrocell11 U(2,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 67.101 MHz 14.903 1068.430
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,0) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 2.688
macrocell11 U(2,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 67.691 MHz 14.773 1068.560
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(2,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 2.558
macrocell11 U(2,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 70.264 MHz 14.232 1069.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(3,0) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 3.908
macrocell12 U(3,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.254
datapathcell4 U(2,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 70.756 MHz 14.133 1069.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 4.380
macrocell9 U(2,5) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.323
statusicell3 U(2,5) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 13.8889ns(72 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\emFile:SPI0:BSPIM:state_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 55.417 MHz 18.045 -4.156 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,4) 1 \emFile:SPI0:BSPIM:state_1\ \emFile:SPI0:BSPIM:state_1\/clock_0 \emFile:SPI0:BSPIM:state_1\/q 1.250
Route 1 \emFile:SPI0:BSPIM:state_1\ \emFile:SPI0:BSPIM:state_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_1 7.021
macrocell45 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.914
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 56.567 MHz 17.678 -3.789 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \emFile:SPI0:BSPIM:mosi_from_dp\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_3 3.173
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_3 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.285
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 57.399 MHz 17.422 -3.533 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \emFile:SPI0:BSPIM:mosi_from_dp\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_3 2.288
macrocell45 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_3 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.914
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 64.470 MHz 15.511 -1.622 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_3 1.940
Route 1 \emFile:SPI0:BSPIM:count_3\ \emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_5 4.426
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_5 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.285
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 66.081 MHz 15.133 -1.244 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_1 1.940
Route 1 \emFile:SPI0:BSPIM:count_1\ \emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_7 4.048
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_7 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.285
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:state_2\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 66.867 MHz 14.955 -1.066 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,3) 1 \emFile:SPI0:BSPIM:state_2\ \emFile:SPI0:BSPIM:state_2\/clock_0 \emFile:SPI0:BSPIM:state_2\/q 1.250
Route 1 \emFile:SPI0:BSPIM:state_2\ \emFile:SPI0:BSPIM:state_2\/q \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_0 4.560
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_0 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.285
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:state_2\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 66.979 MHz 14.930 -1.041 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,3) 1 \emFile:SPI0:BSPIM:state_2\ \emFile:SPI0:BSPIM:state_2\/clock_0 \emFile:SPI0:BSPIM:state_2\/q 1.250
Route 1 \emFile:SPI0:BSPIM:state_2\ \emFile:SPI0:BSPIM:state_2\/q \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_0 3.906
macrocell45 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_0 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.914
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 67.114 MHz 14.900 -1.011 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_4 1.940
Route 1 \emFile:SPI0:BSPIM:count_4\ \emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_4 3.815
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_4 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.285
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:ld_ident\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 67.847 MHz 14.739 -0.850 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,4) 1 \emFile:SPI0:BSPIM:ld_ident\ \emFile:SPI0:BSPIM:ld_ident\/clock_0 \emFile:SPI0:BSPIM:ld_ident\/q 1.250
Route 1 \emFile:SPI0:BSPIM:ld_ident\ \emFile:SPI0:BSPIM:ld_ident\/q \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_9 3.715
macrocell45 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_9 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.914
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:state_0\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 67.866 MHz 14.735 -0.846 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,3) 1 \emFile:SPI0:BSPIM:state_0\ \emFile:SPI0:BSPIM:state_0\/clock_0 \emFile:SPI0:BSPIM:state_0\/q 1.250
Route 1 \emFile:SPI0:BSPIM:state_0\ \emFile:SPI0:BSPIM:state_0\/q \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_2 4.340
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_2 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.285
macrocell25 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 3.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_1\/main_4 2.876
macrocell43 U(3,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 3.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:pollcount_0\/main_3 2.876
macrocell44 U(3,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_status_3\/main_7 3.023
macrocell46 U(2,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.384
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_0\/main_10 3.034
macrocell37 U(2,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.384
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_state_2\/main_9 3.034
macrocell40 U(2,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 4.105
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_last\/main_0 3.755
macrocell47 U(2,1) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART:BUART:sRX:RxShifter:u0\/route_si 8.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,0) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.350
Route 1 Net_111_SYNCOUT Rx_1(0)_SYNC/out \UART:BUART:rx_postpoll\/main_2 2.876
macrocell12 U(3,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.254
datapathcell4 U(2,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_2 Net_23/main_7 2.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 Net_23/main_7 2.316
macrocell49 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 Net_23/main_5 2.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 Net_23/main_5 2.327
macrocell49 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 Net_23/main_9 3.261
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 Net_23/main_9 2.641
macrocell49 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 Net_23/main_6 3.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 Net_23/main_6 2.648
macrocell49 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(2,2) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell54 U(2,2) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.290
macrocell54 U(2,2) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:state_0\/main_2 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(2,3) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
macrocell52 U(2,3) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:state_0\/main_2 2.303
macrocell52 U(2,3) 1 \SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_2\/main_9 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(3,2) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_2\/main_9 2.306
macrocell50 U(3,2) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_1\/main_9 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(3,2) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_1\/main_9 2.306
macrocell51 U(3,2) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_8 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(3,2) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
macrocell55 U(3,2) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_8 2.306
macrocell55 U(3,2) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 Net_23/main_8 3.833
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 Net_23/main_8 3.213
macrocell49 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.118
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell46 U(2,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.868
statusicell4 U(2,1) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.517
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.327
macrocell34 U(2,5) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.256
macrocell41 U(3,0) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.887
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.267
macrocell41 U(3,0) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:pollcount_1\/main_1 2.887
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:pollcount_1\/main_1 2.267
macrocell43 U(3,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:pollcount_0\/main_1 2.887
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:pollcount_0\/main_1 2.267
macrocell44 U(3,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.892
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.272
macrocell41 U(3,0) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_1\/main_0 2.892
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_1\/main_0 2.272
macrocell43 U(3,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_0\/main_0 2.892
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_0\/main_0 2.272
macrocell44 U(3,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.684
macrocell38 U(2,0) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:state_2\/main_7 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_0 0.620
Route 1 \emFile:SPI0:BSPIM:count_0\ \emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:state_2\/main_7 2.619
macrocell20 U(3,3) 1 \emFile:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:state_0\/main_7 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_0 0.620
Route 1 \emFile:SPI0:BSPIM:count_0\ \emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:state_0\/main_7 2.619
macrocell22 U(3,3) 1 \emFile:SPI0:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\emFile:Net_1\/q \emFile:Net_1\/main_3 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,3) 1 \emFile:Net_1\ \emFile:Net_1\/clock_0 \emFile:Net_1\/q 1.250
macrocell23 U(3,3) 1 \emFile:Net_1\ \emFile:Net_1\/q \emFile:Net_1\/main_3 2.293
macrocell23 U(3,3) 1 \emFile:Net_1\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:mosi_hs_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_4 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,5) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ \emFile:SPI0:BSPIM:mosi_hs_reg\/clock_0 \emFile:SPI0:BSPIM:mosi_hs_reg\/q 1.250
macrocell24 U(3,5) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ \emFile:SPI0:BSPIM:mosi_hs_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_4 2.294
macrocell24 U(3,5) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:mosi_from_dp_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_5 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,5) 1 \emFile:SPI0:BSPIM:mosi_from_dp_reg\ \emFile:SPI0:BSPIM:mosi_from_dp_reg\/clock_0 \emFile:SPI0:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \emFile:SPI0:BSPIM:mosi_from_dp_reg\ \emFile:SPI0:BSPIM:mosi_from_dp_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_5 2.308
macrocell24 U(3,5) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:state_2\/main_4 3.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_3 0.620
Route 1 \emFile:SPI0:BSPIM:count_3\ \emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:state_2\/main_4 2.939
macrocell20 U(3,3) 1 \emFile:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:state_0\/main_4 3.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_3 0.620
Route 1 \emFile:SPI0:BSPIM:count_3\ \emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:state_0\/main_4 2.939
macrocell22 U(3,3) 1 \emFile:SPI0:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:load_cond\/q \emFile:SPI0:BSPIM:load_cond\/main_8 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,2) 1 \emFile:SPI0:BSPIM:load_cond\ \emFile:SPI0:BSPIM:load_cond\/clock_0 \emFile:SPI0:BSPIM:load_cond\/q 1.250
macrocell26 U(3,2) 1 \emFile:SPI0:BSPIM:load_cond\ \emFile:SPI0:BSPIM:load_cond\/q \emFile:SPI0:BSPIM:load_cond\/main_8 2.314
macrocell26 U(3,2) 1 \emFile:SPI0:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_2\/main_5 3.577
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_2 0.620
Route 1 \emFile:SPI0:BSPIM:count_2\ \emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_2\/main_5 2.957
macrocell20 U(3,3) 1 \emFile:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_0\/main_5 3.577
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_2 0.620
Route 1 \emFile:SPI0:BSPIM:count_2\ \emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_0\/main_5 2.957
macrocell22 U(3,3) 1 \emFile:SPI0:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_IntClock
Source Destination Delay (ns)
MISO_1(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 15.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO_1(0)_PAD MISO_1(0)_PAD MISO_1(0)/pad_in 0.000
iocell10 P3[0] 1 MISO_1(0) MISO_1(0)/pad_in MISO_1(0)/fb 6.324
Route 1 Net_19 MISO_1(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 5.975
datapathcell5 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ emFile_Clock_1
Source Destination Delay (ns)
\emFile:miso0(0)_PAD\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/route_si 16.682
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 \emFile:miso0(0)_PAD\ \emFile:miso0(0)_PAD\ \emFile:miso0(0)\/pad_in 0.000
iocell3 P0[0] 1 \emFile:miso0(0)\ \emFile:miso0(0)\/pad_in \emFile:miso0(0)\/fb 7.922
Route 1 \emFile:Net_16\ \emFile:miso0(0)\/fb \emFile:SPI0:BSPIM:sR8:Dp:u0\/route_si 5.260
datapathcell1 U(3,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
DMA_RX/termout Pin_1(0)_PAD 27.335
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell2 [DrqContainer=(0)][DrqId=(0)] 1 DMA_RX DMA_RX/clock DMA_RX/termout 9.000
Route 1 Net_218 DMA_RX/termout Pin_1(0)/pin_input 2.876
iocell12 P0[2] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.459
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ SPIM_IntClock
Source Destination Delay (ns)
Net_25/q SCLK_1(0)_PAD 23.813
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell48 U(2,2) 1 Net_25 Net_25/clock_0 Net_25/q 1.250
Route 1 Net_25 Net_25/q SCLK_1(0)/pin_input 7.576
iocell9 P3[4] 1 SCLK_1(0) SCLK_1(0)/pin_input SCLK_1(0)/pad_out 14.987
Route 1 SCLK_1(0)_PAD SCLK_1(0)/pad_out SCLK_1(0)_PAD 0.000
Clock Clock path delay 0.000
Net_430/q CS_pin(0)_PAD 23.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell53 U(2,2) 1 Net_430 Net_430/clock_0 Net_430/q 1.250
Route 1 Net_430 Net_430/q CS_pin(0)/pin_input 7.659
iocell11 P3[3] 1 CS_pin(0) CS_pin(0)/pin_input CS_pin(0)/pad_out 14.591
Route 1 CS_pin(0)_PAD CS_pin(0)/pad_out CS_pin(0)_PAD 0.000
Clock Clock path delay 0.000
Net_23/q MOSI_1(0)_PAD 23.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(3,1) 1 Net_23 Net_23/clock_0 Net_23/q 1.250
Route 1 Net_23 Net_23/q MOSI_1(0)/pin_input 6.918
iocell8 P3[1] 1 MOSI_1(0) MOSI_1(0)/pin_input MOSI_1(0)/pad_out 14.979
Route 1 MOSI_1(0)_PAD MOSI_1(0)/pad_out MOSI_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 35.019
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,4) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_106/main_0 6.013
macrocell7 U(2,1) 1 Net_106 Net_106/main_0 Net_106/q 3.350
Route 1 Net_106 Net_106/q Tx_1(0)/pin_input 7.439
iocell7 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ emFile_Clock_1
Source Destination Delay (ns)
\emFile:SPI0:BSPIM:state_2\/q \emFile:mosi0(0)_PAD\ 31.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,3) 1 \emFile:SPI0:BSPIM:state_2\ \emFile:SPI0:BSPIM:state_2\/clock_0 \emFile:SPI0:BSPIM:state_2\/q 1.250
Route 1 \emFile:SPI0:BSPIM:state_2\ \emFile:SPI0:BSPIM:state_2\/q \emFile:Net_10\/main_0 5.490
macrocell3 U(3,5) 1 \emFile:Net_10\ \emFile:Net_10\/main_0 \emFile:Net_10\/q 3.350
Route 1 \emFile:Net_10\ \emFile:Net_10\/q \emFile:mosi0(0)\/pin_input 5.737
iocell2 P0[1] 1 \emFile:mosi0(0)\ \emFile:mosi0(0)\/pin_input \emFile:mosi0(0)\/pad_out 15.802
Route 1 \emFile:mosi0(0)_PAD\ \emFile:mosi0(0)\/pad_out \emFile:mosi0(0)_PAD\ 0.000
Clock Clock path delay 0.000
\emFile:Net_22\/q \emFile:sclk0(0)_PAD\ 23.874
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(3,1) 1 \emFile:Net_22\ \emFile:Net_22\/clock_0 \emFile:Net_22\/q 1.250
Route 1 \emFile:Net_22\ \emFile:Net_22\/q \emFile:sclk0(0)\/pin_input 7.601
iocell4 P0[5] 1 \emFile:sclk0(0)\ \emFile:sclk0(0)\/pin_input \emFile:sclk0(0)\/pad_out 15.023
Route 1 \emFile:sclk0(0)_PAD\ \emFile:sclk0(0)\/pad_out \emFile:sclk0(0)_PAD\ 0.000
Clock Clock path delay 0.000