Static Timing Analysis

Project : SPIM_Example01
Build Time : 08/29/16 17:26:43
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock CyMASTER_CLK 2.000 MHz 2.000 MHz 64.074 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:RxStsReg\/status_6 64.074 MHz 15.607 484.393
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \SPIM:BSPIM:rx_status_4\ \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:rx_status_6\/main_5 5.916
macrocell4 U(3,0) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_5 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.261
statusicell2 U(2,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 72.780 MHz 13.740 486.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.963
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 72.865 MHz 13.724 486.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.947
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 73.681 MHz 13.572 486.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.795
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 73.697 MHz 13.569 486.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.792
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 74.555 MHz 13.413 486.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.636
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 82.597 MHz 12.107 487.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.963
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.354
statusicell1 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:TxStsReg\/status_3 82.706 MHz 12.091 487.909
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.947
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.354
statusicell1 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:TxStsReg\/status_3 83.759 MHz 11.939 488.061
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.795
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.354
statusicell1 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:TxStsReg\/status_3 83.780 MHz 11.936 488.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.792
macrocell1 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.354
statusicell1 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_2\/main_4 3.247
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_2\/main_4 2.627
macrocell7 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_1\/main_4 3.247
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_1\/main_4 2.627
macrocell8 U(3,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:ld_ident\/main_4 3.247
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:ld_ident\/main_4 2.627
macrocell11 U(3,1) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 Net_30/main_6 3.256
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 Net_30/main_6 2.636
macrocell6 U(3,1) 1 Net_30 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 2.791
macrocell7 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 2.791
macrocell8 U(3,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:ld_ident\/main_6 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:ld_ident\/main_6 2.791
macrocell11 U(3,1) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 Net_30/main_7 3.412
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 Net_30/main_7 2.792
macrocell6 U(3,1) 1 Net_30 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 3.412
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 2.792
macrocell7 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_1\/main_5 3.412
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_1\/main_5 2.792
macrocell8 U(3,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock
Source Destination Delay (ns)
miso(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 15.809
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 miso(0)_PAD miso(0)_PAD miso(0)/pad_in 0.000
iocell11 P3[0] 1 miso(0) miso(0)/pad_in miso(0)/fb 6.324
Route 1 Net_13 miso(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 5.985
datapathcell1 U(3,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock
Source Destination Delay (ns)
Net_31/q sclk(0)_PAD 22.760
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,0) 1 Net_31 Net_31/clock_0 Net_31/q 1.250
Route 1 Net_31 Net_31/q sclk(0)/pin_input 6.523
iocell9 P3[4] 1 sclk(0) sclk(0)/pin_input sclk(0)/pad_out 14.987
Route 1 sclk(0)_PAD sclk(0)/pad_out sclk(0)_PAD 0.000
Clock Clock path delay 0.000
Net_15/q CS_pin(0)_PAD 22.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,0) 1 Net_15 Net_15/clock_0 Net_15/q 1.250
Route 1 Net_15 Net_15/q CS_pin(0)/pin_input 6.519
iocell8 P3[3] 1 CS_pin(0) CS_pin(0)/pin_input CS_pin(0)/pad_out 14.591
Route 1 CS_pin(0)_PAD CS_pin(0)/pad_out CS_pin(0)_PAD 0.000
Clock Clock path delay 0.000
Net_30/q mosi(0)_PAD 22.243
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,1) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q mosi(0)/pin_input 6.014
iocell10 P3[1] 1 mosi(0) mosi(0)/pin_input mosi(0)/pad_out 14.979
Route 1 mosi(0)_PAD mosi(0)/pad_out mosi(0)_PAD 0.000
Clock Clock path delay 0.000